1 /* 2 * Copyright (c) 2006-2024, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-03-21 qiujingbao the first version 9 */ 10 11 #include <rtthread.h> 12 #include <rtdevice.h> 13 14 15 #define DBG_TAG "DRV.POR" 16 #define DBG_LVL DBG_WARNING 17 #include <rtdbg.h> 18 19 #include "mmio.h" 20 #include "drv_ioremap.h" 21 22 static rt_ubase_t _cvi_rtc_ctrl_base = 0x05025000U; 23 static rt_ubase_t _cvi_rtc_reg_base = 0x05026000U; 24 25 #define CVI_RTC_CTRL_BASE _cvi_rtc_ctrl_base 26 #define CVI_RTC_REG_BASE _cvi_rtc_reg_base 27 #define RTC_CTRL0_UNLOCKKEY 0x4 28 #define RTC_CTRL0 0x8 29 #define RTC_APB_BUSY_SEL 0x3C 30 #define RTC_EN_WARM_RST_REQ 0xCC 31 #define RSM_STATE 0xD4 32 #define ST_ON 0x3 33 cvi_restart(void)34static int cvi_restart(void) 35 { 36 /* Enable power suspend wakeup source mask */ 37 mmio_write_32(CVI_RTC_REG_BASE + RTC_APB_BUSY_SEL,0x1); 38 39 /* unlock register */ 40 mmio_write_32(CVI_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18); 41 42 mmio_write_32(CVI_RTC_REG_BASE + RTC_EN_WARM_RST_REQ, 0x1); 43 44 while (mmio_read_32(CVI_RTC_REG_BASE + RTC_EN_WARM_RST_REQ) != 0x01); 45 46 while (mmio_read_32(CVI_RTC_REG_BASE + RSM_STATE) != ST_ON); 47 48 mmio_write_32( CVI_RTC_CTRL_BASE + RTC_CTRL0,0xFFFF0800 | (0x1 << 4)); 49 50 return 0; 51 } 52 rt_hw_cpu_reset(void)53void rt_hw_cpu_reset(void) 54 { 55 rt_kprintf("Rebooting...\n"); 56 57 _cvi_rtc_ctrl_base = (rt_ubase_t)DRV_IOREMAP((void *)_cvi_rtc_ctrl_base, 0x1000); 58 _cvi_rtc_reg_base = (rt_ubase_t)DRV_IOREMAP((void *)_cvi_rtc_reg_base, 0x1000); 59 60 cvi_restart(); 61 62 rt_kprintf("ERROR: Failed to reboot the system\n"); 63 while (1); 64 } 65 66 MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); 67