1 /*
2  * Copyright (c) 2006-2024, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2023/06/25     flyingcys    first version
9  */
10 #ifndef __DRV_USART_H__
11 #define __DRV_USART_H__
12 
13 #include <rtthread.h>
14 #include "rtdevice.h"
15 #include <rthw.h>
16 
17 #include "pinctrl.h"
18 #include "mmio.h"
19 
20 #define UART_REG_SHIFT      0x2     /* Register Shift*/
21 #define UART_INPUT_CLK      25000000
22 
23 #define UART0_BASE          0x04140000
24 #define UART1_BASE          0x04150000
25 #define UART2_BASE          0x04160000
26 #define UART3_BASE          0x04170000
27 #define UART4_BASE          0x041C0000
28 
29 #define UART0_IRQ           (BSP_UART_IRQ_BASE + 0)
30 #define UART1_IRQ           (BSP_UART_IRQ_BASE + 1)
31 #define UART2_IRQ           (BSP_UART_IRQ_BASE + 2)
32 #define UART3_IRQ           (BSP_UART_IRQ_BASE + 3)
33 #define UART4_IRQ           (BSP_UART_IRQ_BASE + 4)
34 
35 /*
36  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
37  * LCR is written whilst busy. If it is, then a busy detect interrupt is
38  * raised, the LCR needs to be rewritten and the uart status register read.
39  */
40 
41 #define UART_RX             0    /* In: Receive buffer */
42 #define UART_TX             0    /* Out: Transmit buffer */
43 
44 #define UART_DLL            0    /* Out: Divisor Latch Low */
45 #define UART_DLM            1    /* Out: Divisor Latch High */
46 
47 #define UART_IER            1    /* Out: Interrupt Enable Register */
48 #define UART_IER_RDI        0x01 /* Enable receiver data interrupt */
49 
50 #define UART_SSR            0x22 /* In: Software Reset Register */
51 #define UART_USR            0x1f /* UART Status Register */
52 
53 #define UART_IIR            2    /* In: Interrupt ID Register */
54 #define UART_IIR_NO_INT     0x01 /* No interrupts pending */
55 #define UART_IIR_BUSY       0x07 /* DesignWare APB Busy Detect */
56 #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
57 
58 #define UART_FCR            2    /* Out: FIFO Control Register */
59 #define UART_FCR_FIFO_EN    0x01 /* Fifo enable */
60 #define UART_FCR_RXSR       0x02 /* Receiver soft reset */
61 #define UART_FCR_TXSR       0x04 /* Transmitter soft reset */
62 
63 #define UART_LCR            3    /* Out: Line Control Register */
64 #define UART_LCR_WLS_MSK    0x03 /* character length select mask */
65 #define UART_LCR_WLS_5      0x00 /* 5 bit character length */
66 #define UART_LCR_WLS_6      0x01 /* 6 bit character length */
67 #define UART_LCR_WLS_7      0x02 /* 7 bit character length */
68 #define UART_LCR_WLS_8      0x03 /* 8 bit character length */
69 #define UART_LCR_STB        0x04 /* # stop Bits, off=1, on=1.5 or 2) */
70 #define UART_LCR_PEN        0x08 /* Parity eneble */
71 #define UART_LCR_EPS        0x10 /* Even Parity Select */
72 #define UART_LCR_STKP       0x20 /* Stick Parity */
73 #define UART_LCR_SBRK       0x40 /* Set Break */
74 #define UART_LCR_BKSE       0x80 /* Bank select enable */
75 #define UART_LCR_DLAB       0x80 /* Divisor latch access bit */
76 
77 
78 #define UART_MCR            4    /* Out: Modem Control Register */
79 #define UART_MCR_DTR        0x01 /* DTR   */
80 #define UART_MCR_RTS        0x02 /* RTS   */
81 
82 #define UART_LSR            5    /* In: Line Status Register */
83 #define UART_LSR_BI         0x10 /* Break interrupt indicator */
84 #define UART_LSR_DR         0x01 /* Receiver data ready */
85 #define UART_LSR_TEMT       0x40 /* Transmitter empty */
86 #define UART_LSR_THRE       0x20 /* Transmit-hold-register empty */
87 
88 #define UART_MCRVAL         (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
89 
90 /* Clear & enable FIFOs */
91 #define UART_FCR_DEFVAL     (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
92 
93 #define UART_LCR_8N1        0x03
94 
95 int rt_hw_uart_init(void);
96 
97 #endif  /* __DRV_USART_H__ */
98