1 #ifndef __CVI_PWM_H__
2 #define __CVI_PWM_H__
3
4 #include <stdio.h>
5
6 #ifdef __cplusplus
7 extern "C" {
8 #endif
9
10 #define __IM volatile const /*! Defines 'read only' structure member permissions */
11 #define __OM volatile /*! Defines 'write only' structure member permissions */
12 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
13
14 #define CVI_PWM0_BASE 0x03060000
15 #define CVI_PWM1_BASE 0x03061000
16 #define CVI_PWM2_BASE 0x03062000
17 #define CVI_PWM3_BASE 0x03063000
18
19 typedef enum {
20 PWM_CHANNEL_0 = 0U,
21 PWM_CHANNEL_1,
22 PWM_CHANNEL_2,
23 PWM_CHANNEL_3,
24 PWM_CHANNEL_4,
25 PWM_CHANNEL_5,
26 PWM_CHANNEL_6,
27 PWM_CHANNEL_7,
28 PWM_CHANNEL_8,
29 PWM_CHANNEL_9,
30 PWM_CHANNEL_10,
31 PWM_CHANNEL_11,
32 PWM_CHANNEL_12,
33 PWM_CHANNEL_13,
34 PWM_CHANNEL_14,
35 PWM_CHANNEL_15,
36 PWM_CHANNEL_NUM
37 } cvi_pwm_channel_t;
38
39
40 struct cvi_pwm_regs_t {
41 uint32_t HLPERIOD0;
42 uint32_t PERIOD0;
43 uint32_t HLPERIOD1;
44 uint32_t PERIOD1;
45 uint32_t HLPERIOD2;
46 uint32_t PERIOD2;
47 uint32_t HLPERIOD3;
48 uint32_t PERIOD3;
49 uint32_t CAP_FREQNUM;
50 uint32_t CAP_FREQDATA;
51 uint32_t POLARITY;
52 uint32_t PWMSTART;
53 uint32_t PWMDONE;
54 uint32_t PWMUPDATE;
55 uint32_t PCOUNT0;
56 uint32_t PCOUNT1;
57 uint32_t PCOUNT2;
58 uint32_t PCOUNT3;
59 uint32_t PULSECOUNT0;
60 uint32_t PULSECOUNT1;
61 uint32_t PULSECOUNT2;
62 uint32_t PULSECOUNT3;
63 uint32_t SHIFTCOUNT0;
64 uint32_t SHIFTCOUNT1;
65 uint32_t SHIFTCOUNT2;
66 uint32_t SHIFTCOUNT3;
67 uint32_t SHIFTSTART;
68 uint32_t CAP_FREQEN;
69 uint32_t CAP_FREQDONE_NUM;
70 uint32_t PWM_OE;
71 };
72
73
74 static struct cvi_pwm_regs_t cv182x_pwm_reg = {
75 .HLPERIOD0 = 0x0,
76 .PERIOD0 = 0x4,
77 .HLPERIOD1 = 0x8,
78 .PERIOD1 = 0xc,
79 .HLPERIOD2 = 0x10,
80 .PERIOD2 = 0x14,
81 .HLPERIOD3 = 0x18,
82 .PERIOD3 = 0x1c,
83 .CAP_FREQNUM = 0x20,
84 .CAP_FREQDATA = 0x24,
85 .POLARITY = 0x40,
86 .PWMSTART = 0x44,
87 .PWMDONE = 0x48,
88 .PWMUPDATE = 0x4c,
89 .PCOUNT0 = 0x50,
90 .PCOUNT1 = 0x54,
91 .PCOUNT2 = 0x58,
92 .PCOUNT3 = 0x5c,
93 .PULSECOUNT0 = 0x60,
94 .PULSECOUNT1 = 0x64,
95 .PULSECOUNT2 = 0x68,
96 .PULSECOUNT3 = 0x6c,
97 .SHIFTCOUNT0 = 0x80,
98 .SHIFTCOUNT1 = 0x84,
99 .SHIFTCOUNT2 = 0x88,
100 .SHIFTCOUNT3 = 0x8c,
101 .SHIFTSTART = 0x90,
102 .CAP_FREQEN = 0x9c,
103 .CAP_FREQDONE_NUM = 0xC0,
104 .PWM_OE = 0xd0,
105 };
106
107 static struct cvi_pwm_regs_t *cvi_pwm_reg = &cv182x_pwm_reg;
108
109 #define PWM_HLPERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0))
110 #define PWM_PERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0))
111 #define PWM_HLPERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD1))
112 #define PWM_PERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD1))
113 #define PWM_HLPERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD2))
114 #define PWM_PERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD2))
115 #define PWM_HLPERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD3))
116 #define PWM_PERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD3))
117 #define PWM_HLPERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0 + (_ch_ << 3)))
118 #define PWM_PERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0 * (1 + (_ch_ << 1))))
119
120 #define CAP_FREQNUM(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQNUM + _ch_ * 8))
121 #define CAP_FREQDATA(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDATA + _ch_ * 8))
122
123 #define PWM_POLARITY(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->POLARITY))
124 #define PWM_PWMSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMSTART))
125 #define PWM_PWMDONE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMDONE))
126 #define PWM_PWMUPDATE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMUPDATE))
127
128 #define PWM_PCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT0))
129 #define PWM_PCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT1))
130 #define PWM_PCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT2))
131 #define PWM_PCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT3))
132
133 #define PWM_PULSECOUNT0(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT0))
134 #define PWM_PULSECOUNT1(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT1))
135 #define PWM_PULSECOUNT2(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT2))
136 #define PWM_PULSECOUNT3(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT3))
137
138 #define PWM_SHIFTCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT0))
139 #define PWM_SHIFTCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT1))
140 #define PWM_SHIFTCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT2))
141 #define PWM_SHIFTCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT3))
142 #define PWM_SHIFTSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTSTART))
143
144 #define CAP_FREQEN(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQEN))
145 #define CAP_FREQDONE_NUM(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDONE_NUM + _ch_ * 4))
146
147 #define PWM_PWM_OE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWM_OE))
148
149
150 /*! PWM Configure Register, offset: 0x00 */
151 #define CVI_PWM_HIGH_PERIOD_Pos (0U)
152 #define CVI_PWM_HIGH_PERIOD_Msk (0xffffffff)
153
154 #define CVI_PWM_PERIOD_Pos (0U)
155 #define CVI_PWM_PERIOD_Msk (0xffffffff)
156
157 #define CVI_PWM_POLARITY_CH_Pos(_ch_) (_ch_)
158 #define CVI_PWM_POLARITY_CH_Msk(_ch_) (1U << CVI_PWM_POLARITY_CH_Pos(_ch_))
159 #define CVI_PWM_POLARITY_CH_HIGH(_ch_) CVI_PWM_POLARITY_CH_Msk(_ch_)
160
161 #define CVI_PWM_START_CH_Pos(_ch_) (_ch_)
162 #define CVI_PWM_START_CH_Msk(_ch_) (1U << CVI_PWM_START_CH_Pos(_ch_))
163 #define CVI_PWM_START_CH_EN(_ch_) CVI_PWM_START_CH_Msk(_ch_)
164
165 #define CVI_PWM_OUTPUT_CH_Pos(_ch_) (_ch_)
166 #define CVI_PWM_OUTPUT_CH_Msk(_ch_) (1U << CVI_PWM_OUTPUT_CH_Pos(_ch_))
167 #define CVI_PWM_OUTPUT_CH_EN(_ch_) CVI_PWM_OUTPUT_CH_Msk(_ch_)
168
169 #define CVI_CAP_FREQNUM_CH_Pos (0U)
170 #define CVI_CAP_FREQNUM_CH_Msk (0xffffffff)
171
172 #define CVI_CAP_FREQEN_Pos(_ch_) (_ch_)
173 #define CVI_CAP_FREQEN_Msk(_ch_) (1U << CVI_CAP_FREQEN_Pos(_ch_))
174 #define CVI_CAP_FREQEN(_ch_) CVI_CAP_FREQEN_Msk(_ch_)
175
176 #define CVI_CAP_FREQDONE_NUM_Poa (0U)
177 #define CVI_CAP_FREQDONE_NUM_Msk (0xffffffff)
178
179 #define CVI_CAP_FREQDATA_pos (0U)
180 #define CVI_CAP_FREQDATA_msk (0xffffffff)
181
cvi_pwm_set_high_period_ch(unsigned long reg_base,uint32_t ch,unsigned long long value)182 static inline void cvi_pwm_set_high_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value)
183 {
184 PWM_HLPERIODX(reg_base, ch) = value;
185 }
186
cvi_pwm_get_high_period_ch(unsigned long reg_base,uint32_t ch)187 static inline unsigned long long cvi_pwm_get_high_period_ch(unsigned long reg_base, uint32_t ch)
188 {
189 return PWM_HLPERIODX(reg_base, ch);
190 }
191
cvi_pwm_set_period_ch(unsigned long reg_base,uint32_t ch,unsigned long long value)192 static inline void cvi_pwm_set_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value)
193 {
194 PWM_PERIODX(reg_base, ch) = value;
195 }
196
cvi_pwm_get_period_ch(unsigned long reg_base,uint32_t ch)197 static inline unsigned long long cvi_pwm_get_period_ch(unsigned long reg_base, uint32_t ch)
198 {
199 return PWM_PERIODX(reg_base, ch);
200 }
201
cvi_pwm_set_polarity_high_ch(unsigned long reg_base,uint32_t ch)202 static inline void cvi_pwm_set_polarity_high_ch(unsigned long reg_base, uint32_t ch)
203 {
204 PWM_POLARITY(reg_base) |= CVI_PWM_POLARITY_CH_HIGH(ch);
205 }
206
cvi_pwm_set_polarity_low_ch(unsigned long reg_base,uint32_t ch)207 static inline void cvi_pwm_set_polarity_low_ch(unsigned long reg_base, uint32_t ch)
208 {
209 PWM_POLARITY(reg_base) &= ~CVI_PWM_POLARITY_CH_HIGH(ch);
210 }
211
cvi_pwm_get_polarity(unsigned long reg_base,uint32_t ch)212 static inline uint32_t cvi_pwm_get_polarity(unsigned long reg_base, uint32_t ch)
213 {
214 return (PWM_POLARITY(reg_base) & CVI_PWM_POLARITY_CH_Msk(ch));
215 }
216
cvi_pwm_start_en_ch(unsigned long reg_base,uint32_t ch)217 static inline void cvi_pwm_start_en_ch(unsigned long reg_base, uint32_t ch)
218 {
219 PWM_PWMSTART(reg_base) |= CVI_PWM_START_CH_EN(ch);
220 }
221
cvi_pwm_start_dis_ch(unsigned long reg_base,uint32_t ch)222 static inline void cvi_pwm_start_dis_ch(unsigned long reg_base, uint32_t ch)
223 {
224 PWM_PWMSTART(reg_base) &= ~CVI_PWM_START_CH_EN(ch);
225 }
226
cvi_pwm_output_en_ch(unsigned long reg_base,uint32_t ch)227 static inline void cvi_pwm_output_en_ch(unsigned long reg_base, uint32_t ch)
228 {
229 PWM_PWM_OE(reg_base) |= CVI_PWM_OUTPUT_CH_EN(ch);
230 }
231
cvi_pwm_input_en_ch(unsigned long reg_base,uint32_t ch)232 static inline void cvi_pwm_input_en_ch(unsigned long reg_base, uint32_t ch)
233 {
234 PWM_PWM_OE(reg_base) &= ~CVI_PWM_OUTPUT_CH_EN(ch);
235 }
236
cvi_cap_set_freqnum_ch(unsigned long reg_base,uint32_t ch,uint32_t value)237 static inline void cvi_cap_set_freqnum_ch(unsigned long reg_base, uint32_t ch, uint32_t value)
238 {
239 CAP_FREQNUM(reg_base, ch) = value;
240 }
241
cvi_cap_freq_en_ch(unsigned long reg_base,uint32_t ch)242 static inline void cvi_cap_freq_en_ch(unsigned long reg_base, uint32_t ch)
243 {
244 CAP_FREQEN(reg_base) |= CVI_CAP_FREQEN(ch);
245 }
246
cvi_cap_freq_dis_ch(unsigned long reg_base,uint32_t ch)247 static inline void cvi_cap_freq_dis_ch(unsigned long reg_base, uint32_t ch)
248 {
249 CAP_FREQEN(reg_base) &= ~CVI_CAP_FREQEN(ch);
250 }
251
cvi_cap_get_freq_done_num_ch(unsigned long reg_base,uint32_t ch)252 static inline uint32_t cvi_cap_get_freq_done_num_ch(unsigned long reg_base, uint32_t ch)
253 {
254 return CAP_FREQDONE_NUM(reg_base, ch);
255 }
256
cvi_cap_get_freq_data_ch(unsigned long reg_base,uint32_t ch)257 static inline uint32_t cvi_cap_get_freq_data_ch(unsigned long reg_base, uint32_t ch)
258 {
259 return CAP_FREQDATA(reg_base, ch);
260 }
261
262 #ifdef __cplusplus
263 }
264 #endif
265
266 #endif
267