1 /*
2 * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #ifndef __DW_SPI_HEADER_H__
17 #define __DW_SPI_HEADER_H__
18
19 #include "stdint.h"
20 #include "stdbool.h"
21
22 #define SPI_REGBASE 0x04180000
23 #define SPI_REF_CLK 187500000
24 #define MAX_SPI_NUM 4
25
26 #define CVI_DW_SPI_CTRLR0 0x00
27 #define CVI_DW_SPI_CTRLR1 0x04
28 #define CVI_DW_SPI_SSIENR 0x08
29 #define CVI_DW_SPI_MWCR 0x0c
30 #define CVI_DW_SPI_SER 0x10
31 #define CVI_DW_SPI_BAUDR 0x14
32 #define CVI_DW_SPI_TXFTLR 0x18
33 #define CVI_DW_SPI_RXFTLR 0x1c
34 #define CVI_DW_SPI_TXFLR 0x20
35 #define CVI_DW_SPI_RXFLR 0x24
36 #define CVI_DW_SPI_SR 0x28
37 #define CVI_DW_SPI_IMR 0x2c
38 #define CVI_DW_SPI_ISR 0x30
39 #define CVI_DW_SPI_RISR 0x34
40 #define CVI_DW_SPI_TXOICR 0x38
41 #define CVI_DW_SPI_RXOICR 0x3c
42 #define CVI_DW_SPI_RXUICR 0x40
43 #define CVI_DW_SPI_MSTICR 0x44
44 #define CVI_DW_SPI_ICR 0x48
45 #define CVI_DW_SPI_DMACR 0x4c
46 #define CVI_DW_SPI_DMATDLR 0x50
47 #define CVI_DW_SPI_DMARDLR 0x54
48 #define CVI_DW_SPI_IDR 0x58
49 #define CVI_DW_SPI_VERSION 0x5c
50 #define CVI_DW_SPI_DR 0x60
51
52 /* Bit fields in CTRLR0 */
53 #define CVI_SPI_DFS_OFFSET 0
54
55 #define CVI_SPI_FRF_OFFSET 4
56 #define CVI_SPI_FRF_SPI 0x0
57 #define CVI_SPI_FRF_SSP 0x1
58 #define CVI_SPI_FRF_MICROWIRE 0x2
59 #define CVI_SPI_FRF_RESV 0x3
60
61 #define CVI_SPI_MODE_OFFSET 6
62 #define CVI_SPI_SCPH_OFFSET 6
63 #define CVI_SPI_SCOL_OFFSET 7
64
65 #define CVI_SPI_TMOD_OFFSET 8
66 #define CVI_SPI_TMOD_MASK (0x3 << CVI_SPI_TMOD_OFFSET)
67 #define CVI_SPI_TMOD_TR 0x0 /* xmit & recv */
68 #define CVI_SPI_TMOD_TO 0x1 /* xmit only */
69 #define CVI_SPI_TMOD_RO 0x2 /* recv only */
70 #define CVI_SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
71
72 #define CVI_SPI_SLVOE_OFFSET 10
73 #define CVI_SPI_SRL_OFFSET 11
74 #define CVI_SPI_CFS_OFFSET 12
75
76 /* Bit fields in SR, 7 bits */
77 #define CVI_SR_MASK 0x7f
78 #define CVI_SR_BUSY (1 << 0)
79 #define CVI_SR_TF_NOT_FULL (1 << 1)
80 #define CVI_SR_TF_EMPT (1 << 2)
81 #define CVI_SR_RF_NOT_EMPT (1 << 3)
82 #define CVI_SR_RF_FULL (1 << 4)
83 #define CVI_SR_TX_ERR (1 << 5)
84 #define SR_DCOL (1 << 6)
85
86 /* Bit fields in ISR, IMR, RISR, 7 bits */
87 #define CVI_SPI_INT_TXEI (1 << 0)
88 #define CVI_SPI_INT_TXOI (1 << 1)
89 #define CVI_SPI_INT_RXUI (1 << 2)
90 #define CVI_SPI_INT_RXOI (1 << 3)
91 #define CVI_SPI_INT_RXFI (1 << 4)
92 #define CVI_SPI_INT_MSTI (1 << 5)
93
94 /* Bit fields in DMACR */
95 #define CVI_SPI_DMA_RDMAE (1 << 0)
96 #define CVI_SPI_DMA_TDMAE (1 << 1)
97
98 /* TX RX interrupt level threshold, max can be 256 */
99 #define CVI_SPI_INT_THRESHOLD 32
100 #define BITS_PER_BYTE 8
101 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
102
103 struct dw_spi {
104 void *regs;
105 int irq;
106 int index;
107 uint32_t fifo_len; /* depth of the FIFO buffer */
108 uint16_t num_cs; /* supported slave numbers */
109 uint32_t speed_hz;
110 /* Current message transfer state info */
111 size_t len;
112 const void *tx;
113 const void *tx_end;
114 void *rx;
115 void *rx_end;
116 uint32_t rx_len;
117 uint32_t tx_len;
118 uint8_t n_bytes; /* current is a 1/2 bytes op */
119 uint32_t dma_width;
120 int (*transfer_handler)(struct dw_spi *dws);
121
122 /* Bus interface info */
123 void *priv;
124 };
125
126 struct spi_delay {
127 #define SPI_DELAY_UNIT_USECS 0
128 #define SPI_DELAY_UNIT_NSECS 1
129 #define SPI_DELAY_UNIT_SCK 2
130 uint16_t value;
131 uint8_t unit;
132 };
133
134 #define SPI_CPHA 0x01
135 #define SPI_CPOL 0x02
136
137 #define SPI_MODE_0 (0|0)
138 #define SPI_MODE_1 (0|SPI_CPHA)
139 #define SPI_MODE_2 (SPI_CPOL|0)
140 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
141
142 enum transfer_type {
143 POLL_TRAN = 0,
144 IRQ_TRAN,
145 DMA_TRAN,
146 };
147
148 enum dw_ssi_type {
149 SSI_MOTO_SPI = 0,
150 SSI_TI_SSP,
151 SSI_NS_MICROWIRE,
152 };
153
154 #define SPI_FORMAT_CPOL0_CPHA0 0
155 #define SPI_FORMAT_CPOL0_CPHA1 1
156 #define SPI_FORMAT_CPOL1_CPHA0 2
157 #define SPI_FORMAT_CPOL1_CPHA1 3
158
159 #ifndef BIT
160 #define BIT(_n) ( 1 << (_n))
161 #endif
162
dw_writel(struct dw_spi * dws,uint32_t off,uint32_t val)163 static void dw_writel(struct dw_spi *dws, uint32_t off, uint32_t val)
164 {
165 writel(val, (dws->regs + off));
166 }
167
dw_readl(struct dw_spi * dws,uint32_t off)168 static uint32_t dw_readl(struct dw_spi *dws, uint32_t off)
169 {
170 return readl(dws->regs + off);
171 }
172
spi_enable_chip(struct dw_spi * dws,int enable)173 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
174 {
175 dw_writel(dws, CVI_DW_SPI_SSIENR, (enable ? 1 : 0));
176 }
177
spi_set_clk(struct dw_spi * dws,uint16_t div)178 static inline void spi_set_clk(struct dw_spi *dws, uint16_t div)
179 {
180 dw_writel(dws, CVI_DW_SPI_BAUDR, div);
181 }
182
183 /* Disable IRQ bits */
spi_mask_intr(struct dw_spi * dws,uint32_t mask)184 static inline void spi_mask_intr(struct dw_spi *dws, uint32_t mask)
185 {
186 uint32_t new_mask;
187
188 new_mask = dw_readl(dws, CVI_DW_SPI_IMR) & ~mask;
189 dw_writel(dws, CVI_DW_SPI_IMR, new_mask);
190 }
191
spi_get_status(struct dw_spi * dws)192 static inline uint32_t spi_get_status(struct dw_spi *dws)
193 {
194 return dw_readl(dws, CVI_DW_SPI_SR);
195 }
196
197 /* Enable IRQ bits */
spi_umask_intr(struct dw_spi * dws,uint32_t mask)198 static inline void spi_umask_intr(struct dw_spi *dws, uint32_t mask)
199 {
200 uint32_t new_mask;
201
202 new_mask = dw_readl(dws, CVI_DW_SPI_IMR) | mask;
203 dw_writel(dws, CVI_DW_SPI_IMR, new_mask);
204 }
205
spi_reset_chip(struct dw_spi * dws)206 static inline void spi_reset_chip(struct dw_spi *dws)
207 {
208 spi_enable_chip(dws, 0);
209 spi_mask_intr(dws, 0xff);
210 dw_readl(dws, CVI_DW_SPI_ICR);
211 dw_writel(dws, CVI_DW_SPI_SER, 0);
212 spi_enable_chip(dws, 1);
213 }
214
spi_enable_dma(struct dw_spi * dws,uint8_t is_tx,uint8_t op)215 static inline void spi_enable_dma(struct dw_spi *dws, uint8_t is_tx, uint8_t op)
216 {
217 /* 1: TDMAE, 0: RDMAE */
218 uint32_t val = dw_readl(dws, CVI_DW_SPI_DMACR);
219
220 if (op)
221 val |= 1 << (!!is_tx);
222 else
223 val &= ~(1 << (!!is_tx));
224
225 dw_writel(dws, CVI_DW_SPI_DMACR, val);
226 }
227
spi_shutdown_chip(struct dw_spi * dws)228 static inline void spi_shutdown_chip(struct dw_spi *dws)
229 {
230 spi_enable_chip(dws, 0);
231 spi_set_clk(dws, 0);
232 }
233
234 void spi_hw_init(struct dw_spi *dws);
235 void dw_spi_set_controller_mode(struct dw_spi *dws, uint8_t enable_master);
236 void dw_spi_set_polarity_and_phase(struct dw_spi *dws, uint8_t format);
237 uint32_t dw_spi_set_clock(struct dw_spi *dws, uint32_t clock_in, uint32_t clock_out);
238 int dw_spi_set_data_frame_len(struct dw_spi *dws, uint32_t size);
239 void dw_spi_set_cs(struct dw_spi *dws, bool enable, uint32_t index);
240 void dw_reader(struct dw_spi *dws);
241 void dw_writer(struct dw_spi *dws);
242 void set_tran_mode(struct dw_spi *dws);
243 void dw_spi_show_regs(struct dw_spi *dws);
244 int poll_transfer(struct dw_spi *dws);
245 int dw_spi_check_status(struct dw_spi *dws, bool raw);
246 #endif
247