1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2010-11-13 weety first version
9 */
10
11
12 #include <rtthread.h>
13 #include <rthw.h>
14 #include <mmu.h>
15 #include "board.h"
16
17 /**
18 * @addtogroup dm365
19 */
20 /*@{*/
21 #if defined(__CC_ARM)
22 extern int Image$$ER_ZI$$ZI$$Base;
23 extern int Image$$ER_ZI$$ZI$$Length;
24 extern int Image$$ER_ZI$$ZI$$Limit;
25 #elif (defined (__GNUC__))
26 rt_uint8_t _irq_stack_start[1024];
27 rt_uint8_t _fiq_stack_start[1024];
28 rt_uint8_t _undefined_stack_start[512];
29 rt_uint8_t _abort_stack_start[512];
30 rt_uint8_t _svc_stack_start[1024] rt_section(".nobss");
31 extern unsigned char __bss_start;
32 extern unsigned char __bss_end;
33 #endif
34
35 extern void rt_hw_clock_init(void);
36 extern void rt_hw_uart_init(void);
37
38 static struct mem_desc dm365_mem_desc[] = {
39 { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED }, /* 128M cached SDRAM memory */
40 { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* 128M No cached SDRAM memory */
41 { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */
42 { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* CFG BUS peripherals */
43 { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* AEMIF */
44 };
45
46
47 /**
48 * This function will handle rtos timer
49 */
rt_timer_handler(int vector,void * param)50 void rt_timer_handler(int vector, void *param)
51 {
52 rt_tick_increase();
53 }
54
55 /**
56 * This function will init timer0 for system ticks
57 */
rt_hw_timer_init()58 void rt_hw_timer_init()
59 {
60 /* timer0, input clocks 24MHz */
61 volatile timer_regs_t *regs =
62 (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE;
63
64 psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3);
65 psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3);
66
67 /*disable timer*/
68 regs->tcr &= ~(0x3UL << 6);
69
70 //TIMMODE 32BIT UNCHAINED MODE
71 regs->tgcr |=(0x1UL << 2);
72
73 /*not in reset timer */
74 regs->tgcr |= (0x1UL << 0);
75
76 //regs->tgcr &= ~(0x1UL << 1);
77
78 /* set Period Registers */
79 regs->prd12 = 24000000/RT_TICK_PER_SECOND;
80 regs->tim12 = 0;
81
82 /* Set enable mode */
83 regs->tcr |= (0x2UL << 6); //period mode
84
85
86 /* install interrupt handler */
87 rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler,
88 RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12
89 rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2
90
91 }
92
93 #define LSR_DR 0x01 /* Data ready */
94 #define LSR_THRE 0x20 /* Xmit holding register empty */
95 #define BPS 115200 /* serial baudrate */
96
97 typedef struct uartport
98 {
99 volatile rt_uint32_t rbr;
100 volatile rt_uint32_t ier;
101 volatile rt_uint32_t fcr;
102 volatile rt_uint32_t lcr;
103 volatile rt_uint32_t mcr;
104 volatile rt_uint32_t lsr;
105 volatile rt_uint32_t msr;
106 volatile rt_uint32_t scr;
107 volatile rt_uint32_t dll;
108 volatile rt_uint32_t dlh;
109
110 volatile rt_uint32_t res[2];
111 volatile rt_uint32_t pwremu_mgmt;
112 volatile rt_uint32_t mdr;
113 }uartport;
114
115 #define thr rbr
116 #define iir fcr
117
118 #define UART0 ((struct uartport *)DAVINCI_UART0_BASE)
119
davinci_uart_putc(char c)120 static void davinci_uart_putc(char c)
121 {
122 while (!(UART0->lsr & LSR_THRE));
123 UART0->thr = c;
124 }
125
126 /**
127 * This function is used to display a string on console, normally, it's
128 * invoked by rt_kprintf
129 *
130 * @param str the displayed string
131 */
rt_hw_console_output(const char * str)132 void rt_hw_console_output(const char* str)
133 {
134 while (*str)
135 {
136 if (*str=='\n')
137 {
138 davinci_uart_putc('\r');
139 }
140
141 davinci_uart_putc(*str++);
142 }
143 }
144
rt_hw_console_init(void)145 static void rt_hw_console_init(void)
146 {
147 rt_uint32_t divisor;
148
149 divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS);
150 UART0->ier = 0;
151 UART0->lcr = 0x83; //8N1
152 UART0->dll = 0;
153 UART0->dlh = 0;
154 UART0->lcr = 0x03;
155 UART0->mcr = 0x03; //RTS,CTS
156 UART0->fcr = 0x07; //FIFO
157 UART0->lcr = 0x83;
158 UART0->dll = divisor & 0xff;
159 UART0->dlh = (divisor >> 8) & 0xff;
160 UART0->lcr = 0x03;
161 UART0->mdr = 0; //16x over-sampling
162 UART0->pwremu_mgmt = 0x6000;
163 }
164
165 /**
166 * This function will init dm365 board
167 */
rt_hw_board_init()168 void rt_hw_board_init()
169 {
170 /* initialize console */
171 rt_hw_console_init();
172
173 /* initialize mmu */
174 rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0]));
175
176 /* initialize hardware interrupt */
177 rt_hw_interrupt_init();
178
179 /* initialize the system clock */
180 rt_hw_clock_init();
181
182 /* initialize heap memory system */
183 #ifdef __CC_ARM
184 rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000);
185 #else
186 rt_system_heap_init((void*)&__bss_end, (void*)0x88000000);
187 #endif
188
189 /* initialize early device */
190 #ifdef RT_USING_COMPONENTS_INIT
191 rt_components_board_init();
192 #endif
193 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
194 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
195 #endif
196
197 /* initialize timer0 */
198 rt_hw_timer_init();
199
200 }
201
202 /*@}*/
203