1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-01-13 weety first version
9 */
10
11 #include <rtthread.h>
12 #include <drivers/dev_i2c.h>
13 #include <dm36x.h>
14
15 /* ----- global defines ----------------------------------------------- */
16 #define BIT(nr) (1UL << (nr))
17
18 #define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND)
19 #define DAVINCI_I2C_MAX_TRIES 2
20 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
21 DAVINCI_I2C_IMR_SCD | \
22 DAVINCI_I2C_IMR_ARDY | \
23 DAVINCI_I2C_IMR_NACK | \
24 DAVINCI_I2C_IMR_AL)
25
26 #define DAVINCI_I2C_OAR_REG 0x00
27 #define DAVINCI_I2C_IMR_REG 0x04
28 #define DAVINCI_I2C_STR_REG 0x08
29 #define DAVINCI_I2C_CLKL_REG 0x0c
30 #define DAVINCI_I2C_CLKH_REG 0x10
31 #define DAVINCI_I2C_CNT_REG 0x14
32 #define DAVINCI_I2C_DRR_REG 0x18
33 #define DAVINCI_I2C_SAR_REG 0x1c
34 #define DAVINCI_I2C_DXR_REG 0x20
35 #define DAVINCI_I2C_MDR_REG 0x24
36 #define DAVINCI_I2C_IVR_REG 0x28
37 #define DAVINCI_I2C_EMDR_REG 0x2c
38 #define DAVINCI_I2C_PSC_REG 0x30
39
40 #define DAVINCI_I2C_IVR_AAS 0x07
41 #define DAVINCI_I2C_IVR_SCD 0x06
42 #define DAVINCI_I2C_IVR_XRDY 0x05
43 #define DAVINCI_I2C_IVR_RDR 0x04
44 #define DAVINCI_I2C_IVR_ARDY 0x03
45 #define DAVINCI_I2C_IVR_NACK 0x02
46 #define DAVINCI_I2C_IVR_AL 0x01
47
48 #define DAVINCI_I2C_STR_BB BIT(12)
49 #define DAVINCI_I2C_STR_RSFULL BIT(11)
50 #define DAVINCI_I2C_STR_SCD BIT(5)
51 #define DAVINCI_I2C_STR_ARDY BIT(2)
52 #define DAVINCI_I2C_STR_NACK BIT(1)
53 #define DAVINCI_I2C_STR_AL BIT(0)
54
55 #define DAVINCI_I2C_MDR_NACK BIT(15)
56 #define DAVINCI_I2C_MDR_STT BIT(13)
57 #define DAVINCI_I2C_MDR_STP BIT(11)
58 #define DAVINCI_I2C_MDR_MST BIT(10)
59 #define DAVINCI_I2C_MDR_TRX BIT(9)
60 #define DAVINCI_I2C_MDR_XA BIT(8)
61 #define DAVINCI_I2C_MDR_RM BIT(7)
62 #define DAVINCI_I2C_MDR_IRS BIT(5)
63
64 #define DAVINCI_I2C_IMR_AAS BIT(6)
65 #define DAVINCI_I2C_IMR_SCD BIT(5)
66 #define DAVINCI_I2C_IMR_XRDY BIT(4)
67 #define DAVINCI_I2C_IMR_RRDY BIT(3)
68 #define DAVINCI_I2C_IMR_ARDY BIT(2)
69 #define DAVINCI_I2C_IMR_NACK BIT(1)
70 #define DAVINCI_I2C_IMR_AL BIT(0)
71
72 #ifdef RT_EDMA_DEBUG
73 #define i2c_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
74 #else
75 #define i2c_dbg(fmt, ...)
76 #endif
77
78
79 struct davinci_i2c_dev {
80 void *base;
81 struct rt_semaphore completion;
82 struct clk *clk;
83 int cmd_err;
84 rt_uint8_t *buf;
85 rt_uint32_t buf_len;
86 int irq;
87 int stop;
88 rt_uint8_t terminate;
89 rt_uint32_t bus_freq;
90 rt_uint32_t bus_delay;
91 struct rt_i2c_bus_device *bus;
92 };
93
davinci_i2c_write_reg(struct davinci_i2c_dev * i2c_dev,int reg,rt_uint16_t val)94 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
95 int reg, rt_uint16_t val)
96 {
97 davinci_writew(val, i2c_dev->base + reg);
98 }
99
davinci_i2c_read_reg(struct davinci_i2c_dev * i2c_dev,int reg)100 static inline rt_uint16_t davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
101 {
102 return davinci_readw(i2c_dev->base + reg);
103 }
104
udelay(rt_uint32_t us)105 static void udelay (rt_uint32_t us)
106 {
107 rt_int32_t i;
108 for (; us > 0; us--)
109 {
110 i = 50000;
111 while(i > 0)
112 {
113 i--;
114 }
115 }
116 }
117
118
119 #if 0
120 /* Generate a pulse on the i2c clock pin. */
121 static void generic_i2c_clock_pulse(unsigned int scl_pin)
122 {
123 rt_uint16_t i;
124
125 if (scl_pin) {
126 /* Send high and low on the SCL line */
127 for (i = 0; i < 9; i++) {
128 gpio_set_value(scl_pin, 0);
129 udelay(20);
130 gpio_set_value(scl_pin, 1);
131 udelay(20);
132 }
133 }
134 }
135 #endif
136
137 /* This routine does i2c bus recovery as specified in the
138 * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
139 */
i2c_recover_bus(struct davinci_i2c_dev * dev)140 static void i2c_recover_bus(struct davinci_i2c_dev *dev)
141 {
142 rt_uint32_t flag = 0;
143
144 i2c_dbg("initiating i2c bus recovery\n");
145 /* Send NACK to the slave */
146 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
147 flag |= DAVINCI_I2C_MDR_NACK;
148 /* write the data into mode register */
149 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
150 #if 0
151 if (pdata)
152 generic_i2c_clock_pulse(pdata->scl_pin);
153 #endif
154 /* Send STOP */
155 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
156 flag |= DAVINCI_I2C_MDR_STP;
157 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
158 }
159
davinci_i2c_reset_ctrl(struct davinci_i2c_dev * i2c_dev,int val)160 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
161 int val)
162 {
163 rt_uint16_t w;
164
165 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
166 if (!val) /* put I2C into reset */
167 w &= ~DAVINCI_I2C_MDR_IRS;
168 else /* take I2C out of reset */
169 w |= DAVINCI_I2C_MDR_IRS;
170
171 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
172 }
173
i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev * dev)174 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
175 {
176 rt_uint16_t psc;
177 rt_uint32_t clk;
178 rt_uint32_t d;
179 rt_uint32_t clkh;
180 rt_uint32_t clkl;
181 rt_uint32_t input_clock = clk_get_rate(dev->clk);
182
183 /* NOTE: I2C Clock divider programming info
184 * As per I2C specs the following formulas provide prescaler
185 * and low/high divider values
186 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
187 * module clk
188 *
189 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
190 *
191 * Thus,
192 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
193 *
194 * where if PSC == 0, d = 7,
195 * if PSC == 1, d = 6
196 * if PSC > 1 , d = 5
197 */
198
199 /* get minimum of 7 MHz clock, but max of 12 MHz */
200 psc = (input_clock / 7000000) - 1;
201 if ((input_clock / (psc + 1)) > 12000000)
202 psc++; /* better to run under spec than over */
203 d = (psc >= 2) ? 5 : 7 - psc;
204
205 clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1);
206 clkh = clk >> 1;
207 clkl = clk - clkh;
208
209 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
210 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
211 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
212
213 i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk);
214 }
215
216 /*
217 * This function configures I2C and brings I2C out of reset.
218 * This function is called during I2C init function. This function
219 * also gets called if I2C encounters any errors.
220 */
i2c_davinci_init(struct davinci_i2c_dev * dev)221 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
222 {
223 /* put I2C into reset */
224 davinci_i2c_reset_ctrl(dev, 0);
225
226 /* compute clock dividers */
227 i2c_davinci_calc_clk_dividers(dev);
228
229 /* Respond at reserved "SMBus Host" slave address" (and zero);
230 * we seem to have no option to not respond...
231 */
232 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
233
234 i2c_dbg("PSC = %d\n",
235 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
236 i2c_dbg("CLKL = %d\n",
237 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
238 i2c_dbg("CLKH = %d\n",
239 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
240 i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n",
241 dev->bus_freq, dev->bus_delay);
242
243 /* Take the I2C module out of reset: */
244 davinci_i2c_reset_ctrl(dev, 1);
245
246 /* Enable interrupts */
247 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
248
249 return 0;
250 }
251
252 /*
253 * Waiting for bus not busy
254 */
i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev * dev,char allow_sleep)255 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
256 char allow_sleep)
257 {
258 unsigned long timeout;
259 static rt_uint16_t to_cnt;
260 RT_ASSERT(dev != RT_NULL);
261 RT_ASSERT(dev->bus != RT_NULL);
262
263 timeout = rt_tick_get() + dev->bus->timeout;
264 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
265 & DAVINCI_I2C_STR_BB) {
266 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
267 if (rt_tick_get() >= timeout) {
268 rt_kprintf("timeout waiting for bus ready\n");
269 to_cnt++;
270 return -RT_ETIMEOUT;
271 } else {
272 to_cnt = 0;
273 i2c_recover_bus(dev);
274 i2c_davinci_init(dev);
275 }
276 }
277 if (allow_sleep)
278 rt_thread_delay(2);
279 }
280
281 return 0;
282 }
283
284 /*
285 * Low level master read/write transaction. This function is called
286 * from i2c_davinci_xfer.
287 */
288 static int
i2c_davinci_xfer_msg(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msg,int stop)289 i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int stop)
290 {
291 struct davinci_i2c_dev *dev = bus->priv;
292 rt_uint32_t flag;
293 rt_uint16_t w;
294 int r;
295
296 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
297 if (dev->bus_delay)
298 udelay(dev->bus_delay);
299
300 /* set the slave address */
301 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
302
303 dev->buf = msg->buf;
304 dev->buf_len = msg->len;
305 dev->stop = stop;
306
307 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
308
309 //INIT_COMPLETION(dev->cmd_complete);
310 dev->cmd_err = 0;
311
312 /* Take I2C out of reset and configure it as master */
313 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
314
315 /* if the slave address is ten bit address, enable XA bit */
316 if (msg->flags & RT_I2C_ADDR_10BIT)
317 flag |= DAVINCI_I2C_MDR_XA;
318 if (!(msg->flags & RT_I2C_RD))
319 flag |= DAVINCI_I2C_MDR_TRX;
320 if (msg->len == 0)
321 flag |= DAVINCI_I2C_MDR_RM;
322
323 /* Enable receive or transmit interrupts */
324 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
325 if (msg->flags & RT_I2C_RD)
326 w |= DAVINCI_I2C_IMR_RRDY;
327 else
328 w |= DAVINCI_I2C_IMR_XRDY;
329 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
330
331 dev->terminate = 0;
332
333 /*
334 * Write mode register first as needed for correct behaviour
335 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
336 * occurring before we have loaded DXR
337 */
338 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
339
340 /*
341 * First byte should be set here, not after interrupt,
342 * because transmit-data-ready interrupt can come before
343 * NACK-interrupt during sending of previous message and
344 * ICDXR may have wrong data
345 * It also saves us one interrupt, slightly faster
346 */
347 if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len)
348 {
349 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
350 dev->buf_len--;
351 }
352
353 /* Set STT to begin transmit now DXR is loaded */
354 flag |= DAVINCI_I2C_MDR_STT;
355 if (stop && msg->len != 0)
356 flag |= DAVINCI_I2C_MDR_STP;
357 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
358
359 r = rt_sem_take(&dev->completion, dev->bus->timeout);
360 if (r == -RT_ETIMEOUT)
361 {
362 rt_kprintf("controller timed out\n");
363 i2c_recover_bus(dev);
364 i2c_davinci_init(dev);
365 dev->buf_len = 0;
366 return -RT_ETIMEOUT;
367 }
368 if (dev->buf_len)
369 {
370 /* This should be 0 if all bytes were transferred
371 * or dev->cmd_err denotes an error.
372 * A signal may have aborted the transfer.
373 */
374 if (r == RT_EOK)
375 {
376 rt_kprintf("abnormal termination buf_len=%i\n",
377 dev->buf_len);
378 r = -RT_EIO;
379 }
380 dev->terminate = 1;
381 dev->buf_len = 0;
382 }
383 if (r < 0)
384 return r;
385
386 /* no error */
387 if (!dev->cmd_err)
388 return msg->len;
389
390 /* We have an error */
391 if (dev->cmd_err & DAVINCI_I2C_STR_AL)
392 {
393 i2c_davinci_init(dev);
394 return -RT_EIO;
395 }
396
397 if (dev->cmd_err & DAVINCI_I2C_STR_NACK)
398 {
399 if (msg->flags & RT_I2C_IGNORE_NACK)
400 return msg->len;
401 if (stop)
402 {
403 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
404 w |= DAVINCI_I2C_MDR_STP;
405 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
406 }
407 return -RT_EIO;
408 }
409 return -RT_EIO;
410 }
411
412 /*
413 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
414 */
415 static int
i2c_davinci_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg msgs[],int num)416 i2c_davinci_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], int num)
417 {
418 struct davinci_i2c_dev *dev = bus->priv;
419 int i;
420 int ret;
421
422 i2c_dbg("%s: msgs: %d\n", __func__, num);
423
424 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
425 if (ret < 0)
426 {
427 i2c_dbg("timeout waiting for bus ready\n");
428 return ret;
429 }
430
431 for (i = 0; i < num; i++)
432 {
433 ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1)));
434 i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num,
435 ret);
436 if (ret < 0)
437 return ret;
438 }
439
440
441 return num;
442 }
443
444
terminate_read(struct davinci_i2c_dev * dev)445 static void terminate_read(struct davinci_i2c_dev *dev)
446 {
447 rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
448 w |= DAVINCI_I2C_MDR_NACK;
449 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
450
451 /* Throw away data */
452 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
453 if (!dev->terminate)
454 rt_kprintf("RDR IRQ while no data requested\n");
455 }
terminate_write(struct davinci_i2c_dev * dev)456 static void terminate_write(struct davinci_i2c_dev *dev)
457 {
458 rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
459 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
460 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
461
462 if (!dev->terminate)
463 i2c_dbg("TDR IRQ while no data to send\n");
464 }
465
466 /*
467 * Interrupt service routine. This gets called whenever an I2C interrupt
468 * occurs.
469 */
i2c_davinci_isr(int irq,void * param)470 static void i2c_davinci_isr(int irq, void *param)
471 {
472 struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param;
473 rt_uint32_t stat;
474 int count = 0;
475 rt_uint16_t w;
476
477 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
478 i2c_dbg("%s: stat=0x%x\n", __func__, stat);
479 if (count++ == 100) {
480 rt_kprintf("Too much work in one IRQ\n");
481 break;
482 }
483
484 switch (stat) {
485 case DAVINCI_I2C_IVR_AL:
486 /* Arbitration lost, must retry */
487 dev->cmd_err |= DAVINCI_I2C_STR_AL;
488 dev->buf_len = 0;
489 rt_sem_release(&dev->completion);
490 break;
491
492 case DAVINCI_I2C_IVR_NACK:
493 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
494 dev->buf_len = 0;
495 rt_sem_release(&dev->completion);
496 break;
497
498 case DAVINCI_I2C_IVR_ARDY:
499 davinci_i2c_write_reg(dev,
500 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
501 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
502 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
503 w = davinci_i2c_read_reg(dev,
504 DAVINCI_I2C_MDR_REG);
505 w |= DAVINCI_I2C_MDR_STP;
506 davinci_i2c_write_reg(dev,
507 DAVINCI_I2C_MDR_REG, w);
508 }
509 rt_sem_release(&dev->completion);
510 break;
511
512 case DAVINCI_I2C_IVR_RDR:
513 if (dev->buf_len) {
514 *dev->buf++ =
515 davinci_i2c_read_reg(dev,
516 DAVINCI_I2C_DRR_REG);
517 dev->buf_len--;
518 if (dev->buf_len)
519 continue;
520
521 davinci_i2c_write_reg(dev,
522 DAVINCI_I2C_STR_REG,
523 DAVINCI_I2C_IMR_RRDY);
524 } else {
525 /* signal can terminate transfer */
526 terminate_read(dev);
527 }
528 break;
529
530 case DAVINCI_I2C_IVR_XRDY:
531 if (dev->buf_len) {
532 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
533 *dev->buf++);
534 dev->buf_len--;
535 if (dev->buf_len)
536 continue;
537
538 w = davinci_i2c_read_reg(dev,
539 DAVINCI_I2C_IMR_REG);
540 w &= ~DAVINCI_I2C_IMR_XRDY;
541 davinci_i2c_write_reg(dev,
542 DAVINCI_I2C_IMR_REG,
543 w);
544 } else {
545 /* signal can terminate transfer */
546 terminate_write(dev);
547 }
548 break;
549
550 case DAVINCI_I2C_IVR_SCD:
551 davinci_i2c_write_reg(dev,
552 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
553 rt_sem_release(&dev->completion);
554 break;
555
556 case DAVINCI_I2C_IVR_AAS:
557 i2c_dbg("Address as slave interrupt\n");
558 break;
559
560 default:
561 i2c_dbg("Unrecognized irq stat %d\n", stat);
562 break;
563 }
564 }
565
566 }
567
568
569
570 static struct rt_i2c_bus_device_ops bus_ops = {
571 .master_xfer = i2c_davinci_xfer,
572 };
573
davinci_i2c_init(char * bus_name)574 int davinci_i2c_init(char *bus_name)
575 {
576 struct rt_i2c_bus_device *bus;
577 struct davinci_i2c_dev *dev;
578 int r;
579
580 bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
581 if (bus == RT_NULL)
582 {
583 rt_kprintf("rt_malloc failed\n");
584 return -RT_ENOMEM;
585 }
586
587 rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
588
589 bus->ops = &bus_ops;
590 bus->timeout = DAVINCI_I2C_TIMEOUT;
591
592 dev = rt_malloc(sizeof(struct davinci_i2c_dev));
593 if (!dev)
594 {
595 r = -RT_ENOMEM;
596 goto err;
597 }
598
599 rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev));
600
601 rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO);
602
603 dev->irq = IRQ_I2C;
604
605 dev->clk = clk_get("I2CCLK");
606 if (dev->clk == RT_NULL) {
607 r = -RT_ERROR;
608 goto err1;
609 }
610
611 psc_change_state(DAVINCI_DM365_LPSC_I2C, 3);
612
613 dev->base = DAVINCI_I2C_BASE;
614 dev->bus_freq = 100;
615 dev->bus_delay = 0;
616 dev->bus = bus;
617
618 bus->priv = dev;
619
620 i2c_davinci_init(dev);
621
622 rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C");
623 rt_hw_interrupt_umask(dev->irq);
624
625 return rt_i2c_bus_device_register(bus, bus_name);
626
627 err1:
628 rt_free(dev);
629
630 err:
631 rt_free(bus);
632
633 return r;
634 }
635
rt_hw_iic_init(void)636 int rt_hw_iic_init(void)
637 {
638 davinci_i2c_init("I2C1");
639 }
640
641 INIT_DEVICE_EXPORT(rt_hw_iic_init);
642
643