1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-01-13 weety first version 9 */ 10 11 #ifndef __DAVINCI_MMC_H__ 12 #define __DAVINCI_MMC_H__ 13 14 /* DAVINCI_MMCCTL definitions */ 15 #define MMCCTL_DATRST (1 << 0) 16 #define MMCCTL_CMDRST (1 << 1) 17 #define MMCCTL_WIDTH_8_BIT (1 << 8) 18 #define MMCCTL_WIDTH_4_BIT (1 << 2) 19 #define MMCCTL_DATEG_DISABLED (0 << 6) 20 #define MMCCTL_DATEG_RISING (1 << 6) 21 #define MMCCTL_DATEG_FALLING (2 << 6) 22 #define MMCCTL_DATEG_BOTH (3 << 6) 23 #define MMCCTL_PERMDR_LE (0 << 9) 24 #define MMCCTL_PERMDR_BE (1 << 9) 25 #define MMCCTL_PERMDX_LE (0 << 10) 26 #define MMCCTL_PERMDX_BE (1 << 10) 27 28 /* DAVINCI_MMCCLK definitions */ 29 #define MMCCLK_CLKEN (1 << 8) 30 #define MMCCLK_CLKRT_MASK (0xFF << 0) 31 32 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 33 #define MMCST0_DATDNE (1 << 0) /* data done */ 34 #define MMCST0_BSYDNE (1 << 1) /* busy done */ 35 #define MMCST0_RSPDNE (1 << 2) /* command done */ 36 #define MMCST0_TOUTRD (1 << 3) /* data read timeout */ 37 #define MMCST0_TOUTRS (1 << 4) /* command response timeout */ 38 #define MMCST0_CRCWR (1 << 5) /* data write CRC error */ 39 #define MMCST0_CRCRD (1 << 6) /* data read CRC error */ 40 #define MMCST0_CRCRS (1 << 7) /* command response CRC error */ 41 #define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */ 42 #define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/ 43 #define MMCST0_DATED (1 << 11) /* DAT3 edge detect */ 44 #define MMCST0_TRNDNE (1 << 12) /* transfer done */ 45 46 /* DAVINCI_MMCST1 definitions */ 47 #define MMCST1_BUSY (1 << 0) 48 49 /* DAVINCI_MMCCMD definitions */ 50 #define MMCCMD_CMD_MASK (0x3F << 0) 51 #define MMCCMD_PPLEN (1 << 7) 52 #define MMCCMD_BSYEXP (1 << 8) 53 #define MMCCMD_RSPFMT_MASK (3 << 9) 54 #define MMCCMD_RSPFMT_NONE (0 << 9) 55 #define MMCCMD_RSPFMT_R1456 (1 << 9) 56 #define MMCCMD_RSPFMT_R2 (2 << 9) 57 #define MMCCMD_RSPFMT_R3 (3 << 9) 58 #define MMCCMD_DTRW (1 << 11) 59 #define MMCCMD_STRMTP (1 << 12) 60 #define MMCCMD_WDATX (1 << 13) 61 #define MMCCMD_INITCK (1 << 14) 62 #define MMCCMD_DCLR (1 << 15) 63 #define MMCCMD_DMATRIG (1 << 16) 64 65 /* DAVINCI_MMCFIFOCTL definitions */ 66 #define MMCFIFOCTL_FIFORST (1 << 0) 67 #define MMCFIFOCTL_FIFODIR_WR (1 << 1) 68 #define MMCFIFOCTL_FIFODIR_RD (0 << 1) 69 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 70 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 71 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 72 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 73 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 74 75 /* DAVINCI_SDIOST0 definitions */ 76 #define SDIOST0_DAT1_HI (1 << 0) 77 #define SDIOST0_INTPRD (1 << 1) 78 #define SDIOST0_RDWTST (1 << 2) 79 80 /* DAVINCI_SDIOIEN definitions */ 81 #define SDIOIEN_IOINTEN (1 << 0) 82 #define SDIOIEN_RWSEN (1 << 1) 83 84 /* DAVINCI_SDIOIST definitions */ 85 #define SDIOIST_IOINT (1 << 0) 86 #define SDIOIST_RWS (1 << 1) 87 88 /* MMCSD Init clock in Hz in opendrain mode */ 89 #define MMCSD_INIT_CLOCK 200000 90 91 #define MAX_CCNT ((1 << 16) - 1) 92 93 #define MAX_NR_SG 16 94 95 #define MMC_DATA_WRITE (1 << 8) 96 #define MMC_DATA_READ (1 << 9) 97 #define MMC_DATA_STREAM (1 << 10) 98 99 typedef struct { 100 volatile rt_uint32_t MMCCTL; 101 volatile rt_uint32_t MMCCLK; 102 volatile rt_uint32_t MMCST0; 103 volatile rt_uint32_t MMCST1; 104 volatile rt_uint32_t MMCIM; 105 volatile rt_uint32_t MMCTOR; 106 volatile rt_uint32_t MMCTOD; 107 volatile rt_uint32_t MMCBLEN; 108 volatile rt_uint32_t MMCNBLK; 109 volatile rt_uint32_t MMCNBLC; 110 volatile rt_uint32_t MMCDRR; 111 volatile rt_uint32_t MMCDXR; 112 volatile rt_uint32_t MMCCMD; 113 volatile rt_uint32_t MMCARGHL; 114 volatile rt_uint32_t MMCRSP01; 115 volatile rt_uint32_t MMCRSP23; 116 volatile rt_uint32_t MMCRSP45; 117 volatile rt_uint32_t MMCRSP67; 118 volatile rt_uint32_t MMCDRSP; 119 volatile rt_uint32_t reserved0; 120 volatile rt_uint32_t MMCCIDX; 121 volatile rt_uint32_t reserved1[4]; 122 volatile rt_uint32_t SDIOCTL; 123 volatile rt_uint32_t SDIOST0; 124 volatile rt_uint32_t SDIOIEN; 125 volatile rt_uint32_t SDIOIST; 126 volatile rt_uint32_t MMCFIFOCTL; 127 }mmcsd_regs_t; 128 129 extern int rt_hw_mmcsd_init(void); 130 131 #endif 132