1 /**************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File 4 * for EFM EFM32G890F32 5 * @author Energy Micro AS 6 * @version 3.0.0 7 ****************************************************************************** 8 * @section License 9 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 10 ****************************************************************************** 11 * 12 * Permission is granted to anyone to use this software for any purpose, 13 * including commercial applications, and to alter it and redistribute it 14 * freely, subject to the following restrictions: 15 * 16 * 1. The origin of this software must not be misrepresented; you must not 17 * claim that you wrote the original software. 18 * 2. Altered source versions must be plainly marked as such, and must not be 19 * misrepresented as being the original software. 20 * 3. This notice may not be removed or altered from any source distribution. 21 * 22 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 23 * obligation to support this Software. Energy Micro AS is providing the 24 * Software "AS IS", with no express or implied warranties of any kind, 25 * including, but not limited to, any implied warranties of merchantability 26 * or fitness for any particular purpose or warranties against infringement 27 * of any proprietary rights of a third party. 28 * 29 * Energy Micro AS will not be liable for any consequential, incidental, or 30 * special damages, or any other relief, or for any claim by any third party, 31 * arising from your use of this Software. 32 * 33 *****************************************************************************/ 34 35 #ifndef __EFM32G890F32_H 36 #define __EFM32G890F32_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /**************************************************************************//** 43 * @addtogroup Parts 44 * @{ 45 *****************************************************************************/ 46 47 /**************************************************************************//** 48 * @defgroup EFM32G890F32 EFM32G890F32 49 * @{ 50 *****************************************************************************/ 51 52 /** Interrupt Number Definition */ 53 typedef enum IRQn 54 { 55 /****** Cortex-M3 Processor Exceptions Numbers *******************************************/ 56 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 57 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 58 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 59 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 60 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 61 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 62 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 63 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 64 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 65 66 /****** EFM32G Peripheral Interrupt Numbers **********************************************/ 67 DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */ 68 GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */ 69 TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */ 70 USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */ 71 USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */ 72 ACMP0_IRQn = 5, /*!< 16+5 EFM32 ACMP0 Interrupt */ 73 ADC0_IRQn = 6, /*!< 16+6 EFM32 ADC0 Interrupt */ 74 DAC0_IRQn = 7, /*!< 16+7 EFM32 DAC0 Interrupt */ 75 I2C0_IRQn = 8, /*!< 16+8 EFM32 I2C0 Interrupt */ 76 GPIO_ODD_IRQn = 9, /*!< 16+9 EFM32 GPIO_ODD Interrupt */ 77 TIMER1_IRQn = 10, /*!< 16+10 EFM32 TIMER1 Interrupt */ 78 TIMER2_IRQn = 11, /*!< 16+11 EFM32 TIMER2 Interrupt */ 79 USART1_RX_IRQn = 12, /*!< 16+12 EFM32 USART1_RX Interrupt */ 80 USART1_TX_IRQn = 13, /*!< 16+13 EFM32 USART1_TX Interrupt */ 81 USART2_RX_IRQn = 14, /*!< 16+14 EFM32 USART2_RX Interrupt */ 82 USART2_TX_IRQn = 15, /*!< 16+15 EFM32 USART2_TX Interrupt */ 83 UART0_RX_IRQn = 16, /*!< 16+16 EFM32 UART0_RX Interrupt */ 84 UART0_TX_IRQn = 17, /*!< 16+17 EFM32 UART0_TX Interrupt */ 85 LEUART0_IRQn = 18, /*!< 16+18 EFM32 LEUART0 Interrupt */ 86 LEUART1_IRQn = 19, /*!< 16+19 EFM32 LEUART1 Interrupt */ 87 LETIMER0_IRQn = 20, /*!< 16+20 EFM32 LETIMER0 Interrupt */ 88 PCNT0_IRQn = 21, /*!< 16+21 EFM32 PCNT0 Interrupt */ 89 PCNT1_IRQn = 22, /*!< 16+22 EFM32 PCNT1 Interrupt */ 90 PCNT2_IRQn = 23, /*!< 16+23 EFM32 PCNT2 Interrupt */ 91 RTC_IRQn = 24, /*!< 16+24 EFM32 RTC Interrupt */ 92 CMU_IRQn = 25, /*!< 16+25 EFM32 CMU Interrupt */ 93 VCMP_IRQn = 26, /*!< 16+26 EFM32 VCMP Interrupt */ 94 LCD_IRQn = 27, /*!< 16+27 EFM32 LCD Interrupt */ 95 MSC_IRQn = 28, /*!< 16+28 EFM32 MSC Interrupt */ 96 AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */ 97 } IRQn_Type; 98 99 /**************************************************************************//** 100 * @defgroup EFM32G890F32_Core EFM32G890F32 Core 101 * @{ 102 * @brief Processor and Core Peripheral Section 103 *****************************************************************************/ 104 #define __MPU_PRESENT 1 /**< Presence of MPU */ 105 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ 106 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ 107 108 /** @} End of group EFM32G890F32_Core */ 109 110 /**************************************************************************//** 111 * @defgroup EFM32G890F32_Part EFM32G890F32 Part 112 * @{ 113 ******************************************************************************/ 114 115 /** Part family */ 116 #define _EFM32_GECKO_FAMILY 1 /**< Gecko EFM32G MCU Family */ 117 118 /* If part number is not defined as compiler option, define it */ 119 #if !defined(EFM32G890F32) 120 #define EFM32G890F32 1 /**< Gecko Part */ 121 #endif 122 123 /** Configure part number */ 124 #define PART_NUMBER "EFM32G890F32" /**< Part Number */ 125 126 /** Memory Base addresses and limits */ 127 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */ 128 #define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */ 129 #define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */ 130 #define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */ 131 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */ 132 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */ 133 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */ 134 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */ 135 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ 136 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */ 137 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */ 138 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ 139 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ 140 #define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */ 141 #define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */ 142 #define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ 143 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ 144 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */ 145 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */ 146 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */ 147 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */ 148 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ 149 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */ 150 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ 151 152 /** Bit banding area */ 153 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ 154 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ 155 156 /** Flash and SRAM limits for EFM32G890F32 */ 157 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 158 #define FLASH_SIZE (0x00008000UL) /**< Available Flash Memory */ 159 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 160 #define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */ 161 #define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */ 162 #define PRS_CHAN_COUNT 8 /**< Number of PRS channels */ 163 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ 164 165 /* Part number capabilities */ 166 167 #define TIMER_PRESENT /**< TIMER is available in this part */ 168 #define TIMER_COUNT 3 /**< 3 TIMERs available */ 169 #define USART_PRESENT /**< USART is available in this part */ 170 #define USART_COUNT 3 /**< 3 USARTs available */ 171 #define UART_PRESENT /**< UART is available in this part */ 172 #define UART_COUNT 1 /**< 1 UARTs available */ 173 #define LEUART_PRESENT /**< LEUART is available in this part */ 174 #define LEUART_COUNT 2 /**< 2 LEUARTs available */ 175 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 176 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ 177 #define PCNT_PRESENT /**< PCNT is available in this part */ 178 #define PCNT_COUNT 3 /**< 3 PCNTs available */ 179 #define I2C_PRESENT /**< I2C is available in this part */ 180 #define I2C_COUNT 1 /**< 1 I2Cs available */ 181 #define ADC_PRESENT /**< ADC is available in this part */ 182 #define ADC_COUNT 1 /**< 1 ADCs available */ 183 #define DAC_PRESENT /**< DAC is available in this part */ 184 #define DAC_COUNT 1 /**< 1 DACs available */ 185 #define ACMP_PRESENT /**< ACMP is available in this part */ 186 #define ACMP_COUNT 2 /**< 2 ACMPs available */ 187 #define LE_PRESENT 188 #define LE_COUNT 1 189 #define MSC_PRESENT 190 #define MSC_COUNT 1 191 #define EMU_PRESENT 192 #define EMU_COUNT 1 193 #define RMU_PRESENT 194 #define RMU_COUNT 1 195 #define CMU_PRESENT 196 #define CMU_COUNT 1 197 #define AES_PRESENT 198 #define AES_COUNT 1 199 #define EBI_PRESENT 200 #define EBI_COUNT 1 201 #define GPIO_PRESENT 202 #define GPIO_COUNT 1 203 #define PRS_PRESENT 204 #define PRS_COUNT 1 205 #define DMA_PRESENT 206 #define DMA_COUNT 1 207 #define VCMP_PRESENT 208 #define VCMP_COUNT 1 209 #define LCD_PRESENT 210 #define LCD_COUNT 1 211 #define RTC_PRESENT 212 #define RTC_COUNT 1 213 #define HFXTAL_PRESENT 214 #define HFXTAL_COUNT 1 215 #define LFXTAL_PRESENT 216 #define LFXTAL_COUNT 1 217 #define WDOG_PRESENT 218 #define WDOG_COUNT 1 219 #define DBG_PRESENT 220 #define DBG_COUNT 1 221 222 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ 223 #include "system_efm32g.h" /* System Header */ 224 225 /** @} End of group EFM32G890F32_Part */ 226 227 /**************************************************************************//** 228 * @defgroup EFM32G890F32_Peripheral_TypeDefs EFM32G890F32 Peripheral TypeDefs 229 * @{ 230 * @brief Device Specific Peripheral Register Structures 231 *****************************************************************************/ 232 233 #include "efm32g_msc.h" 234 #include "efm32g_emu.h" 235 #include "efm32g_rmu.h" 236 #include "efm32g_cmu.h" 237 #include "efm32g_aes.h" 238 #include "efm32g_ebi.h" 239 #include "efm32g_gpio_p.h" 240 #include "efm32g_gpio.h" 241 #include "efm32g_prs_ch.h" 242 #include "efm32g_prs.h" 243 #include "efm32g_dma_ch.h" 244 #include "efm32g_dma.h" 245 #include "efm32g_timer_cc.h" 246 #include "efm32g_timer.h" 247 #include "efm32g_usart.h" 248 #include "efm32g_leuart.h" 249 #include "efm32g_letimer.h" 250 #include "efm32g_pcnt.h" 251 #include "efm32g_i2c.h" 252 #include "efm32g_adc.h" 253 #include "efm32g_dac.h" 254 #include "efm32g_acmp.h" 255 #include "efm32g_vcmp.h" 256 #include "efm32g_lcd.h" 257 #include "efm32g_rtc.h" 258 #include "efm32g_wdog.h" 259 #include "efm32g_dma_descriptor.h" 260 #include "efm32g_devinfo.h" 261 #include "efm32g_romtable.h" 262 #include "efm32g_calibrate.h" 263 264 /** @} End of group EFM32G890F32_Peripheral_TypeDefs */ 265 266 /**************************************************************************//** 267 * @defgroup EFM32G890F32_Peripheral_Base EFM32G890F32 Peripheral Memory Map 268 * @{ 269 *****************************************************************************/ 270 271 #define MSC_BASE (0x400C0000UL) /**< MSC base address */ 272 #define EMU_BASE (0x400C6000UL) /**< EMU base address */ 273 #define RMU_BASE (0x400CA000UL) /**< RMU base address */ 274 #define CMU_BASE (0x400C8000UL) /**< CMU base address */ 275 #define AES_BASE (0x400E0000UL) /**< AES base address */ 276 #define EBI_BASE (0x40008000UL) /**< EBI base address */ 277 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ 278 #define PRS_BASE (0x400CC000UL) /**< PRS base address */ 279 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ 280 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ 281 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ 282 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */ 283 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */ 284 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ 285 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */ 286 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ 287 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ 288 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */ 289 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */ 290 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ 291 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */ 292 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */ 293 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ 294 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 295 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */ 296 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ 297 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */ 298 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ 299 #define LCD_BASE (0x4008A000UL) /**< LCD base address */ 300 #define RTC_BASE (0x40080000UL) /**< RTC base address */ 301 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ 302 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ 303 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 304 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 305 306 /** @} End of group EFM32G890F32_Peripheral_Base */ 307 308 /**************************************************************************//** 309 * @defgroup EFM32G890F32_Peripheral_Declaration EFM32G890F32 Peripheral Declarations 310 * @{ 311 *****************************************************************************/ 312 313 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 314 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 315 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 316 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 317 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ 318 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ 319 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 320 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ 322 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 323 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 324 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 325 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 326 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 327 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 328 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ 329 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 330 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ 331 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 332 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 333 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ 334 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ 335 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 336 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 337 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */ 338 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 339 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 340 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ 341 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ 342 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 343 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ 344 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ 345 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 346 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 347 348 /** @} End of group EFM32G890F32_Peripheral_Declaration */ 349 350 /**************************************************************************//** 351 * @defgroup EFM32G890F32_BitFields EFM32G890F32 Bit Fields 352 * @{ 353 *****************************************************************************/ 354 355 #include "efm32g_prs_signals.h" 356 #include "efm32g_dmareq.h" 357 #include "efm32g_dmactrl.h" 358 #include "efm32g_uart.h" 359 360 /**************************************************************************//** 361 * @defgroup EFM32G890F32_UNLOCK Unlock Codes 362 * @{ 363 *****************************************************************************/ 364 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 365 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 366 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 367 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 368 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 369 370 /** @} End of group EFM32G890F32_UNLOCK */ 371 372 /** @} End of group EFM32G890F32_BitFields */ 373 374 /**************************************************************************//** 375 * @defgroup EFM32G890F32_Alternate_Function EFM32G890F32 Alternate Function 376 * @{ 377 *****************************************************************************/ 378 379 #include "efm32g_af_channels.h" 380 #include "efm32g_af_ports.h" 381 #include "efm32g_af_pins.h" 382 383 /** @} End of group EFM32G890F32_Alternate_Function */ 384 385 /**************************************************************************//** 386 * @brief Set the value of a bit field within a register. 387 * 388 * @param REG 389 * The register to update 390 * @param MASK 391 * The mask for the bit field to update 392 * @param VALUE 393 * The value to write to the bit field 394 * @param OFFSET 395 * The number of bits that the field is offset within the register. 396 * 0 (zero) means LSB. 397 *****************************************************************************/ 398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 400 401 /** @} End of group EFM32G890F32 */ 402 403 /** @} End of group Parts */ 404 405 #ifdef __cplusplus 406 } 407 #endif 408 409 #endif /* __EFM32G890F32_H */ 410