1 /**************************************************************************//** 2 * @file 3 * @brief efm32g_acmp Register and Bit Field definitions 4 * @author Energy Micro AS 5 * @version 3.0.0 6 ****************************************************************************** 7 * @section License 8 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 9 ****************************************************************************** 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. 17 * 2. Altered source versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software. 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 22 * obligation to support this Software. Energy Micro AS is providing the 23 * Software "AS IS", with no express or implied warranties of any kind, 24 * including, but not limited to, any implied warranties of merchantability 25 * or fitness for any particular purpose or warranties against infringement 26 * of any proprietary rights of a third party. 27 * 28 * Energy Micro AS will not be liable for any consequential, incidental, or 29 * special damages, or any other relief, or for any claim by any third party, 30 * arising from your use of this Software. 31 * 32 *****************************************************************************/ 33 /**************************************************************************//** 34 * @defgroup EFM32G_ACMP 35 * @{ 36 * @brief EFM32G_ACMP Register Declaration 37 *****************************************************************************/ 38 typedef struct 39 { 40 __IO uint32_t CTRL; /**< Control Register */ 41 __IO uint32_t INPUTSEL; /**< Input Selection Register */ 42 __I uint32_t STATUS; /**< Status Register */ 43 __IO uint32_t IEN; /**< Interrupt Enable Register */ 44 __I uint32_t IF; /**< Interrupt Flag Register */ 45 __IO uint32_t IFS; /**< Interrupt Flag Set Register */ 46 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ 47 __IO uint32_t ROUTE; /**< I/O Routing Register */ 48 } ACMP_TypeDef; /** @} */ 49 50 /**************************************************************************//** 51 * @defgroup EFM32G_ACMP_BitFields 52 * @{ 53 *****************************************************************************/ 54 55 /* Bit fields for ACMP CTRL */ 56 #define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */ 57 #define _ACMP_CTRL_MASK 0xCF03077FUL /**< Mask for ACMP_CTRL */ 58 #define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ 59 #define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ 60 #define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ 61 #define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 62 #define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ 63 #define ACMP_CTRL_MUXEN (0x1UL << 1) /**< Input Mux Enable */ 64 #define _ACMP_CTRL_MUXEN_SHIFT 1 /**< Shift value for ACMP_MUXEN */ 65 #define _ACMP_CTRL_MUXEN_MASK 0x2UL /**< Bit mask for ACMP_MUXEN */ 66 #define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 67 #define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ 68 #define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ 69 #define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ 70 #define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ 71 #define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 72 #define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ 73 #define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ 74 #define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ 75 #define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ 76 #define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ 77 #define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ 78 #define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ 79 #define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ 80 #define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 81 #define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ 82 #define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ 83 #define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ 84 #define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ 85 #define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ 86 #define _ACMP_CTRL_HYSTSEL_SHIFT 4 /**< Shift value for ACMP_HYSTSEL */ 87 #define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /**< Bit mask for ACMP_HYSTSEL */ 88 #define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 89 #define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_CTRL */ 90 #define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_CTRL */ 91 #define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_CTRL */ 92 #define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_CTRL */ 93 #define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_CTRL */ 94 #define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_CTRL */ 95 #define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_CTRL */ 96 #define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_CTRL */ 97 #define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_CTRL */ 98 #define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) /**< Shifted mode HYST0 for ACMP_CTRL */ 99 #define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) /**< Shifted mode HYST1 for ACMP_CTRL */ 100 #define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) /**< Shifted mode HYST2 for ACMP_CTRL */ 101 #define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) /**< Shifted mode HYST3 for ACMP_CTRL */ 102 #define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) /**< Shifted mode HYST4 for ACMP_CTRL */ 103 #define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) /**< Shifted mode HYST5 for ACMP_CTRL */ 104 #define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) /**< Shifted mode HYST6 for ACMP_CTRL */ 105 #define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) /**< Shifted mode HYST7 for ACMP_CTRL */ 106 #define _ACMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for ACMP_WARMTIME */ 107 #define _ACMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for ACMP_WARMTIME */ 108 #define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 109 #define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for ACMP_CTRL */ 110 #define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for ACMP_CTRL */ 111 #define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for ACMP_CTRL */ 112 #define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for ACMP_CTRL */ 113 #define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for ACMP_CTRL */ 114 #define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for ACMP_CTRL */ 115 #define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for ACMP_CTRL */ 116 #define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for ACMP_CTRL */ 117 #define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ 118 #define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for ACMP_CTRL */ 119 #define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for ACMP_CTRL */ 120 #define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for ACMP_CTRL */ 121 #define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for ACMP_CTRL */ 122 #define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for ACMP_CTRL */ 123 #define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */ 124 #define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */ 125 #define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */ 126 #define ACMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */ 127 #define _ACMP_CTRL_IRISE_SHIFT 16 /**< Shift value for ACMP_IRISE */ 128 #define _ACMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for ACMP_IRISE */ 129 #define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 130 #define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ 131 #define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ 132 #define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CTRL */ 133 #define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) /**< Shifted mode DISABLED for ACMP_CTRL */ 134 #define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) /**< Shifted mode ENABLED for ACMP_CTRL */ 135 #define ACMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */ 136 #define _ACMP_CTRL_IFALL_SHIFT 17 /**< Shift value for ACMP_IFALL */ 137 #define _ACMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for ACMP_IFALL */ 138 #define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 139 #define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ 140 #define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ 141 #define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CTRL */ 142 #define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) /**< Shifted mode DISABLED for ACMP_CTRL */ 143 #define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) /**< Shifted mode ENABLED for ACMP_CTRL */ 144 #define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ 145 #define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for ACMP_BIASPROG */ 146 #define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ 147 #define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ 148 #define ACMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */ 149 #define _ACMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for ACMP_HALFBIAS */ 150 #define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for ACMP_HALFBIAS */ 151 #define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_CTRL */ 152 #define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for ACMP_CTRL */ 153 #define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ 154 #define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ 155 #define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ 156 #define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ 157 #define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ 158 159 /* Bit fields for ACMP INPUTSEL */ 160 #define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /**< Default value for ACMP_INPUTSEL */ 161 #define _ACMP_INPUTSEL_MASK 0x31013FF7UL /**< Mask for ACMP_INPUTSEL */ 162 #define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ 163 #define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /**< Bit mask for ACMP_POSSEL */ 164 #define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ 165 #define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */ 166 #define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */ 167 #define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */ 168 #define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */ 169 #define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */ 170 #define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */ 171 #define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */ 172 #define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */ 173 #define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ 174 #define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) /**< Shifted mode CH0 for ACMP_INPUTSEL */ 175 #define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) /**< Shifted mode CH1 for ACMP_INPUTSEL */ 176 #define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) /**< Shifted mode CH2 for ACMP_INPUTSEL */ 177 #define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) /**< Shifted mode CH3 for ACMP_INPUTSEL */ 178 #define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) /**< Shifted mode CH4 for ACMP_INPUTSEL */ 179 #define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) /**< Shifted mode CH5 for ACMP_INPUTSEL */ 180 #define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) /**< Shifted mode CH6 for ACMP_INPUTSEL */ 181 #define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) /**< Shifted mode CH7 for ACMP_INPUTSEL */ 182 #define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /**< Shift value for ACMP_NEGSEL */ 183 #define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /**< Bit mask for ACMP_NEGSEL */ 184 #define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */ 185 #define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */ 186 #define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */ 187 #define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */ 188 #define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */ 189 #define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */ 190 #define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */ 191 #define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */ 192 #define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /**< Mode DEFAULT for ACMP_INPUTSEL */ 193 #define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL /**< Mode 1V25 for ACMP_INPUTSEL */ 194 #define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL /**< Mode 2V5 for ACMP_INPUTSEL */ 195 #define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL /**< Mode VDD for ACMP_INPUTSEL */ 196 #define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /**< Mode CAPSENSE for ACMP_INPUTSEL */ 197 #define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) /**< Shifted mode CH0 for ACMP_INPUTSEL */ 198 #define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) /**< Shifted mode CH1 for ACMP_INPUTSEL */ 199 #define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) /**< Shifted mode CH2 for ACMP_INPUTSEL */ 200 #define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) /**< Shifted mode CH3 for ACMP_INPUTSEL */ 201 #define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) /**< Shifted mode CH4 for ACMP_INPUTSEL */ 202 #define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) /**< Shifted mode CH5 for ACMP_INPUTSEL */ 203 #define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) /**< Shifted mode CH6 for ACMP_INPUTSEL */ 204 #define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) /**< Shifted mode CH7 for ACMP_INPUTSEL */ 205 #define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ 206 #define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ 207 #define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ 208 #define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) /**< Shifted mode VDD for ACMP_INPUTSEL */ 209 #define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */ 210 #define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /**< Shift value for ACMP_VDDLEVEL */ 211 #define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /**< Bit mask for ACMP_VDDLEVEL */ 212 #define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ 213 #define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ 214 #define ACMP_INPUTSEL_LPREF (0x1UL << 16) /**< Low Power Reference Mode */ 215 #define _ACMP_INPUTSEL_LPREF_SHIFT 16 /**< Shift value for ACMP_LPREF */ 216 #define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /**< Bit mask for ACMP_LPREF */ 217 #define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_INPUTSEL */ 218 #define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ 219 #define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) /**< Capacitive Sense Mode Internal Resistor Enable */ 220 #define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /**< Shift value for ACMP_CSRESEN */ 221 #define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /**< Bit mask for ACMP_CSRESEN */ 222 #define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ 223 #define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ 224 #define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ 225 #define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /**< Bit mask for ACMP_CSRESSEL */ 226 #define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ 227 #define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ 228 #define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ 229 #define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ 230 #define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ 231 #define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ 232 #define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ 233 #define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ 234 #define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ 235 #define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ 236 237 /* Bit fields for ACMP STATUS */ 238 #define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ 239 #define _ACMP_STATUS_MASK 0x00000003UL /**< Mask for ACMP_STATUS */ 240 #define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ 241 #define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ 242 #define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ 243 #define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ 244 #define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ 245 #define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ 246 #define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ 247 #define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ 248 #define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ 249 #define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ 250 251 /* Bit fields for ACMP IEN */ 252 #define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ 253 #define _ACMP_IEN_MASK 0x00000003UL /**< Mask for ACMP_IEN */ 254 #define ACMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */ 255 #define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ 256 #define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ 257 #define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ 258 #define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ 259 #define ACMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */ 260 #define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ 261 #define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ 262 #define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ 263 #define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ 264 265 /* Bit fields for ACMP IF */ 266 #define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ 267 #define _ACMP_IF_MASK 0x00000003UL /**< Mask for ACMP_IF */ 268 #define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ 269 #define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ 270 #define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ 271 #define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ 272 #define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ 273 #define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ 274 #define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ 275 #define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ 276 #define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ 277 #define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ 278 279 /* Bit fields for ACMP IFS */ 280 #define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ 281 #define _ACMP_IFS_MASK 0x00000003UL /**< Mask for ACMP_IFS */ 282 #define ACMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */ 283 #define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ 284 #define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ 285 #define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ 286 #define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ 287 #define ACMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */ 288 #define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ 289 #define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ 290 #define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ 291 #define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ 292 293 /* Bit fields for ACMP IFC */ 294 #define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ 295 #define _ACMP_IFC_MASK 0x00000003UL /**< Mask for ACMP_IFC */ 296 #define ACMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */ 297 #define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ 298 #define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ 299 #define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ 300 #define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ 301 #define ACMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */ 302 #define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ 303 #define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ 304 #define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ 305 #define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ 306 307 /* Bit fields for ACMP ROUTE */ 308 #define _ACMP_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTE */ 309 #define _ACMP_ROUTE_MASK 0x00000301UL /**< Mask for ACMP_ROUTE */ 310 #define ACMP_ROUTE_ACMPPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ 311 #define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /**< Shift value for ACMP_ACMPPEN */ 312 #define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /**< Bit mask for ACMP_ACMPPEN */ 313 #define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */ 314 #define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTE */ 315 #define _ACMP_ROUTE_LOCATION_SHIFT 8 /**< Shift value for ACMP_LOCATION */ 316 #define _ACMP_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for ACMP_LOCATION */ 317 #define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */ 318 #define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTE */ 319 #define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTE */ 320 #define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTE */ 321 #define _ACMP_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTE */ 322 #define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */ 323 #define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for ACMP_ROUTE */ 324 #define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for ACMP_ROUTE */ 325 #define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */ 326 #define ACMP_ROUTE_LOCATION_LOC3 (_ACMP_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for ACMP_ROUTE */ 327 328 /** @} End of group EFM32G_ACMP */ 329 330 331