1 /**************************************************************************//** 2 * @file 3 * @brief efm32g_aes Register and Bit Field definitions 4 * @author Energy Micro AS 5 * @version 3.0.0 6 ****************************************************************************** 7 * @section License 8 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 9 ****************************************************************************** 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. 17 * 2. Altered source versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software. 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 22 * obligation to support this Software. Energy Micro AS is providing the 23 * Software "AS IS", with no express or implied warranties of any kind, 24 * including, but not limited to, any implied warranties of merchantability 25 * or fitness for any particular purpose or warranties against infringement 26 * of any proprietary rights of a third party. 27 * 28 * Energy Micro AS will not be liable for any consequential, incidental, or 29 * special damages, or any other relief, or for any claim by any third party, 30 * arising from your use of this Software. 31 * 32 *****************************************************************************/ 33 /**************************************************************************//** 34 * @defgroup EFM32G_AES 35 * @{ 36 * @brief EFM32G_AES Register Declaration 37 *****************************************************************************/ 38 typedef struct 39 { 40 __IO uint32_t CTRL; /**< Control Register */ 41 __IO uint32_t CMD; /**< Command Register */ 42 __I uint32_t STATUS; /**< Status Register */ 43 __IO uint32_t IEN; /**< Interrupt Enable Register */ 44 __I uint32_t IF; /**< Interrupt Flag Register */ 45 __IO uint32_t IFS; /**< Interrupt Flag Set Register */ 46 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ 47 __IO uint32_t DATA; /**< DATA Register */ 48 __IO uint32_t XORDATA; /**< XORDATA Register */ 49 uint32_t RESERVED0[3]; /**< Reserved for future use **/ 50 __IO uint32_t KEYLA; /**< KEY Low Register */ 51 __IO uint32_t KEYLB; /**< KEY Low Register */ 52 __IO uint32_t KEYLC; /**< KEY Low Register */ 53 __IO uint32_t KEYLD; /**< KEY Low Register */ 54 __IO uint32_t KEYHA; /**< KEY High Register */ 55 __IO uint32_t KEYHB; /**< KEY High Register */ 56 __IO uint32_t KEYHC; /**< KEY High Register */ 57 __IO uint32_t KEYHD; /**< KEY High Register */ 58 } AES_TypeDef; /** @} */ 59 60 /**************************************************************************//** 61 * @defgroup EFM32G_AES_BitFields 62 * @{ 63 *****************************************************************************/ 64 65 /* Bit fields for AES CTRL */ 66 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ 67 #define _AES_CTRL_MASK 0x00000037UL /**< Mask for AES_CTRL */ 68 #define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */ 69 #define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */ 70 #define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */ 71 #define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 72 #define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ 73 #define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */ 74 #define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */ 75 #define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */ 76 #define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 77 #define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ 78 #define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */ 79 #define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */ 80 #define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */ 81 #define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 82 #define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ 83 #define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */ 84 #define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */ 85 #define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */ 86 #define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 87 #define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ 88 #define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */ 89 #define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */ 90 #define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */ 91 #define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 92 #define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */ 93 94 /* Bit fields for AES CMD */ 95 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ 96 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ 97 #define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */ 98 #define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */ 99 #define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */ 100 #define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 101 #define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ 102 #define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */ 103 #define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */ 104 #define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */ 105 #define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 106 #define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ 107 108 /* Bit fields for AES STATUS */ 109 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ 110 #define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */ 111 #define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */ 112 #define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */ 113 #define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */ 114 #define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 115 #define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ 116 117 /* Bit fields for AES IEN */ 118 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ 119 #define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */ 120 #define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */ 121 #define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 122 #define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 123 #define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 124 #define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ 125 126 /* Bit fields for AES IF */ 127 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ 128 #define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */ 129 #define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */ 130 #define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 131 #define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 132 #define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 133 #define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ 134 135 /* Bit fields for AES IFS */ 136 #define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */ 137 #define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */ 138 #define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */ 139 #define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 140 #define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 141 #define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */ 142 #define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */ 143 144 /* Bit fields for AES IFC */ 145 #define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */ 146 #define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */ 147 #define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */ 148 #define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 149 #define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 150 #define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 151 #define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */ 152 153 /* Bit fields for AES DATA */ 154 #define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */ 155 #define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */ 156 #define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */ 157 #define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */ 158 #define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */ 159 #define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */ 160 161 /* Bit fields for AES XORDATA */ 162 #define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */ 163 #define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */ 164 #define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */ 165 #define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */ 166 #define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */ 167 #define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */ 168 169 /* Bit fields for AES KEYLA */ 170 #define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */ 171 #define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */ 172 #define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */ 173 #define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */ 174 #define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */ 175 #define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */ 176 177 /* Bit fields for AES KEYLB */ 178 #define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */ 179 #define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */ 180 #define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */ 181 #define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */ 182 #define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */ 183 #define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */ 184 185 /* Bit fields for AES KEYLC */ 186 #define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */ 187 #define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */ 188 #define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */ 189 #define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */ 190 #define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */ 191 #define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */ 192 193 /* Bit fields for AES KEYLD */ 194 #define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */ 195 #define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */ 196 #define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */ 197 #define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */ 198 #define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */ 199 #define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */ 200 201 /* Bit fields for AES KEYHA */ 202 #define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */ 203 #define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */ 204 #define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */ 205 #define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */ 206 #define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */ 207 #define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */ 208 209 /* Bit fields for AES KEYHB */ 210 #define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */ 211 #define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */ 212 #define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */ 213 #define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */ 214 #define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */ 215 #define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */ 216 217 /* Bit fields for AES KEYHC */ 218 #define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */ 219 #define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */ 220 #define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */ 221 #define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */ 222 #define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */ 223 #define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */ 224 225 /* Bit fields for AES KEYHD */ 226 #define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */ 227 #define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */ 228 #define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */ 229 #define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */ 230 #define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */ 231 #define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */ 232 233 /** @} End of group EFM32G_AES */ 234 235 236