1 /**************************************************************************//** 2 * @file 3 * @brief efm32g_lcd Register and Bit Field definitions 4 * @author Energy Micro AS 5 * @version 3.0.0 6 ****************************************************************************** 7 * @section License 8 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 9 ****************************************************************************** 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. 17 * 2. Altered source versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software. 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 22 * obligation to support this Software. Energy Micro AS is providing the 23 * Software "AS IS", with no express or implied warranties of any kind, 24 * including, but not limited to, any implied warranties of merchantability 25 * or fitness for any particular purpose or warranties against infringement 26 * of any proprietary rights of a third party. 27 * 28 * Energy Micro AS will not be liable for any consequential, incidental, or 29 * special damages, or any other relief, or for any claim by any third party, 30 * arising from your use of this Software. 31 * 32 *****************************************************************************/ 33 /**************************************************************************//** 34 * @defgroup EFM32G_LCD 35 * @{ 36 * @brief EFM32G_LCD Register Declaration 37 *****************************************************************************/ 38 typedef struct 39 { 40 __IO uint32_t CTRL; /**< Control Register */ 41 __IO uint32_t DISPCTRL; /**< Display Control Register */ 42 __IO uint32_t SEGEN; /**< Segment Enable Register */ 43 __IO uint32_t BACTRL; /**< Blink and Animation Control Register */ 44 __I uint32_t STATUS; /**< Status Register */ 45 __IO uint32_t AREGA; /**< Animation Register A */ 46 __IO uint32_t AREGB; /**< Animation Register B */ 47 __I uint32_t IF; /**< Interrupt Flag Register */ 48 __IO uint32_t IFS; /**< Interrupt Flag Set Register */ 49 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ 50 __IO uint32_t IEN; /**< Interrupt Enable Register */ 51 52 uint32_t RESERVED0[5]; /**< Reserved for future use **/ 53 __IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */ 54 __IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */ 55 __IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */ 56 __IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */ 57 __IO uint32_t SEGD0H; /**< Segment Data High Register 0 */ 58 __IO uint32_t SEGD1H; /**< Segment Data High Register 1 */ 59 __IO uint32_t SEGD2H; /**< Segment Data High Register 2 */ 60 __IO uint32_t SEGD3H; /**< Segment Data High Register 3 */ 61 62 __IO uint32_t FREEZE; /**< Freeze Register */ 63 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 64 } LCD_TypeDef; /** @} */ 65 66 /**************************************************************************//** 67 * @defgroup EFM32G_LCD_BitFields 68 * @{ 69 *****************************************************************************/ 70 71 /* Bit fields for LCD CTRL */ 72 #define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */ 73 #define _LCD_CTRL_MASK 0x00000007UL /**< Mask for LCD_CTRL */ 74 #define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */ 75 #define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */ 76 #define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ 77 #define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ 78 #define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */ 79 #define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ 80 #define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ 81 #define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ 82 #define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ 83 #define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */ 84 #define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */ 85 #define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ 86 #define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ 87 #define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ 88 #define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ 89 90 /* Bit fields for LCD DISPCTRL */ 91 #define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */ 92 #define _LCD_DISPCTRL_MASK 0x001D9F1FUL /**< Mask for LCD_DISPCTRL */ 93 #define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ 94 #define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */ 95 #define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 96 #define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ 97 #define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ 98 #define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ 99 #define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ 100 #define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 101 #define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ 102 #define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ 103 #define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ 104 #define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ 105 #define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */ 106 #define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */ 107 #define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 108 #define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ 109 #define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ 110 #define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ 111 #define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 112 #define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */ 113 #define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ 114 #define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ 115 #define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ 116 #define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ 117 #define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ 118 #define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 119 #define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */ 120 #define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */ 121 #define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 122 #define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */ 123 #define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */ 124 #define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */ 125 #define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */ 126 #define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */ 127 #define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */ 128 #define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */ 129 #define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */ 130 #define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 131 #define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */ 132 #define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */ 133 #define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */ 134 #define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */ 135 #define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 136 #define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */ 137 #define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */ 138 #define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 139 #define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */ 140 #define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */ 141 #define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */ 142 #define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */ 143 #define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */ 144 #define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 145 #define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */ 146 #define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */ 147 #define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 148 #define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */ 149 #define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */ 150 #define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */ 151 #define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */ 152 #define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */ 153 #define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */ 154 #define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */ 155 #define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */ 156 #define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */ 157 #define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */ 158 #define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */ 159 #define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */ 160 #define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */ 161 #define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */ 162 #define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */ 163 #define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */ 164 #define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 165 #define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */ 166 #define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */ 167 #define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */ 168 #define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */ 169 #define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */ 170 171 /* Bit fields for LCD SEGEN */ 172 #define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */ 173 #define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */ 174 #define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */ 175 #define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */ 176 #define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */ 177 #define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */ 178 179 /* Bit fields for LCD BACTRL */ 180 #define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ 181 #define _LCD_BACTRL_MASK 0x00FF01FFUL /**< Mask for LCD_BACTRL */ 182 #define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ 183 #define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ 184 #define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ 185 #define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 186 #define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ 187 #define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ 188 #define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ 189 #define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ 190 #define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 191 #define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ 192 #define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ 193 #define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ 194 #define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ 195 #define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 196 #define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ 197 #define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ 198 #define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ 199 #define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 200 #define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ 201 #define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ 202 #define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ 203 #define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ 204 #define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ 205 #define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ 206 #define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ 207 #define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ 208 #define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ 209 #define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 210 #define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ 211 #define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ 212 #define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ 213 #define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ 214 #define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ 215 #define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ 216 #define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ 217 #define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ 218 #define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ 219 #define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ 220 #define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 221 #define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ 222 #define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ 223 #define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ 224 #define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ 225 #define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ 226 #define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ 227 #define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ 228 #define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ 229 #define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 230 #define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ 231 #define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ 232 #define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ 233 #define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 234 #define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */ 235 #define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */ 236 #define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */ 237 #define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */ 238 #define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */ 239 #define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */ 240 #define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */ 241 #define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */ 242 #define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */ 243 #define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ 244 #define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ 245 #define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 246 #define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */ 247 248 /* Bit fields for LCD STATUS */ 249 #define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ 250 #define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */ 251 #define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ 252 #define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ 253 #define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ 254 #define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ 255 #define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ 256 #define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ 257 #define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ 258 #define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ 259 #define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ 260 261 /* Bit fields for LCD AREGA */ 262 #define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ 263 #define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ 264 #define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ 265 #define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ 266 #define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ 267 #define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ 268 269 /* Bit fields for LCD AREGB */ 270 #define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ 271 #define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ 272 #define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ 273 #define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ 274 #define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ 275 #define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ 276 277 /* Bit fields for LCD IF */ 278 #define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ 279 #define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */ 280 #define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */ 281 #define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ 282 #define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 283 #define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ 284 #define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ 285 286 /* Bit fields for LCD IFS */ 287 #define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */ 288 #define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */ 289 #define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */ 290 #define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */ 291 #define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 292 #define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */ 293 #define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */ 294 295 /* Bit fields for LCD IFC */ 296 #define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */ 297 #define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */ 298 #define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */ 299 #define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */ 300 #define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 301 #define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */ 302 #define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */ 303 304 /* Bit fields for LCD IEN */ 305 #define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ 306 #define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */ 307 #define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */ 308 #define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ 309 #define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 310 #define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ 311 #define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ 312 313 /* Bit fields for LCD SEGD0L */ 314 #define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */ 315 #define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */ 316 #define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */ 317 #define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */ 318 #define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */ 319 #define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */ 320 321 /* Bit fields for LCD SEGD1L */ 322 #define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */ 323 #define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */ 324 #define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */ 325 #define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */ 326 #define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */ 327 #define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */ 328 329 /* Bit fields for LCD SEGD2L */ 330 #define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */ 331 #define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */ 332 #define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */ 333 #define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */ 334 #define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */ 335 #define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */ 336 337 /* Bit fields for LCD SEGD3L */ 338 #define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */ 339 #define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */ 340 #define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */ 341 #define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */ 342 #define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */ 343 #define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */ 344 345 /* Bit fields for LCD SEGD0H */ 346 #define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */ 347 #define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */ 348 #define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */ 349 #define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */ 350 #define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */ 351 #define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */ 352 353 /* Bit fields for LCD SEGD1H */ 354 #define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */ 355 #define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */ 356 #define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */ 357 #define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */ 358 #define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */ 359 #define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */ 360 361 /* Bit fields for LCD SEGD2H */ 362 #define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */ 363 #define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */ 364 #define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */ 365 #define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */ 366 #define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */ 367 #define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */ 368 369 /* Bit fields for LCD SEGD3H */ 370 #define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */ 371 #define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */ 372 #define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */ 373 #define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */ 374 #define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */ 375 #define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */ 376 377 /* Bit fields for LCD FREEZE */ 378 #define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */ 379 #define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */ 380 #define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 381 #define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */ 382 #define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */ 383 #define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */ 384 #define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */ 385 #define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */ 386 #define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */ 387 #define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */ 388 #define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */ 389 390 /* Bit fields for LCD SYNCBUSY */ 391 #define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */ 392 #define _LCD_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for LCD_SYNCBUSY */ 393 #define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< LCD_CTRL Register Busy */ 394 #define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */ 395 #define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */ 396 #define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 397 #define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 398 #define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< LCD_BACTRL Register Busy */ 399 #define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */ 400 #define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */ 401 #define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 402 #define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 403 #define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< LCD_AREGA Register Busy */ 404 #define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */ 405 #define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */ 406 #define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 407 #define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 408 #define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< LCD_AREGB Register Busy */ 409 #define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */ 410 #define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */ 411 #define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 412 #define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 413 #define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< LCD_SEGD0L Register Busy */ 414 #define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */ 415 #define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */ 416 #define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 417 #define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 418 #define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< LCD_SEGD1L Register Busy */ 419 #define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */ 420 #define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */ 421 #define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 422 #define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 423 #define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< LCD_SEGD2L Register Busy */ 424 #define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */ 425 #define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */ 426 #define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 427 #define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 428 #define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< LCD_SEGD3L Register Busy */ 429 #define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */ 430 #define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */ 431 #define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 432 #define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 433 #define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< LCD_SEGD0H Register Busy */ 434 #define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */ 435 #define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */ 436 #define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 437 #define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 438 #define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< LCD_SEGD1H Register Busy */ 439 #define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */ 440 #define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */ 441 #define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 442 #define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 443 #define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< LCD_SEGD2H Register Busy */ 444 #define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */ 445 #define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */ 446 #define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 447 #define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 448 #define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< LCD_SEGD3H Register Busy */ 449 #define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */ 450 #define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */ 451 #define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 452 #define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 453 454 /** @} End of group EFM32G_LCD */ 455 456 457