1 /**************************************************************************//** 2 * @file 3 * @brief efm32g_rtc Register and Bit Field definitions 4 * @author Energy Micro AS 5 * @version 3.0.0 6 ****************************************************************************** 7 * @section License 8 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 9 ****************************************************************************** 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. 17 * 2. Altered source versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software. 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 22 * obligation to support this Software. Energy Micro AS is providing the 23 * Software "AS IS", with no express or implied warranties of any kind, 24 * including, but not limited to, any implied warranties of merchantability 25 * or fitness for any particular purpose or warranties against infringement 26 * of any proprietary rights of a third party. 27 * 28 * Energy Micro AS will not be liable for any consequential, incidental, or 29 * special damages, or any other relief, or for any claim by any third party, 30 * arising from your use of this Software. 31 * 32 *****************************************************************************/ 33 /**************************************************************************//** 34 * @defgroup EFM32G_RTC 35 * @{ 36 * @brief EFM32G_RTC Register Declaration 37 *****************************************************************************/ 38 typedef struct 39 { 40 __IO uint32_t CTRL; /**< Control Register */ 41 __I uint32_t CNT; /**< Counter Value Register */ 42 __IO uint32_t COMP0; /**< Compare Value Register 0 */ 43 __IO uint32_t COMP1; /**< Compare Value Register 1 */ 44 __I uint32_t IF; /**< Interrupt Flag Register */ 45 __IO uint32_t IFS; /**< Interrupt Flag Set Register */ 46 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ 47 __IO uint32_t IEN; /**< Interrupt Enable Register */ 48 49 __IO uint32_t FREEZE; /**< Freeze Register */ 50 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 51 } RTC_TypeDef; /** @} */ 52 53 /**************************************************************************//** 54 * @defgroup EFM32G_RTC_BitFields 55 * @{ 56 *****************************************************************************/ 57 58 /* Bit fields for RTC CTRL */ 59 #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */ 60 #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */ 61 #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */ 62 #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ 63 #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ 64 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 65 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */ 66 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ 67 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ 68 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ 69 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 70 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */ 71 #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */ 72 #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ 73 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ 74 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ 75 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */ 76 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */ 77 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */ 78 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */ 79 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */ 80 81 /* Bit fields for RTC CNT */ 82 #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */ 83 #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */ 84 #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ 85 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */ 86 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */ 87 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */ 88 89 /* Bit fields for RTC COMP0 */ 90 #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */ 91 #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */ 92 #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */ 93 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */ 94 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */ 95 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */ 96 97 /* Bit fields for RTC COMP1 */ 98 #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */ 99 #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */ 100 #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */ 101 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */ 102 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */ 103 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */ 104 105 /* Bit fields for RTC IF */ 106 #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */ 107 #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */ 108 #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 109 #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ 110 #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 111 #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 112 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */ 113 #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */ 114 #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 115 #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 116 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 117 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */ 118 #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */ 119 #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 120 #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 121 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ 122 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */ 123 124 /* Bit fields for RTC IFS */ 125 #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */ 126 #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */ 127 #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */ 128 #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ 129 #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 130 #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 131 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */ 132 #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */ 133 #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 134 #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 135 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 136 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */ 137 #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */ 138 #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 139 #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 140 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ 141 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */ 142 143 /* Bit fields for RTC IFC */ 144 #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */ 145 #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */ 146 #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */ 147 #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ 148 #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 149 #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 150 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */ 151 #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */ 152 #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 153 #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 154 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 155 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */ 156 #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */ 157 #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 158 #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 159 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ 160 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */ 161 162 /* Bit fields for RTC IEN */ 163 #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */ 164 #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */ 165 #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ 166 #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ 167 #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 168 #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 169 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */ 170 #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */ 171 #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 172 #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 173 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 174 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */ 175 #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */ 176 #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 177 #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 178 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ 179 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */ 180 181 /* Bit fields for RTC FREEZE */ 182 #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */ 183 #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */ 184 #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 185 #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */ 186 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */ 187 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */ 188 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */ 189 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */ 190 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */ 191 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */ 192 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */ 193 194 /* Bit fields for RTC SYNCBUSY */ 195 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */ 196 #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */ 197 #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< RTC_CTRL Register Busy */ 198 #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */ 199 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */ 200 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ 201 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ 202 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< RTC_COMP0 Register Busy */ 203 #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ 204 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ 205 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ 206 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ 207 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< RTC_COMP1 Register Busy */ 208 #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ 209 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ 210 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ 211 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ 212 213 /** @} End of group EFM32G_RTC */ 214 215 216