1 /** 2 ********************************************************************************* 3 * 4 * @file ald_i2c.h 5 * @brief Header file of I2C driver 6 * 7 * @version V1.0 8 * @date 15 Nov 2017 9 * @author AE Team 10 * @note 11 * 12 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 13 * 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the License); you may 17 * not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 * 28 ******************************************************************************** 29 */ 30 31 #ifndef __ALD_I2C_H__ 32 #define __ALD_I2C_H__ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include "utils.h" 39 #include "ald_dma.h" 40 #include "ald_cmu.h" 41 42 /** @addtogroup ES32FXXX_ALD 43 * @{ 44 */ 45 46 /** @addtogroup I2C 47 * @{ 48 */ 49 50 /** @defgroup I2C_Public_Types I2C Public Types 51 * @{ 52 */ 53 /** 54 * @brief I2C Error Code 55 */ 56 typedef enum { 57 I2C_ERROR_NONE = 0x0U, /**< No error */ 58 I2C_ERROR_BERR = 0x1U, /**< Berr error */ 59 I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ 60 I2C_ERROR_AF = 0x4U, /**< Af error */ 61 I2C_ERROR_OVR = 0x8U, /**< Ovr error */ 62 I2C_ERROR_DMA = 0x10U, /**< Dma error */ 63 I2C_ERROR_TIMEOUT = 0x20U, /**< Timeout error */ 64 } i2c_error_t; 65 66 /** 67 * @brief I2C state structure definition 68 */ 69 typedef enum { 70 I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ 71 I2C_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ 72 I2C_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ 73 I2C_STATE_BUSY_TX = 0x3U, /**< Data Transmission process is ongoing */ 74 I2C_STATE_BUSY_RX = 0x4U, /**< Data Reception process is ongoing */ 75 I2C_STATE_TIMEOUT = 0x5U, /**< timeout state */ 76 I2C_STATE_ERROR = 0x6U, /**< Error */ 77 } i2c_state_t; 78 79 /** 80 * @brief I2C Duty Cycle 81 */ 82 typedef enum { 83 I2C_DUTYCYCLE_2 = 0x0U, /**< duty cycle is 2 */ 84 I2C_DUTYCYCLE_16_9 = 0x4000U, /**< duty cycle is 16/9 */ 85 } i2c_duty_t; 86 87 /** 88 * @brief I2C Addressing Mode 89 */ 90 typedef enum { 91 I2C_ADDR_7BIT = 0x1U, /**< 7 bit address */ 92 I2C_ADDR_10BIT = 0x2U, /**< 10 bit address */ 93 } i2c_addr_t; 94 95 /** 96 * @brief I2C Dual Addressing Mode 97 */ 98 typedef enum { 99 I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ 100 I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ 101 } i2c_dual_addr_t; 102 103 /** 104 * @brief I2C General Call Addressing mode 105 */ 106 typedef enum { 107 I2C_GENERALCALL_DISABLE = 0x0U, /**< feneral call address is disable */ 108 I2C_GENERALCALL_ENABLE = 0x40U, /**< feneral call address is enable */ 109 } i2c_general_addr_t; 110 111 /** 112 * @brief I2C Nostretch Mode 113 */ 114 typedef enum { 115 I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ 116 I2C_NOSTRETCH_ENABLE = 0x80U, /**< Nostretch enable */ 117 } i2c_nostretch_t; 118 119 /** 120 * @brief I2C Memory Address Size 121 */ 122 typedef enum { 123 I2C_MEMADD_SIZE_8BIT = 0x1U, /**< 8 bit memory address size */ 124 I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ 125 } i2c_addr_size_t; 126 127 /** 128 * @brief I2C Flag Definition 129 */ 130 typedef enum { 131 I2C_FLAG_SB = (1U << 0), 132 I2C_FLAG_ADDR = (1U << 1), 133 I2C_FLAG_BTF = (1U << 2), 134 I2C_FLAG_ADD10 = (1U << 3), 135 I2C_FLAG_STOPF = (1U << 4), 136 I2C_FLAG_RXNE = (1U << 6), 137 I2C_FLAG_TXE = (1U << 7), 138 I2C_FLAG_BERR = (1U << 8), 139 I2C_FLAG_ARLO = (1U << 9), 140 I2C_FLAG_AF = (1U << 10), 141 I2C_FLAG_OVR = (1U << 11), 142 I2C_FLAG_PECERR = (1U << 12), 143 I2C_FLAG_TIMEOUT = (1U << 14), 144 I2C_FLAG_SMBALERT = (1U << 15), 145 I2C_FLAG_MSL = (1U << 16), 146 I2C_FLAG_BUSY = (1U << 17), 147 I2C_FLAG_TRA = (1U << 18), 148 I2C_FLAG_GENCALL = (1U << 20), 149 I2C_FLAG_SMBDEFAULT = (1U << 21), 150 I2C_FLAG_SMBHOST = (1U << 22), 151 I2C_FLAG_DUALF = (1U << 23), 152 } i2c_flag_t; 153 154 /** 155 * @brief I2C mode structure definition 156 */ 157 typedef enum 158 { 159 I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ 160 I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ 161 I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ 162 I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ 163 } i2c_mode_t; 164 165 /** 166 * @brief I2C Clock 167 */ 168 typedef enum { 169 I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ 170 I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ 171 } i2c_clock_t; 172 173 /** 174 * @brief Interrupt Configuration Definition 175 */ 176 typedef enum { 177 I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ 178 I2C_IT_EVT = (1U << 9), /**< Event interrupt */ 179 I2C_IT_ERR = (1U << 8), /**< Error interrupt */ 180 } i2c_interrupt_t; 181 182 /** 183 * @brief I2C CON1 Register 184 */ 185 typedef enum { 186 I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ 187 I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ 188 I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ 189 I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ 190 I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ 191 I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ 192 I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ 193 I2C_CON1_START = (1U << 8), /**< START BIT */ 194 I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ 195 I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ 196 I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ 197 I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ 198 I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ 199 I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ 200 } i2c_con1_t; 201 202 /** 203 * @brief I2C CON2 Register 204 */ 205 typedef enum { 206 I2C_CON2_CLKF = 0x3FU, /**< CLKF BITS */ 207 I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ 208 I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ 209 I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ 210 I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ 211 I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ 212 I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ 213 I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ 214 I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ 215 I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ 216 I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ 217 I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ 218 } i2c_con2_t; 219 220 /** 221 * @brief I2C ADDR1 Register 222 */ 223 typedef enum { 224 I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ 225 I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ 226 I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ 227 I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ 228 I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ 229 I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ 230 I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ 231 I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ 232 I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ 233 I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ 234 I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ 235 } i2c_addr1_t; 236 237 /** 238 * @brief I2C ADDR2 Register 239 */ 240 typedef enum { 241 I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ 242 I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ 243 } i2c_addr2_t; 244 245 /** 246 * @brief I2C STAT1 Register 247 */ 248 typedef enum { 249 I2C_STAT1_SB = (1U << 0), /**< SB BIT */ 250 I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ 251 I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ 252 I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ 253 I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ 254 I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ 255 I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ 256 I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ 257 I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ 258 I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ 259 I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ 260 I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ 261 I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ 262 I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ 263 } i2c_stat1_t; 264 265 /** 266 * @brief I2C STAT2 Register 267 */ 268 typedef enum { 269 I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ 270 I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ 271 I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ 272 I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ 273 I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ 274 I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ 275 I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ 276 I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ 277 } i2c_stat2_t; 278 279 /** 280 * @brief I2C CKCFG Register 281 */ 282 typedef enum { 283 I2C_CKCFG_CLKSET = 0xFFFU, /**< CLKSET BITS */ 284 I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ 285 I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ 286 } i2c_ckcfg_t; 287 288 /** 289 * @brief I2C RT Register 290 */ 291 typedef enum { 292 I2C_RT_RISET = 0x3FU, /**< RISET BITS */ 293 } i2c_trise_t; 294 295 /** 296 * @brief I2C Configuration Structure definition 297 */ 298 typedef struct { 299 uint32_t clk_speed; /**< Specifies the clock frequency */ 300 i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ 301 uint32_t own_addr1; /**< Specifies the first device own address */ 302 i2c_addr_t addr_mode; /**< Specifies addressing mode */ 303 i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ 304 uint32_t own_addr2; /**< Specifies the second device own address */ 305 i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ 306 i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ 307 } i2c_init_t; 308 309 /** 310 * @brief I2C handle Structure definition 311 */ 312 typedef struct i2c_handle_s { 313 I2C_TypeDef *perh; /**< I2C registers base address */ 314 i2c_init_t init; /**< I2C communication parameters */ 315 uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ 316 uint16_t xfer_size; /**< I2C transfer size */ 317 __IO uint16_t xfer_count; /**< I2C transfer counter */ 318 #ifdef ALD_DMA 319 dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ 320 dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ 321 #endif 322 lock_state_t lock; /**< I2C locking object */ 323 __IO i2c_state_t state; /**< I2C communication state */ 324 __IO i2c_mode_t mode; /**< I2C communication mode */ 325 __IO uint32_t error_code; /**< I2C Error code */ 326 327 void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ 328 void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ 329 void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ 330 void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ 331 void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ 332 void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ 333 void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ 334 } i2c_handle_t; 335 336 /** 337 * @} 338 */ 339 340 /** @defgroup I2C_Public_Macro I2C Public Macros 341 * @{ 342 */ 343 #define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) 344 #define I2C_CLEAR_ADDRFLAG(x) \ 345 do { \ 346 __IO uint32_t tmpreg; \ 347 tmpreg = (x)->perh->STAT1; \ 348 tmpreg = (x)->perh->STAT2; \ 349 UNUSED(tmpreg); \ 350 } while (0) 351 #define __I2C_CLEAR_STOPFLAG(x) \ 352 do { \ 353 __IO uint32_t tmpreg; \ 354 tmpreg = (x)->perh->STAT1; \ 355 tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ 356 UNUSED(tmpreg); \ 357 } while (0) 358 #define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) 359 #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) 360 /** 361 * @} 362 */ 363 364 /** @defgroup I2C_Private_Macro I2C Private Macros 365 * @{ 366 */ 367 #define IS_I2C_TYPE(x) (((x) == I2C0) || \ 368 ((x) == I2C1)) 369 #define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ 370 ((x) == I2C_ADDR_10BIT)) 371 #define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ 372 ((x) == I2C_DUALADDR_ENABLE)) 373 #define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ 374 ((x) == I2C_GENERALCALL_ENABLE)) 375 #define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ 376 ((x) == I2C_MEMADD_SIZE_16BIT)) 377 #define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ 378 ((x) == I2C_NOSTRETCH_ENABLE)) 379 #define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) 380 #define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) 381 #define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) 382 #define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ 383 ((x) == I2C_DUTYCYCLE_16_9)) 384 #define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ 385 ((x) == I2C_IT_EVT) || \ 386 ((x) == I2C_IT_ERR)) 387 #define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ 388 ((x) == I2C_FLAG_ADDR) || \ 389 ((x) == I2C_FLAG_BTF) || \ 390 ((x) == I2C_FLAG_ADD10) || \ 391 ((x) == I2C_FLAG_STOPF) || \ 392 ((x) == I2C_FLAG_RXNE) || \ 393 ((x) == I2C_FLAG_TXE) || \ 394 ((x) == I2C_FLAG_BERR) || \ 395 ((x) == I2C_FLAG_ARLO) || \ 396 ((x) == I2C_FLAG_AF) || \ 397 ((x) == I2C_FLAG_OVR) || \ 398 ((x) == I2C_FLAG_PECERR) || \ 399 ((x) == I2C_FLAG_TIMEOUT) || \ 400 ((x) == I2C_FLAG_SMBALERT) || \ 401 ((x) == I2C_FLAG_MSL) || \ 402 ((x) == I2C_FLAG_BUSY) || \ 403 ((x) == I2C_FLAG_TRA) || \ 404 ((x) == I2C_FLAG_GENCALL) || \ 405 ((x) == I2C_FLAG_SMBDEFAULT) || \ 406 ((x) == I2C_FLAG_SMBHOST) || \ 407 ((x) == I2C_FLAG_DUALF)) 408 409 #define I2C_FREQ_RANGE(x) ((x) / 1000000) 410 #define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ 411 ((((x) * 300) / 1000) + 1)) 412 #define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ 413 ((x) / ((y) << 1))) 414 #define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ 415 (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) 416 #define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ 417 ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ 418 ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) 419 #define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ 420 (uint16_t)(0xFF00))) >> 8))) 421 #define I2C_MEM_ADD_LSB(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) 422 #define I2C_7BIT_ADD_WRITE(x) ((uint8_t)((x) & (~I2C_ADDR1_ADDH0))) 423 #define I2C_7BIT_ADD_READ(x) ((uint8_t)((x) | I2C_ADDR1_ADDH0)) 424 #define I2C_10BIT_ADDRESS(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) 425 #define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ 426 (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) 427 #define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ 428 (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) 429 /** 430 * @} 431 */ 432 433 /** @addtogroup I2C_Public_Functions 434 * @{ 435 */ 436 437 /** @addtogroup I2C_Public_Functions_Group1 438 * @{ 439 */ 440 ald_status_t ald_i2c_init(i2c_handle_t *hperh); 441 ald_status_t ald_i2c_reset(i2c_handle_t *hperh); 442 443 /** 444 * @} 445 */ 446 447 /** @addtogroup I2C_Public_Functions_Group2 448 * @{ 449 */ 450 /** Blocking mode: Polling */ 451 ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, 452 uint8_t *buf, uint16_t size, uint32_t timeout); 453 ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, 454 uint8_t *buf, uint16_t size, uint32_t timeout); 455 ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); 456 ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); 457 ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 458 i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); 459 ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 460 i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); 461 ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); 462 463 /** Non-Blocking mode: Interrupt */ 464 ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); 465 ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); 466 ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); 467 ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); 468 ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 469 i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); 470 ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 471 i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); 472 473 #ifdef ALD_DMA 474 /** Non-Blocking mode: DMA */ 475 ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, 476 uint8_t *buf, uint16_t size, uint8_t channel); 477 ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, 478 uint8_t *buf, uint16_t size, uint8_t channel); 479 ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); 480 ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); 481 ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, 482 uint8_t *buf, uint16_t size, uint8_t channel); 483 ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 484 i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); 485 #endif 486 /** 487 * @} 488 */ 489 490 /** @addtogroup I2C_Public_Functions_Group3 491 * @{ 492 */ 493 i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh); 494 uint32_t ald_i2c_get_error(i2c_handle_t *hperh); 495 flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); 496 flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); 497 void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); 498 /** 499 * @} 500 */ 501 502 /** @addtogroup I2C_Public_Functions_Group4 503 * @{ 504 */ 505 void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); 506 void ald_i2c_ev_irq_handler(i2c_handle_t *hperh); 507 void ald_i2c_er_irq_handler(i2c_handle_t *hperh); 508 /** 509 * @} 510 */ 511 512 /** 513 * @} 514 */ 515 516 /** 517 * @} 518 */ 519 520 /** 521 * @} 522 */ 523 #ifdef __cplusplus 524 } 525 #endif 526 527 #endif /* __ALD_I2C_H__ */ 528