1 /* 2 * Change Logs: 3 * Date Author Notes 4 * 2021-04-20 liuhy the first version 5 * 6 * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved. 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 * 10 * Licensed under the Apache License, Version 2.0 (the License); you may 11 * not use this file except in compliance with the License. 12 * You may obtain a copy of the License at 13 * 14 * www.apache.org/licenses/LICENSE-2.0 15 * 16 * Unless required by applicable law or agreed to in writing, software 17 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 18 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 19 * See the License for the specific language governing permissions and 20 * limitations under the License. 21 * 22 */ 23 24 #ifndef __ES_CONF_INFO_SPI_H__ 25 #define __ES_CONF_INFO_SPI_H__ 26 27 #include "es_conf_info_map.h" 28 #include <ald_spi.h> 29 #include <ald_gpio.h> 30 #include <ald_cmu.h> 31 32 /* SPI 配置 */ 33 34 #define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \ 35 _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \ 36 ES_SPI##_I_##_WIRE_3_4 | \ 37 ES_SPI##_I_##_CPHA_1_2 | \ 38 ES_SPI##_I_##_CPOL_H_L | \ 39 ES_SPI##_I_##_CS | \ 40 ES_SPI##_I_##_M_L_SB ); \ 41 _CONF_.data_width = ES_SPI##_I_##_DATA_W; \ 42 _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \ 43 }while(0) 44 45 46 // spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ 47 // spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ 48 // spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ 49 // spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ 50 // spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ 51 // spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ 52 // spi_config.data_width = 8; /* 数据长度：8 */ 53 // spi_config.max_hz = 2000000; /* 最快时钟频率 */ 54 55 #define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL 56 #define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL 57 58 #define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA 59 #define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA 60 61 #define ES_C_SPI_MSB RT_SPI_MSB 62 #define ES_C_SPI_LSB RT_SPI_LSB 63 64 #define ES_C_SPI_CS_LOW_LEVEL 0 65 #define ES_C_SPI_CS_HIGH_LEVEL 1 66 67 /* codes_main */ 68 69 70 #ifndef ES_DEVICE_NAME_SPI0_BUS 71 #define ES_DEVICE_NAME_SPI0_BUS "spi0" 72 #endif 73 #ifndef ES_DEVICE_NAME_SPI0_DEV0 74 #define ES_DEVICE_NAME_SPI0_DEV0 "spi00" 75 #endif 76 77 #ifndef ES_DEVICE_NAME_SPI1_BUS 78 #define ES_DEVICE_NAME_SPI1_BUS "spi1" 79 #endif 80 #ifndef ES_DEVICE_NAME_SPI1_DEV0 81 #define ES_DEVICE_NAME_SPI1_DEV0 "spi10" 82 #endif 83 84 #ifndef ES_DEVICE_NAME_SPI2_BUS 85 #define ES_DEVICE_NAME_SPI2_BUS "spi2" 86 #endif 87 #ifndef ES_DEVICE_NAME_SPI2_DEV0 88 #define ES_DEVICE_NAME_SPI2_DEV0 "spi20" 89 #endif 90 91 92 #define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL 93 94 #ifndef ES_SPI0_CPHA_1_2 95 #define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND 96 #endif 97 #ifndef ES_SPI0_CPOL_H_L 98 #define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH 99 #endif 100 #ifndef ES_SPI0_M_L_SB 101 #define ES_SPI0_M_L_SB RT_SPI_MSB 102 #endif 103 #ifndef ES_SPI0_MAX_HZ 104 #define ES_SPI0_MAX_HZ 2000000 105 #endif 106 #ifndef ES_SPI0_NSS_PIN 107 #define ES_SPI0_NSS_PIN 0xFFFFFFFF 108 #endif 109 110 #ifndef ES_SPI1_CPHA_1_2 111 #define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND 112 #endif 113 #ifndef ES_SPI1_CPOL_H_L 114 #define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH 115 #endif 116 #ifndef ES_SPI1_M_L_SB 117 #define ES_SPI1_M_L_SB RT_SPI_MSB 118 #endif 119 #ifndef ES_SPI1_MAX_HZ 120 #define ES_SPI1_MAX_HZ 2000000 121 #endif 122 #ifndef ES_SPI1_NSS_PIN 123 #define ES_SPI1_NSS_PIN 0xFFFFFFFF 124 #endif 125 126 #ifndef ES_SPI2_CPHA_1_2 127 #define ES_SPI2_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND 128 #endif 129 #ifndef ES_SPI2_CPOL_H_L 130 #define ES_SPI2_CPOL_H_L ES_C_SPI_CLK_POL_HIGH 131 #endif 132 #ifndef ES_SPI2_M_L_SB 133 #define ES_SPI2_M_L_SB RT_SPI_MSB 134 #endif 135 #ifndef ES_SPI2_MAX_HZ 136 #define ES_SPI2_MAX_HZ 2000000 137 #endif 138 #ifndef ES_SPI2_NSS_PIN 139 #define ES_SPI2_NSS_PIN 0xFFFFFFFF 140 #endif 141 142 143 #define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE 144 #define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE 145 #define ES_SPI0_CS RT_SPI_NO_CS 146 #define ES_SPI0_DATA_W 8 147 148 #define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE 149 #define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE 150 #define ES_SPI1_CS RT_SPI_NO_CS 151 #define ES_SPI1_DATA_W 8 152 153 #define ES_SPI2_MASTER_SLAVE !RT_SPI_SLAVE 154 #define ES_SPI2_WIRE_3_4 !RT_SPI_3WIRE 155 #define ES_SPI2_CS RT_SPI_NO_CS 156 #define ES_SPI2_DATA_W 8 157 158 159 #endif 160