1 /*
2 * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * Change Logs:
19 * Date Author Notes
20 * 2020-01-14 wangyq the first version
21 * 2021-04-20 liuhy the second version
22 */
23
24 #include "board.h"
25 #include "drv_gpio.h"
26
27 /*管脚映射在 es_conf_info_map.h 的 pins[] 中*/
28
29 #ifdef RT_USING_PIN
30
31
32 struct pin_irq_map
33 {
34 rt_uint16_t pinbit;
35 IRQn_Type irqno;
36 };
37
38 static const struct pin_irq_map pin_irq_map[] =
39 {
40 {GPIO_PIN_0, EXTI0_IRQn},
41 {GPIO_PIN_1, EXTI1_IRQn},
42 {GPIO_PIN_2, EXTI2_IRQn},
43 {GPIO_PIN_3, EXTI3_IRQn},
44 {GPIO_PIN_4, EXTI4_IRQn},
45 {GPIO_PIN_5, EXTI5_IRQn},
46 {GPIO_PIN_6, EXTI6_IRQn},
47 {GPIO_PIN_7, EXTI7_IRQn},
48 {GPIO_PIN_8, EXTI8_IRQn},
49 {GPIO_PIN_9, EXTI9_IRQn},
50 {GPIO_PIN_10, EXTI10_IRQn},
51 {GPIO_PIN_11, EXTI11_IRQn},
52 {GPIO_PIN_12, EXTI12_IRQn},
53 {GPIO_PIN_13, EXTI13_IRQn},
54 {GPIO_PIN_14, EXTI14_IRQn},
55 {GPIO_PIN_15, EXTI15_IRQn},
56 };
57
58 struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
59 {
60 { -1, 0, RT_NULL, RT_NULL},
61 { -1, 0, RT_NULL, RT_NULL},
62 { -1, 0, RT_NULL, RT_NULL},
63 { -1, 0, RT_NULL, RT_NULL},
64 { -1, 0, RT_NULL, RT_NULL},
65 { -1, 0, RT_NULL, RT_NULL},
66 { -1, 0, RT_NULL, RT_NULL},
67 { -1, 0, RT_NULL, RT_NULL},
68 { -1, 0, RT_NULL, RT_NULL},
69 { -1, 0, RT_NULL, RT_NULL},
70 { -1, 0, RT_NULL, RT_NULL},
71 { -1, 0, RT_NULL, RT_NULL},
72 { -1, 0, RT_NULL, RT_NULL},
73 { -1, 0, RT_NULL, RT_NULL},
74 { -1, 0, RT_NULL, RT_NULL},
75 { -1, 0, RT_NULL, RT_NULL},
76 };
77
78 #ifdef ES_CONF_EXTI_IRQ_0
79
irq_pin0_callback(void * arg)80 rt_weak void irq_pin0_callback(void* arg)
81 {
82 rt_kprintf("\r\nEXTI 0\r\n");
83 }
84 #endif
85
86 #ifdef ES_CONF_EXTI_IRQ_1
87
irq_pin1_callback(void * arg)88 rt_weak void irq_pin1_callback(void* arg)
89 {
90 rt_kprintf("\r\nEXTI 1\r\n");
91 }
92
93 #endif
94
95 #ifdef ES_CONF_EXTI_IRQ_2
96
irq_pin2_callback(void * arg)97 rt_weak void irq_pin2_callback(void* arg)
98 {
99 rt_kprintf("\r\nEXTI 2\r\n");
100 }
101
102 #endif
103
104 #ifdef ES_CONF_EXTI_IRQ_3
105
irq_pin3_callback(void * arg)106 rt_weak void irq_pin3_callback(void* arg)
107 {
108 rt_kprintf("\r\nEXTI 3\r\n");
109 }
110
111 #endif
112
113 #ifdef ES_CONF_EXTI_IRQ_4
114
irq_pin4_callback(void * arg)115 rt_weak void irq_pin4_callback(void* arg)
116 {
117 rt_kprintf("\r\nEXTI 4\r\n");
118 }
119
120 #endif
121
122 #ifdef ES_CONF_EXTI_IRQ_5
123
irq_pin5_callback(void * arg)124 rt_weak void irq_pin5_callback(void* arg)
125 {
126 rt_kprintf("\r\nEXTI 5\r\n");
127 }
128
129 #endif
130
131 #ifdef ES_CONF_EXTI_IRQ_6
132
irq_pin6_callback(void * arg)133 rt_weak void irq_pin6_callback(void* arg)
134 {
135 rt_kprintf("\r\nEXTI 6\r\n");
136 }
137
138 #endif
139
140 #ifdef ES_CONF_EXTI_IRQ_7
141
irq_pin7_callback(void * arg)142 rt_weak void irq_pin7_callback(void* arg)
143 {
144 rt_kprintf("\r\nEXTI 7\r\n");
145 }
146
147 #endif
148
149 #ifdef ES_CONF_EXTI_IRQ_8
150
irq_pin8_callback(void * arg)151 rt_weak void irq_pin8_callback(void* arg)
152 {
153 rt_kprintf("\r\nEXTI 8\r\n");
154 }
155
156 #endif
157
158 #ifdef ES_CONF_EXTI_IRQ_9
159
irq_pin9_callback(void * arg)160 rt_weak void irq_pin9_callback(void* arg)
161 {
162 rt_kprintf("\r\nEXTI 9\r\n");
163 }
164
165 #endif
166
167 #ifdef ES_CONF_EXTI_IRQ_10
168
irq_pin10_callback(void * arg)169 rt_weak void irq_pin10_callback(void* arg)
170 {
171 rt_kprintf("\r\nEXTI 10\r\n");
172 }
173
174 #endif
175
176 #ifdef ES_CONF_EXTI_IRQ_11
177
irq_pin11_callback(void * arg)178 rt_weak void irq_pin11_callback(void* arg)
179 {
180 rt_kprintf("\r\nEXTI 11\r\n");
181 }
182
183 #endif
184
185 #ifdef ES_CONF_EXTI_IRQ_12
186
irq_pin12_callback(void * arg)187 rt_weak void irq_pin12_callback(void* arg)
188 {
189 rt_kprintf("\r\nEXTI 12\r\n");
190 }
191
192 #endif
193
194 #ifdef ES_CONF_EXTI_IRQ_13
195
irq_pin13_callback(void * arg)196 rt_weak void irq_pin13_callback(void* arg)
197 {
198 rt_kprintf("\r\nEXTI 13\r\n");
199 }
200
201 #endif
202
203 #ifdef ES_CONF_EXTI_IRQ_14
204
irq_pin14_callback(void * arg)205 rt_weak void irq_pin14_callback(void* arg)
206 {
207 rt_kprintf("\r\nEXTI 14\r\n");
208 }
209
210 #endif
211
212 #ifdef ES_CONF_EXTI_IRQ_15
213
irq_pin15_callback(void * arg)214 rt_weak void irq_pin15_callback(void* arg)
215 {
216 rt_kprintf("\r\nEXTI 15\r\n");
217 }
218
219 #endif
220
221
222 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
get_pin(uint8_t pin)223 const struct pin_index *get_pin(uint8_t pin)
224 {
225 const struct pin_index *index;
226 if (pin < ITEM_NUM(pins))
227 {
228 index = &pins[pin];
229 if (index->index == -1)
230 index = RT_NULL;
231 }
232 else
233 {
234 index = RT_NULL;
235 }
236 return index;
237 };
238
es32f3_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)239 void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
240 {
241 const struct pin_index *index;
242 index = get_pin(pin);
243 if (index == RT_NULL)
244 {
245 return;
246 }
247 ald_gpio_write_pin(index->gpio, index->pin, value);
248 }
249
es32f3_pin_read(rt_device_t dev,rt_base_t pin)250 rt_ssize_t es32f3_pin_read(rt_device_t dev, rt_base_t pin)
251 {
252 rt_ssize_t value;
253 const struct pin_index *index;
254 value = PIN_LOW;
255 index = get_pin(pin);
256 if (index == RT_NULL)
257 {
258 return -RT_EINVAL;
259 }
260 value = ald_gpio_read_pin(index->gpio, index->pin);
261 return value;
262 }
263
es32f3_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)264 void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
265 {
266 const struct pin_index *index;
267 gpio_init_t gpio_initstruct;
268 index = get_pin(pin);
269 if (index == RT_NULL)
270 {
271 return;
272 }
273
274 /* Configure GPIO_InitStructure */
275 gpio_initstruct.mode = GPIO_MODE_OUTPUT;
276 gpio_initstruct.func = GPIO_FUNC_1;
277 gpio_initstruct.podrv = GPIO_OUT_DRIVE_6;
278 gpio_initstruct.nodrv = GPIO_OUT_DRIVE_6;
279 gpio_initstruct.type = GPIO_TYPE_CMOS;
280 gpio_initstruct.odos = GPIO_PUSH_PULL;
281 gpio_initstruct.flt = GPIO_FILTER_DISABLE;
282
283 if (mode == PIN_MODE_OUTPUT)
284 {
285 /* output setting */
286 gpio_initstruct.mode = GPIO_MODE_OUTPUT;
287 gpio_initstruct.pupd = GPIO_FLOATING;
288 }
289 else if (mode == PIN_MODE_INPUT)
290 {
291 /* input setting: not pull. */
292 gpio_initstruct.mode = GPIO_MODE_INPUT;
293 gpio_initstruct.pupd = GPIO_FLOATING;
294 }
295 else if (mode == PIN_MODE_INPUT_PULLUP)
296 {
297 /* input setting: pull up. */
298 gpio_initstruct.mode = GPIO_MODE_INPUT;
299 gpio_initstruct.pupd = GPIO_PUSH_UP;
300 }
301 else if (mode == PIN_MODE_INPUT_PULLDOWN)
302 {
303 /* input setting: pull down. */
304 gpio_initstruct.mode = GPIO_MODE_INPUT;
305 gpio_initstruct.pupd = GPIO_PUSH_DOWN;
306 }
307 else if (mode == PIN_MODE_OUTPUT_OD)
308 {
309 /* output setting: od. */
310 gpio_initstruct.mode = GPIO_MODE_OUTPUT;
311 gpio_initstruct.pupd = GPIO_FLOATING;
312 gpio_initstruct.odos = GPIO_OPEN_DRAIN;
313 }
314 ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
315 }
316
get_pin_irq_map(rt_uint16_t gpio_pin)317 rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
318 {
319 uint8_t map_index = 0U;
320
321 while(gpio_pin >> (++map_index))
322 {
323 }
324 map_index--;
325
326 if (map_index >= ITEM_NUM(pin_irq_map))
327 {
328 return RT_NULL;
329 }
330 return &pin_irq_map[map_index];
331 };
332
es32f3_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)333 rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin,
334 rt_uint8_t mode, void (*hdr)(void *args), void *args)
335 {
336 const struct pin_index *index;
337 rt_base_t level;
338 rt_int32_t irqindex;
339 index = get_pin(pin);
340 if (index == RT_NULL)
341 {
342 return -RT_ENOSYS;
343 }
344 /* pin no. convert to dec no. */
345 for (irqindex = 0; irqindex < 16; irqindex++)
346 {
347 if ((0x01 << irqindex) == index->pin)
348 {
349 break;
350 }
351 }
352 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
353 {
354 return -RT_ENOSYS;
355 }
356 level = rt_hw_interrupt_disable();
357 if (pin_irq_hdr_tab[irqindex].pin == pin &&
358 pin_irq_hdr_tab[irqindex].hdr == hdr &&
359 pin_irq_hdr_tab[irqindex].mode == mode &&
360 pin_irq_hdr_tab[irqindex].args == args)
361 {
362 rt_hw_interrupt_enable(level);
363 return RT_EOK;
364 }
365 if (pin_irq_hdr_tab[irqindex].pin != -1)
366 {
367 rt_hw_interrupt_enable(level);
368 return -RT_EBUSY;
369 }
370 pin_irq_hdr_tab[irqindex].pin = pin;
371 pin_irq_hdr_tab[irqindex].hdr = hdr;
372 pin_irq_hdr_tab[irqindex].mode = mode;
373 pin_irq_hdr_tab[irqindex].args = args;
374 rt_hw_interrupt_enable(level);
375 return RT_EOK;
376 }
377
es32f3_pin_detach_irq(struct rt_device * device,rt_base_t pin)378 rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_base_t pin)
379 {
380 const struct pin_index *index;
381 rt_base_t level;
382 rt_int32_t irqindex = -1;
383 index = get_pin(pin);
384 if (index == RT_NULL)
385 {
386 return -RT_ENOSYS;
387 }
388
389 for (irqindex = 0; irqindex < 16; irqindex++)
390 {
391 if ((0x01 << irqindex) == index->pin)
392 {
393 break;
394 }
395 }
396 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
397 {
398 return -RT_ENOSYS;
399 }
400 level = rt_hw_interrupt_disable();
401 if (pin_irq_hdr_tab[irqindex].pin == -1)
402 {
403 rt_hw_interrupt_enable(level);
404 return RT_EOK;
405 }
406 pin_irq_hdr_tab[irqindex].pin = -1;
407 pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
408 pin_irq_hdr_tab[irqindex].mode = 0;
409 pin_irq_hdr_tab[irqindex].args = RT_NULL;
410 rt_hw_interrupt_enable(level);
411 return RT_EOK;
412 }
413
es32f3_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)414 rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin,
415 rt_uint8_t enabled)
416 {
417 const struct pin_index *index;
418 const struct pin_irq_map *irqmap;
419 rt_base_t level;
420 rt_int32_t irqindex = -1;
421 /* Configure GPIO_InitStructure & EXTI_InitStructure */
422 gpio_init_t gpio_initstruct;
423 exti_init_t exti_initstruct;
424 exti_initstruct.filter = DISABLE;
425 exti_initstruct.cks = EXTI_FILTER_CLOCK_10K;
426 exti_initstruct.filter_time = 0x0;
427
428 index = get_pin(pin);
429 if (index == RT_NULL)
430 {
431 return -RT_ENOSYS;
432 }
433 if (enabled == PIN_IRQ_ENABLE)
434 {
435 /* pin no. convert to dec no. */
436 for (irqindex = 0; irqindex < 16; irqindex++)
437 {
438 if ((0x01 << irqindex) == index->pin)
439 {
440 break;
441 }
442 }
443 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
444 {
445 return -RT_ENOSYS;
446 }
447 level = rt_hw_interrupt_disable();
448 if (pin_irq_hdr_tab[irqindex].pin == -1)
449 {
450 rt_hw_interrupt_enable(level);
451 return -RT_ENOSYS;
452 }
453 irqmap = &pin_irq_map[irqindex];
454 ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
455 /* Configure GPIO_InitStructure */
456 gpio_initstruct.mode = GPIO_MODE_INPUT;
457 gpio_initstruct.odos = GPIO_PUSH_PULL;
458 gpio_initstruct.podrv = GPIO_OUT_DRIVE_6;
459 gpio_initstruct.nodrv = GPIO_OUT_DRIVE_6;
460 gpio_initstruct.func = GPIO_FUNC_1;
461 gpio_initstruct.flt = GPIO_FILTER_DISABLE;
462 switch (pin_irq_hdr_tab[irqindex].mode)
463 {
464 case PIN_IRQ_MODE_RISING:
465 gpio_initstruct.pupd = GPIO_PUSH_DOWN;
466 ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
467 break;
468 case PIN_IRQ_MODE_FALLING:
469 gpio_initstruct.pupd = GPIO_PUSH_UP;
470 ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
471 break;
472 case PIN_IRQ_MODE_RISING_FALLING:
473 gpio_initstruct.pupd = GPIO_FLOATING;
474 ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
475 break;
476 }
477 ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
478 NVIC_EnableIRQ(irqmap->irqno);
479 rt_hw_interrupt_enable(level);
480 }
481 else if (enabled == PIN_IRQ_DISABLE)
482 {
483 irqmap = get_pin_irq_map(index->pin);
484 if (irqmap == RT_NULL)
485 {
486 return -RT_ENOSYS;
487 }
488 NVIC_DisableIRQ(irqmap->irqno);
489 }
490 else
491 {
492 return -RT_ENOSYS;
493 }
494 return RT_EOK;
495 }
496
497 const static struct rt_pin_ops _es32f3_pin_ops =
498 {
499 es32f3_pin_mode,
500 es32f3_pin_write,
501 es32f3_pin_read,
502 es32f3_pin_attach_irq,
503 es32f3_pin_detach_irq,
504 es32f3_pin_irq_enable,
505 /*RT_NULL,*/
506 };
507
pin_irq_hdr(uint16_t GPIO_Pin)508 rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
509 {
510 uint16_t irqno;
511 /* pin no. convert to dec no. */
512 for (irqno = 0; irqno < 16; irqno++)
513 {
514 if ((0x01 << irqno) == GPIO_Pin)
515 {
516 break;
517 }
518 }
519 if (irqno == 16)
520 return;
521 if (pin_irq_hdr_tab[irqno].hdr)
522 {
523 pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
524 }
525 }
526
GPIO_EXTI_Callback(uint16_t GPIO_Pin)527 void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
528 {
529 if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
530 {
531 ald_gpio_exti_clear_flag_status(GPIO_Pin);
532 pin_irq_hdr(GPIO_Pin);
533 }
534 }
535
EXTI0_Handler(void)536 void EXTI0_Handler(void)
537 {
538 rt_interrupt_enter();
539 GPIO_EXTI_Callback(GPIO_PIN_0);
540 rt_interrupt_leave();
541 }
542
EXTI1_Handler(void)543 void EXTI1_Handler(void)
544 {
545 rt_interrupt_enter();
546 GPIO_EXTI_Callback(GPIO_PIN_1);
547 rt_interrupt_leave();
548 }
549
EXTI2_Handler(void)550 void EXTI2_Handler(void)
551 {
552 rt_interrupt_enter();
553 GPIO_EXTI_Callback(GPIO_PIN_2);
554 rt_interrupt_leave();
555 }
556
EXTI3_Handler(void)557 void EXTI3_Handler(void)
558 {
559 rt_interrupt_enter();
560 GPIO_EXTI_Callback(GPIO_PIN_3);
561 rt_interrupt_leave();
562 }
563
EXTI4_Handler(void)564 void EXTI4_Handler(void)
565 {
566 rt_interrupt_enter();
567 GPIO_EXTI_Callback(GPIO_PIN_4);
568 rt_interrupt_leave();
569 }
570
EXTI5_Handler(void)571 void EXTI5_Handler(void)
572 {
573 rt_interrupt_enter();
574 GPIO_EXTI_Callback(GPIO_PIN_5);
575 rt_interrupt_leave();
576 }
577
EXTI6_Handler(void)578 void EXTI6_Handler(void)
579 {
580 rt_interrupt_enter();
581 GPIO_EXTI_Callback(GPIO_PIN_6);
582 rt_interrupt_leave();
583 }
584
EXTI7_Handler(void)585 void EXTI7_Handler(void)
586 {
587 rt_interrupt_enter();
588 GPIO_EXTI_Callback(GPIO_PIN_7);
589 rt_interrupt_leave();
590 }
591
EXTI8_Handler(void)592 void EXTI8_Handler(void)
593 {
594 rt_interrupt_enter();
595 GPIO_EXTI_Callback(GPIO_PIN_8);
596 rt_interrupt_leave();
597 }
598
EXTI9_Handler(void)599 void EXTI9_Handler(void)
600 {
601 rt_interrupt_enter();
602 GPIO_EXTI_Callback(GPIO_PIN_9);
603 rt_interrupt_leave();
604 }
605
EXTI10_Handler(void)606 void EXTI10_Handler(void)
607 {
608 rt_interrupt_enter();
609 GPIO_EXTI_Callback(GPIO_PIN_10);
610 rt_interrupt_leave();
611 }
612
EXTI11_Handler(void)613 void EXTI11_Handler(void)
614 {
615 rt_interrupt_enter();
616 GPIO_EXTI_Callback(GPIO_PIN_11);
617 rt_interrupt_leave();
618 }
619
EXTI12_Handler(void)620 void EXTI12_Handler(void)
621 {
622 rt_interrupt_enter();
623 GPIO_EXTI_Callback(GPIO_PIN_12);
624 rt_interrupt_leave();
625 }
626
EXTI13_Handler(void)627 void EXTI13_Handler(void)
628 {
629 rt_interrupt_enter();
630 GPIO_EXTI_Callback(GPIO_PIN_13);
631 rt_interrupt_leave();
632 }
633
EXTI14_Handler(void)634 void EXTI14_Handler(void)
635 {
636 rt_interrupt_enter();
637 GPIO_EXTI_Callback(GPIO_PIN_14);
638 rt_interrupt_leave();
639 }
640
EXTI15_Handler(void)641 void EXTI15_Handler(void)
642 {
643 rt_interrupt_enter();
644 GPIO_EXTI_Callback(GPIO_PIN_15);
645 rt_interrupt_leave();
646 }
647
rt_hw_pin_init(void)648 int rt_hw_pin_init(void)
649 {
650 int result;
651
652
653 #ifdef ES_INIT_GPIOS
654
655 rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t);
656
657 #endif
658
659 ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
660
661 result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f3_pin_ops, RT_NULL);
662
663 if(result != RT_EOK)return result;
664
665 #ifdef ES_INIT_GPIOS
666
667 for(i = 0;i < gpio_conf_num;i++)
668 {
669 rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode);
670
671 if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD))
672 rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level);
673
674 if(!gpio_conf_all[i].irq_en)continue;
675
676 rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL);
677 rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en);
678 }
679
680 #endif
681
682
683
684 return result;
685 }
686 INIT_BOARD_EXPORT(rt_hw_pin_init);
687
688 #endif
689