1 /*
2  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  *
18  * Change Logs:
19  * Date           Author       Notes
20  * 2019-3-19      wangyq       the first version
21  * 2019-11-01     wangyq        update libraries
22  * 2021-04-20     liuhy         the second version
23  */
24 
25 #include <rthw.h>
26 #include <rtthread.h>
27 #include <rtdevice.h>
28 #include <drv_hwtimer.h>
29 #include <board.h>
30 
31 
32 #ifdef RT_USING_HWTIMER
33 
34 struct es32f3_hwtimer_dev
35 {
36     rt_hwtimer_t parent;
37     timer_handle_t *hwtimer_periph;
38     IRQn_Type IRQn;
39 };
40 
41 #ifdef BSP_USING_AD16C4T0_HWTIMER
42 static struct es32f3_hwtimer_dev ad16c4t0_hwtimer;
43 
44 static struct rt_hwtimer_info ad16c4t0_info =
45 {
46     ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
47     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
48     0xFFFF,    /* counter maximum value */
49     ES_AD16C4T0_HWTIMER_MODE
50 };
51 
AD16C4T0_UP_Handler(void)52 void AD16C4T0_UP_Handler(void)
53 {
54     ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
55     rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent);
56 }
57 
58 #endif
59 
60 #ifdef BSP_USING_AD16C4T1_HWTIMER
61 
62 static struct es32f3_hwtimer_dev ad16c4t1_hwtimer;
63 
64 static struct rt_hwtimer_info ad16c4t1_info =
65 {
66     ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
67     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
68     0xFFFF,    /* counter maximum value */
69     ES_AD16C4T1_HWTIMER_MODE
70 };
71 
AD16C4T1_UP_Handler(void)72 void AD16C4T1_UP_Handler(void)
73 {
74     ald_timer_clear_flag_status(ad16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
75     rt_device_hwtimer_isr(&ad16c4t1_hwtimer.parent);
76 }
77 
78 #endif
79 #ifdef BSP_USING_GP32C4T0_HWTIMER
80 
81 static struct es32f3_hwtimer_dev gp32c4t0_hwtimer;
82 
83 static struct rt_hwtimer_info gp32c4t0_info =
84 {
85 
86     ES_SYS_CLK >> ES_CMU_PCLK_1_DIV , /* maximum count frequency */
87     ( ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16),        /* minimum count frequency */
88     0xFFFFFFFF,    /* counter maximum value */
89     ES_GP32C4T0_HWTIMER_MODE
90 };
91 
GP32C4T0_Handler(void)92 void GP32C4T0_Handler(void)
93 {
94     ald_timer_clear_flag_status(gp32c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
95     rt_device_hwtimer_isr(&gp32c4t0_hwtimer.parent);
96 }
97 
98 #endif
99 #ifdef BSP_USING_GP32C4T1_HWTIMER
100 
101 static struct es32f3_hwtimer_dev gp32c4t1_hwtimer;
102 
103 static struct rt_hwtimer_info gp32c4t1_info =
104 {
105     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV ), /* maximum count frequency */
106     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16),        /* minimum count frequency */
107     0xFFFFFFFF,    /* counter maximum value */
108     ES_GP32C4T1_HWTIMER_MODE
109 };
110 
GP32C4T1_Handler(void)111 void GP32C4T1_Handler(void)
112 {
113     ald_timer_clear_flag_status(gp32c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
114     rt_device_hwtimer_isr(&gp32c4t1_hwtimer.parent);
115 }
116 
117 #endif
118 #ifdef BSP_USING_GP16C4T0_HWTIMER
119 
120 static struct es32f3_hwtimer_dev gp16c4t0_hwtimer;
121 
122 static struct rt_hwtimer_info gp16c4t0_info =
123 {
124     ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
125     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
126     0xFFFF,    /* counter maximum value */
127     ES_GP16C4T0_HWTIMER_MODE
128 };
129 
GP16C4T0_Handler(void)130 void GP16C4T0_Handler(void)
131 {
132     ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
133     rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent);
134 }
135 
136 #endif
137 #ifdef BSP_USING_GP16C4T1_HWTIMER
138 
139 static struct es32f3_hwtimer_dev gp16c4t1_hwtimer;
140 
141 static struct rt_hwtimer_info gp16c4t1_info =
142 {
143     ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
144     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
145     0xFFFF,    /* counter maximum value */
146     ES_GP16C4T1_HWTIMER_MODE
147 };
148 
GP16C4T1_Handler(void)149 void GP16C4T1_Handler(void)
150 {
151     ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
152     rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent);
153 }
154 
155 #endif
156 #ifdef BSP_USING_BS16T0_HWTIMER
157 
158 static struct es32f3_hwtimer_dev bs16t0_hwtimer;
159 
160 static struct rt_hwtimer_info bs16t0_info =
161 {
162     ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
163     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
164     0xFFFF,    /* counter maximum value */
165     ES_BS16T0_HWTIMER_MODE
166 };
167 
BS16T0_Handler(void)168 void BS16T0_Handler(void)
169 {
170     ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
171     rt_device_hwtimer_isr(&bs16t0_hwtimer.parent);
172 }
173 
174 #endif
175 #ifdef BSP_USING_BS16T1_HWTIMER
176 
177 static struct es32f3_hwtimer_dev bs16t1_hwtimer;
178 
179 static struct rt_hwtimer_info bs16t1_info =
180 {
181     ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
182     (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
183     0xFFFF,    /* counter maximum value */
184     ES_BS16T1_HWTIMER_MODE
185 };
186 
BS16T1_Handler(void)187 void BS16T1_Handler(void)
188 {
189     ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
190     rt_device_hwtimer_isr(&bs16t1_hwtimer.parent);
191 }
192 
193 #endif
194 
es32f3_hwtimer_init(rt_hwtimer_t * timer,rt_uint32_t state)195 static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
196 {
197     struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
198 
199     struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info;
200 
201 
202     RT_ASSERT(hwtimer != RT_NULL);
203 
204     if (1 == state)
205     {
206         ald_timer_base_init(hwtimer->hwtimer_periph);
207         ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
208         NVIC_EnableIRQ(hwtimer->IRQn);
209     }
210 
211     hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
212     hwtimer_info->maxfreq = hwtimer->parent.freq;
213     hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF;
214 
215 }
216 
es32f3_hwtimer_start(rt_hwtimer_t * timer,rt_uint32_t cnt,rt_hwtimer_mode_t mode)217 static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer,
218                                      rt_uint32_t cnt,
219                                      rt_hwtimer_mode_t mode)
220 {
221     struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
222 
223     RT_ASSERT(hwtimer != RT_NULL);
224 
225     WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
226     ald_timer_base_start(hwtimer->hwtimer_periph);
227 
228     return RT_EOK;
229 }
230 
es32f3_hwtimer_stop(rt_hwtimer_t * timer)231 static void es32f3_hwtimer_stop(rt_hwtimer_t *timer)
232 {
233     struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
234 
235     RT_ASSERT(hwtimer != RT_NULL);
236 
237     ald_timer_base_stop(hwtimer->hwtimer_periph);
238 }
239 
es32f3_hwtimer_count_get(rt_hwtimer_t * timer)240 static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer)
241 {
242     struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
243     uint32_t hwtimer_count = 0;
244 
245     RT_ASSERT(hwtimer != RT_NULL);
246 
247     hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT);
248 
249     return hwtimer_count;
250 }
251 
es32f3_hwtimer_control(rt_hwtimer_t * timer,rt_uint32_t cmd,void * args)252 static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer,
253                                        rt_uint32_t cmd,
254                                        void *args)
255 {
256     rt_err_t ret = RT_EOK;
257     rt_uint32_t freq = 0;
258     struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
259 
260     RT_ASSERT(hwtimer != RT_NULL);
261 
262     switch (cmd)
263     {
264     case HWTIMER_CTRL_FREQ_SET:
265         freq = *(rt_uint32_t *)args;
266 
267         ret = -RT_ERROR;
268 
269         if(freq)
270         {
271             double temp,target;
272             temp = (double)ald_cmu_get_pclk1_clock();
273             target = temp/freq;
274 
275             if(target < 0x10001)   /*最大分频 = max(PRES)+1*/
276             {
277                 temp = target - (int)(target);
278 
279                 if((temp > 0.998)&&(target < 0x10000))
280                 {
281                     hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target;
282                     ret = RT_EOK;
283                 }
284                 if((temp < 0.002)&&(target >= 0x1))
285                 {
286                     hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1;
287                     ret = RT_EOK;
288                 }
289 
290             }
291 
292             if(ret == RT_EOK)     /*更新信息*/
293                 hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
294 
295         }
296 
297         break;
298 
299     case HWTIMER_CTRL_STOP:
300         ald_timer_base_stop(hwtimer->hwtimer_periph);
301         break;
302 
303     default:
304         ret = -RT_EINVAL;
305         break;
306     }
307 
308     return ret;
309 }
310 
311 static struct rt_hwtimer_ops es32f3_hwtimer_ops =
312 {
313     es32f3_hwtimer_init,
314     es32f3_hwtimer_start,
315     es32f3_hwtimer_stop,
316     es32f3_hwtimer_count_get,
317     es32f3_hwtimer_control
318 };
319 
rt_hw_hwtimer_init(void)320 int rt_hw_hwtimer_init(void)
321 {
322     rt_err_t ret = RT_EOK;
323 
324 #ifdef BSP_USING_AD16C4T0_HWTIMER
325     static timer_handle_t ad16c4t0_hwtimer_periph;
326 
327     ad16c4t0_hwtimer_periph.perh = AD16C4T0;
328     ad16c4t0_hwtimer.IRQn = AD16C4T0_UP_IRQn;
329 
330     ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1;
331     ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
332     ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph;
333 
334     ad16c4t0_hwtimer.parent.info = &ad16c4t0_info;
335     ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
336     ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer);
337 #endif
338 
339 #ifdef BSP_USING_AD16C4T1_HWTIMER
340     static timer_handle_t ad16c4t1_hwtimer_periph;
341 
342     ad16c4t1_hwtimer_periph.perh = AD16C4T1;
343     ad16c4t1_hwtimer.IRQn = AD16C4T1_UP_IRQn;
344 
345     ad16c4t1_hwtimer_periph.init.prescaler = ES_AD16C4T1_HWTIMER_PRES - 1;
346     ad16c4t1_hwtimer_periph.init.mode = ( ES_AD16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
347     ad16c4t1_hwtimer.hwtimer_periph = &ad16c4t1_hwtimer_periph;
348 
349     ad16c4t1_hwtimer.parent.info = &ad16c4t1_info;
350     ad16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops;
351     ret = rt_device_hwtimer_register(&ad16c4t1_hwtimer.parent, ES_DEVICE_NAME_AD16C4T1_HWTIMER, &ad16c4t1_hwtimer);
352 #endif
353 
354 #ifdef BSP_USING_GP32C4T0_HWTIMER
355     static timer_handle_t gp32c4t0_hwtimer_periph;
356 
357     gp32c4t0_hwtimer_periph.perh = GP32C4T0;
358     gp32c4t0_hwtimer.IRQn = GP32C4T0_IRQn;
359 
360     gp32c4t0_hwtimer_periph.init.prescaler = ES_GP32C4T0_HWTIMER_PRES - 1;
361     gp32c4t0_hwtimer_periph.init.mode = ( ES_GP32C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
362     gp32c4t0_hwtimer.hwtimer_periph = &gp32c4t0_hwtimer_periph;
363 
364     gp32c4t0_hwtimer.parent.info = &gp32c4t0_info;
365     gp32c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
366     ret = rt_device_hwtimer_register(&gp32c4t0_hwtimer.parent, ES_DEVICE_NAME_GP32C4T0_HWTIMER, &gp32c4t0_hwtimer);
367 #endif
368 
369 #ifdef BSP_USING_GP32C4T1_HWTIMER
370     static timer_handle_t gp32c4t1_hwtimer_periph;
371 
372     gp32c4t1_hwtimer_periph.perh = GP32C4T1;
373     gp32c4t1_hwtimer.IRQn = GP32C4T1_IRQn;
374 
375     gp32c4t1_hwtimer_periph.init.prescaler = ES_GP32C4T1_HWTIMER_PRES - 1;
376     gp32c4t1_hwtimer_periph.init.mode = ( ES_GP32C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
377     gp32c4t1_hwtimer.hwtimer_periph = &gp32c4t1_hwtimer_periph;
378 
379     gp32c4t1_hwtimer.parent.info = &gp32c4t1_info;
380     gp32c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops;
381     ret = rt_device_hwtimer_register(&gp32c4t1_hwtimer.parent, ES_DEVICE_NAME_GP32C4T1_HWTIMER, &gp32c4t1_hwtimer);
382 #endif
383 
384 #ifdef BSP_USING_GP16C4T0_HWTIMER
385     static timer_handle_t gp16c4t0_hwtimer_periph;
386 
387     gp16c4t0_hwtimer_periph.perh = GP16C4T0;
388     gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn;
389 
390     gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1;
391     gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
392     gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph;
393 
394     gp16c4t0_hwtimer.parent.info = &gp16c4t0_info;
395     gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
396     ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer);
397 #endif
398 
399 #ifdef BSP_USING_GP16C4T1_HWTIMER
400     static timer_handle_t gp16c4t1_hwtimer_periph;
401 
402     gp16c4t1_hwtimer_periph.perh = GP16C4T1;
403     gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn;
404 
405     gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1;
406     gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
407     gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph;
408 
409     gp16c4t1_hwtimer.parent.info = &gp16c4t1_info;
410     gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops;
411     ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer);
412 #endif
413 
414 #ifdef BSP_USING_BS16T0_HWTIMER
415     static timer_handle_t bs16t0_hwtimer_periph;
416 
417     bs16t0_hwtimer_periph.perh = BS16T0;
418     bs16t0_hwtimer.IRQn = BS16T0_IRQn;
419 
420     bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1;
421     bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
422     bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph;
423 
424     bs16t0_hwtimer.parent.info = &bs16t0_info;
425     bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
426     ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer);
427 #endif
428 
429 #ifdef BSP_USING_BS16T1_HWTIMER
430     static timer_handle_t bs16t1_hwtimer_periph;
431 
432     bs16t1_hwtimer_periph.perh = BS16T1;
433     bs16t1_hwtimer.IRQn = BS16T1_IRQn;
434 
435     bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1;
436     bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
437     bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph;
438 
439     bs16t1_hwtimer.parent.info = &bs16t1_info;
440     bs16t1_hwtimer.parent.ops = &es32f3_hwtimer_ops;
441     ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer);
442 #endif
443 
444     return ret;
445 }
446 INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
447 
448 #endif
449