1 /** 2 ********************************************************************************* 3 * 4 * @file ald_cmu.h 5 * @brief Header file of CMU module driver. 6 * 7 * @version V1.0 8 * @date 22 Nov 2019 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 22 Nov 2019 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_CMU_H__ 34 #define __ALD_CMU_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include "utils.h" 41 #include "ald_syscfg.h" 42 43 44 /** @addtogroup ES32FXXX_ALD 45 * @{ 46 */ 47 48 /** @addtogroup CMU 49 * @{ 50 */ 51 52 /** @defgroup CMU_Public_Macros CMU Public Macros 53 * @{ 54 */ 55 #define CMU_HRC_SEL_BY_SW() \ 56 do { \ 57 SYSCFG_UNLOCK(); \ 58 SET_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \ 59 SYSCFG_LOCK(); \ 60 } while (0) 61 #define CMU_HRC_SEL_BY_CFGW() \ 62 do { \ 63 SYSCFG_UNLOCK(); \ 64 CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \ 65 SYSCFG_LOCK(); \ 66 } while (0) 67 #define CMU_HRC_DIV_1MHZ_ENABLE() \ 68 do { \ 69 SYSCFG_UNLOCK(); \ 70 SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \ 71 SYSCFG_LOCK(); \ 72 } while (0) 73 #define CMU_HRC_DIV_1MHZ_DISABLE() \ 74 do { \ 75 SYSCFG_UNLOCK(); \ 76 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \ 77 SYSCFG_LOCK(); \ 78 } while (0) 79 #define CMU_HOSC_DIV_1MHZ_ENABLE() \ 80 do { \ 81 SYSCFG_UNLOCK(); \ 82 SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK); \ 83 SYSCFG_LOCK(); \ 84 } while (0) 85 #define CMU_HOSC_DIV_1MHZ_DISABLE() \ 86 do { \ 87 SYSCFG_UNLOCK(); \ 88 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK);\ 89 SYSCFG_LOCK(); \ 90 } while (0) 91 #define CMU_LOSC_ENABLE() \ 92 do { \ 93 SYSCFG_UNLOCK(); \ 94 SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ 95 SYSCFG_LOCK(); \ 96 } while (0) 97 #define CMU_LOSC_DISABLE() \ 98 do { \ 99 SYSCFG_UNLOCK(); \ 100 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ 101 SYSCFG_LOCK(); \ 102 } while (0) 103 #define CMU_LRC_ENABLE() \ 104 do { \ 105 SYSCFG_UNLOCK(); \ 106 SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ 107 SYSCFG_LOCK(); \ 108 } while (0) 109 #define CMU_LRC_DISABLE() \ 110 do { \ 111 SYSCFG_UNLOCK(); \ 112 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ 113 SYSCFG_LOCK(); \ 114 } while (0) 115 #define CMU_ULRC_ENABLE() \ 116 do { \ 117 SYSCFG_UNLOCK(); \ 118 SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ 119 SYSCFG_LOCK(); \ 120 } while (0) 121 #define CMU_ULRC_DISABLE() \ 122 do { \ 123 SYSCFG_UNLOCK(); \ 124 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ 125 SYSCFG_LOCK(); \ 126 } while (0) 127 128 /* Low power mode control */ 129 #define CMU_LP_LRC_ENABLE() \ 130 do { \ 131 SYSCFG_UNLOCK(); \ 132 SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ 133 SYSCFG_LOCK(); \ 134 } while (0) 135 #define CMU_LP_LRC_DISABLE() \ 136 do { \ 137 SYSCFG_UNLOCK(); \ 138 CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ 139 SYSCFG_LOCK(); \ 140 } while (0) 141 #define CMU_LP_LOSC_ENABLE() \ 142 do { \ 143 SYSCFG_UNLOCK(); \ 144 SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ 145 SYSCFG_LOCK(); \ 146 } while (0) 147 #define CMU_LP_LOSC_DISABLE() \ 148 do { \ 149 SYSCFG_UNLOCK(); \ 150 CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ 151 SYSCFG_LOCK(); \ 152 } while (0) 153 #define CMU_LP_HRC_ENABLE() \ 154 do { \ 155 SYSCFG_UNLOCK(); \ 156 SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ 157 SYSCFG_LOCK(); \ 158 } while (0) 159 #define CMU_LP_HRC_DISABLE() \ 160 do { \ 161 SYSCFG_UNLOCK(); \ 162 CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ 163 SYSCFG_LOCK(); \ 164 } while (0) 165 #define CMU_LP_HOSC_ENABLE() \ 166 do { \ 167 SYSCFG_UNLOCK(); \ 168 SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ 169 SYSCFG_LOCK(); \ 170 } while (0) 171 #define CMU_LP_HOSC_DISABLE() \ 172 do { \ 173 SYSCFG_UNLOCK(); \ 174 CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ 175 SYSCFG_LOCK(); \ 176 } while (0) 177 /** 178 * @} 179 */ 180 181 182 /** @defgroup CMU_Public_Types CMU Public Types 183 * @{ 184 */ 185 /** 186 * @brief CMU state structure definition 187 */ 188 typedef enum { 189 CMU_CLOCK_HRC = 0x1U, /**< HRC */ 190 CMU_CLOCK_LRC = 0x2U, /**< LRC */ 191 CMU_CLOCK_LOSC = 0x3U, /**< LOSC */ 192 CMU_CLOCK_PLL1 = 0x4U, /**< PLL1 */ 193 CMU_CLOCK_HOSC = 0x5U, /**< HOSC */ 194 } cmu_clock_t; 195 196 /** 197 * @brief PLL1 output clock 198 */ 199 typedef enum { 200 CMU_PLL1_OUTPUT_36M = 0x0U, /**< x9 (36MHz) */ 201 CMU_PLL1_OUTPUT_48M = 0x1U, /**< x12 (48MHz) */ 202 #if defined(ES32F36xx) || defined(ES32F39xx) 203 CMU_PLL1_OUTPUT_72M = 0x2U, /**< x18 (72MHz) */ 204 CMU_PLL1_OUTPUT_96M = 0x3U, /**< x24 (96MHz) */ 205 #endif 206 } cmu_pll1_output_t; 207 208 /** 209 * @brief PLL1 referance clock 210 */ 211 typedef enum { 212 CMU_PLL1_INPUT_HRC_6 = 0x0U, /**< HRC / 6 */ 213 CMU_PLL1_INPUT_PLL2 = 0x1U, /**< PLL2 */ 214 CMU_PLL1_INPUT_HOSC = 0x2U, /**< HOSC / 1 */ 215 CMU_PLL1_INPUT_HOSC_2 = 0x3U, /**< HOSC / 2 */ 216 CMU_PLL1_INPUT_HOSC_3 = 0x4U, /**< HOSC / 3 */ 217 CMU_PLL1_INPUT_HOSC_4 = 0x5U, /**< HOSC / 4 */ 218 CMU_PLL1_INPUT_HOSC_5 = 0x6U, /**< HOSC / 5 */ 219 CMU_PLL1_INPUT_HOSC_6 = 0x7U, /**< HOSC / 6 */ 220 } cmu_pll1_input_t; 221 222 /** 223 * @brief HOSC range 224 */ 225 typedef enum { 226 CMU_HOSC_2M = 0x0U, /**< 0~2MHz */ 227 CMU_HOSC_4M = 0x1U, /**< 2~4MHz */ 228 CMU_HOSC_8M = 0x2U, /**< 4~8MHz */ 229 CMU_HOSC_16M = 0x3U, /**< 8~16MHz */ 230 CMU_HOSC_24M = 0x4U, /**< 16~24MHz */ 231 } cmu_hosc_range_t; 232 233 /** 234 * @brief Safe clock source type 235 */ 236 typedef enum { 237 CMU_SAFE_CLK_HOSC = 0x0U, /**< HOSC */ 238 CMU_SAFE_CLK_LOSC = 0x1U, /**< LOSC */ 239 CMU_SAFE_CLK_PLL = 0x2U, /**< PLL */ 240 } cmu_clock_safe_type_t; 241 242 /** 243 * @brief Frequency division select bit 244 */ 245 typedef enum { 246 CMU_DIV_1 = 0x0U, /**< Division by 1 */ 247 CMU_DIV_2 = 0x1U, /**< Division by 2 */ 248 CMU_DIV_4 = 0x2U, /**< Division by 4 */ 249 CMU_DIV_8 = 0x3U, /**< Division by 8 */ 250 CMU_DIV_16 = 0x4U, /**< Division by 16 */ 251 CMU_DIV_32 = 0x5U, /**< Division by 32 */ 252 CMU_DIV_64 = 0x6U, /**< Division by 64 */ 253 CMU_DIV_128 = 0x7U, /**< Division by 128 */ 254 CMU_DIV_256 = 0x8U, /**< Division by 256 */ 255 CMU_DIV_512 = 0x9U, /**< Division by 512 */ 256 CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ 257 CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ 258 CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ 259 } cmu_div_t; 260 261 /** 262 * @brief Bus type 263 */ 264 typedef enum { 265 CMU_HCLK_1 = 0x0U, /**< AHB1 bus */ 266 CMU_HCLK_2 = 0x1U, /**< AHB2 bus */ 267 CMU_SYS = 0x2U, /**< SYS bus */ 268 CMU_PCLK_1 = 0x3U, /**< APB1 bus */ 269 CMU_PCLK_2 = 0x4U, /**< APB2 bus */ 270 } cmu_bus_t; 271 272 /** 273 * @brief Output high clock select 274 */ 275 typedef enum { 276 CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ 277 CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, /**< Select LOSC */ 278 CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, /**< Select HRC */ 279 CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ 280 CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, /**< Select HOSM */ 281 CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, /**< Select PLL1 */ 282 CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, /**< Select PLL2 */ 283 CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U, /**< Select SYSCLK */ 284 } cmu_output_high_sel_t; 285 286 /** 287 * @brief Output frequency division 288 */ 289 typedef enum { 290 CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ 291 CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ 292 CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ 293 CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ 294 CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ 295 CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ 296 CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ 297 CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ 298 } cmu_output_high_div_t; 299 300 /** 301 * @brief Output low clock select 302 */ 303 typedef enum { 304 CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, /**< Select LOSC */ 305 CMU_OUTPUT_LOW_SEL_LRC = 0x1U, /**< Select LRC */ 306 CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, /**< Select LOSM */ 307 CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U, /**< Select BUZZ */ 308 CMU_OUTPUT_LOW_SEL_ULRC = 0x4U, /**< Select ULRC */ 309 } cmu_output_low_sel_t; 310 311 /** 312 * @brief BUZZ frequency division 313 */ 314 typedef enum { 315 CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ 316 CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ 317 CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ 318 CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ 319 CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ 320 CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ 321 CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ 322 CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ 323 } cmu_buzz_div_t; 324 325 /** 326 * @brief Low power peripheral clock select 327 */ 328 typedef enum { 329 CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, /**< Select PCLK2 */ 330 CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, /**< Select PLL1 */ 331 CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, /**< Select PLL2 */ 332 CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U, /**< Select HRC */ 333 CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, /**< Select HOSC */ 334 CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, /**< Select LRC */ 335 CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, /**< Select LOSC */ 336 CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U, /**< Select ULRC */ 337 CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, /**< Select HRC down to 1MHz */ 338 CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, /**< Select HOSC down to 1MHz */ 339 CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, /**< Select LOSM */ 340 CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU, /**< Select HOSM */ 341 } cmu_lp_perh_clock_sel_t; 342 343 /** 344 * @brief LCD clock select 345 */ 346 typedef enum { 347 CMU_LCD_SEL_LOSM = 0x0U, /**< Select LOSM */ 348 CMU_LCD_SEL_LOSC = 0x1U, /**< Select LOSC */ 349 CMU_LCD_SEL_LRC = 0x2U, /**< Select LRC */ 350 CMU_LCD_SEL_ULRC = 0x3U, /**< Select ULRC */ 351 CMU_LCD_SEL_HRC_1M = 0x4U, /**< Select HRC down to 1MHz */ 352 CMU_LCD_SEL_HOSC_1M = 0x5U, /**< Select HOSC down to 1MHz */ 353 } cmu_lcd_clock_sel_t; 354 355 /** 356 * @brief QSPI clock select 357 */ 358 typedef enum { 359 CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U, /**< Select PCLK1 */ 360 CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U, /**< Select HCLK2 */ 361 CMU_QSPI_CLOCK_SEL_HRC = 0x2U, /**< Select HRC */ 362 CMU_QSPI_CLOCK_SEL_HOSC = 0x3U, /**< Select HOSC */ 363 CMU_QSPI_CLOCK_SEL_PLL1 = 0x4U, /**< Select PLL1 */ 364 CMU_QSPI_CLOCK_SEL_HOSM = 0x5U, /**< Select HOSC security management */ 365 } cmu_qspi_clock_sel_t; 366 367 /** 368 * @brief USB clock select 369 */ 370 typedef enum { 371 CMU_USB_CLOCK_SEL_HOSC = 0x0U, /**< Select HOSC */ 372 CMU_USB_CLOCK_SEL_HRC = 0x1U, /**< Select HRC */ 373 CMU_USB_CLOCK_SEL_PCLK1 = 0x2U, /**< Select PCLK1 */ 374 CMU_USB_CLOCK_SEL_PLL1 = 0x3U, /**< Select PLL1 */ 375 CMU_USB_CLOCK_SEL_HOSM = 0x4U, /**< Select HOSC security management */ 376 } cmu_usb_clock_sel_t; 377 378 /** 379 * @brief USB clock division 380 */ 381 typedef enum { 382 CMU_USB_DIV_1 = 0x0U, /**< Division by 1 */ 383 CMU_USB_DIV_2 = 0x1U, /**< Division by 2 */ 384 CMU_USB_DIV_4 = 0x2U, /**< Division by 4 */ 385 CMU_USB_DIV_8 = 0x3U, /**< Division by 8 */ 386 CMU_USB_DIV_16 = 0x4U, /**< Division by 16 */ 387 CMU_USB_DIV_32 = 0x5U, /**< Division by 32 */ 388 CMU_USB_DIV_64 = 0x6U, /**< Division by 64 */ 389 CMU_USB_DIV_128 = 0x7U, /**< Division by 128 */ 390 CMU_USB_DIV_256 = 0x8U, /**< Division by 256 */ 391 CMU_USB_DIV_512 = 0x9U, /**< Division by 512 */ 392 CMU_USB_DIV_1024 = 0xAU, /**< Division by 1024 */ 393 CMU_USB_DIV_2048 = 0xBU, /**< Division by 2048 */ 394 CMU_USB_DIV_4096 = 0xCU, /**< Division by 4096 */ 395 } cmu_usb_div_t; 396 397 /** 398 * @brief Peripheral clock enable/disable 399 * @verbatim 400 In this module, for the convenience of code maintenance, 401 TIMERx is used to indicate the sequence of the timer peripheral. 402 Different product series TIMERx represent different meanings: 403 1. For ES32F36xx series: 404 TIMER0 ----> AD16C4T0 405 TIMER1 ----> AD16C4T1 406 TIMER2 ----> GP32C4T0 407 TIMER3 ----> GP32C4T1 408 TIMER4 ----> BS16T0 409 TIMER5 ----> BS16T1 410 TIMER6 ----> GP16C4T0 411 TIMER7 ----> GP16C4T1 412 413 2. For ES32F393x/ES32F336x/ES32F392x series: 414 TIMER0 ----> GP16C4T0 415 TIMER1 ----> GP16C4T1 416 TIMER2 ----> GP32C4T0 417 TIMER3 ----> GP32C4T1 418 TIMER4 ----> BS16T0 419 TIMER5 ----> BS16T1 420 TIMER6 ----> GP16C4T2 421 TIMER7 ----> GP16C4T3 422 @endverbatim 423 */ 424 typedef enum { 425 CMU_PERH_GPIO = (1U << 0), /**< GPIO */ 426 CMU_PERH_CRC = (1U << 1), /**< CRC */ 427 CMU_PERH_CALC = (1U << 2), /**< CALC */ 428 CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ 429 CMU_PERH_TRNG = (1U << 4), /**< TRNG */ 430 CMU_PERH_PIS = (1U << 5), /**< PIS */ 431 CMU_PERH_EBI = (1U << 6), /**< EBI */ 432 CMU_PERH_QSPI_H = (1U << 7), /**< QSPI AHB */ 433 CMU_PERH_DMA = (1U << 8), /**< DMA */ 434 CMU_PERH_USB = (1U << 10), /**< USB */ 435 CMU_PERH_ECC = (1U << 11), /**< ECC */ 436 CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ 437 CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ 438 CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ 439 CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ 440 CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ 441 CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ 442 CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ 443 CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ 444 CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ 445 CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ 446 CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ 447 CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ 448 CMU_PERH_UART4 = (1U << 12) | (1U << 27), /**< UART4 */ 449 CMU_PERH_UART5 = (1U << 13) | (1U << 27), /**< UART5 */ 450 CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ 451 CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ 452 CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ 453 CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ 454 CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ 455 CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ 456 CMU_PERH_QSPI_P = (1U << 25) | (1U << 27), /**< QSPI APB */ 457 CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ 458 CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ 459 CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ 460 CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ 461 CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ 462 CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ 463 CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ 464 CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ 465 CMU_PERH_ACMP2 = (1U << 11) | (1U << 28), /**< ACMP2 */ 466 CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ 467 CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ 468 CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ 469 CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ 470 CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ 471 CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ 472 CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ 473 CMU_PERH_ALL = (0x7FFFFFFFU), /**< ALL */ 474 } cmu_perh_t; 475 476 /** 477 * @brief CMU interrupt type 478 */ 479 typedef enum { 480 CMU_LOSC_STOP = 0x0U, /**< LOSC STOP INTERRUPT */ 481 CMU_HOSC_STOP = 0x1U, /**< HOSC STOP INTERRUPT */ 482 CMU_PLL1_UNLOCK = 0x2U, /**< PLL1 UNLOCK INTERRUPT */ 483 CMU_LOSC_START = 0x3U, /**< LOSC START INTERRUPT */ 484 CMU_HOSC_START = 0x4U, /**< HOSC START INTERRUPT */ 485 } cmu_security_t; 486 487 /** 488 * @brief CMU clock state type 489 */ 490 typedef enum { 491 CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ 492 CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ 493 CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ 494 CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ 495 CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ 496 CMU_CLOCK_STATE_PLL1ACT = (1U << 8), /**< PLL1 active */ 497 CMU_CLOCK_STATE_PLL2ACT = (1U << 9), /**< PLL2 active */ 498 CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ 499 CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ 500 CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ 501 CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ 502 CMU_CLOCK_STATE_PLL1RDY = (1U << 24), /**< PLL1 ready */ 503 CMU_CLOCK_STATE_PLL2RDY = (1U << 25), /**< PLL2 ready */ 504 } cmu_clock_state_t; 505 506 /** 507 * @brief Stop1 clock select type 508 */ 509 typedef enum { 510 CMU_STOP1_CLOCK_LRC = 0x0U, /**< LRC */ 511 CMU_STOP1_CLOCK_HRC_24M = 0x1U, /**< HRC 24MHz */ 512 CMU_STOP1_CLOCK_HRC_2M = 0x2U, /**< HRC 2MHz */ 513 CMU_STOP1_CLOCK_HRC_1M = 0x3U, /**< HRC divides to 1MHz */ 514 CMU_STOP1_CLOCK_HOSC = 0x4U, /**< HOSC */ 515 CMU_STOP1_CLOCK_HOSC_1M = 0x5U, /**< HOSC divides to 1MHz */ 516 CMU_STOP1_CLOCK_HOSCM = 0x6U, /**< HOSC security management */ 517 } cmu_stop1_clock_t; 518 519 /** 520 * @} 521 */ 522 523 /** 524 * @defgroup CMU_Private_Macros CMU Private Macros 525 * @{ 526 */ 527 #define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ 528 ((x) == CMU_CLOCK_LRC) || \ 529 ((x) == CMU_CLOCK_LOSC) || \ 530 ((x) == CMU_CLOCK_PLL1) || \ 531 ((x) == CMU_CLOCK_HOSC)) 532 #if defined(ES32F36xx) || defined(ES32F39xx) 533 #define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \ 534 ((x) == CMU_PLL1_OUTPUT_48M) || \ 535 ((x) == CMU_PLL1_OUTPUT_72M) || \ 536 ((x) == CMU_PLL1_OUTPUT_96M)) 537 #endif 538 #ifdef ES32F336x 539 #define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \ 540 ((x) == CMU_PLL1_OUTPUT_48M)) 541 #endif 542 #define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ 543 ((x) == CMU_PLL1_INPUT_PLL2) || \ 544 ((x) == CMU_PLL1_INPUT_HOSC) || \ 545 ((x) == CMU_PLL1_INPUT_HOSC_2) || \ 546 ((x) == CMU_PLL1_INPUT_HOSC_3) || \ 547 ((x) == CMU_PLL1_INPUT_HOSC_4) || \ 548 ((x) == CMU_PLL1_INPUT_HOSC_5) || \ 549 ((x) == CMU_PLL1_INPUT_HOSC_6)) 550 #define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ 551 ((x) == CMU_HOSC_4M) || \ 552 ((x) == CMU_HOSC_8M) || \ 553 ((x) == CMU_HOSC_16M) || \ 554 ((x) == CMU_HOSC_24M)) 555 #define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ 556 ((x) == CMU_DIV_2) || \ 557 ((x) == CMU_DIV_4) || \ 558 ((x) == CMU_DIV_8) || \ 559 ((x) == CMU_DIV_16) || \ 560 ((x) == CMU_DIV_32) || \ 561 ((x) == CMU_DIV_64) || \ 562 ((x) == CMU_DIV_128) || \ 563 ((x) == CMU_DIV_256) || \ 564 ((x) == CMU_DIV_512) || \ 565 ((x) == CMU_DIV_1024) || \ 566 ((x) == CMU_DIV_2048) || \ 567 ((x) == CMU_DIV_4096)) 568 #define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ 569 ((x) == CMU_HCLK_2) || \ 570 ((x) == CMU_SYS) || \ 571 ((x) == CMU_PCLK_1) || \ 572 ((x) == CMU_PCLK_2)) 573 #define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ 574 ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ 575 ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ 576 ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ 577 ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ 578 ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ 579 ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ 580 ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) 581 #define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ 582 ((x) == CMU_OUTPUT_DIV_2) || \ 583 ((x) == CMU_OUTPUT_DIV_4) || \ 584 ((x) == CMU_OUTPUT_DIV_8) || \ 585 ((x) == CMU_OUTPUT_DIV_16) || \ 586 ((x) == CMU_OUTPUT_DIV_32) || \ 587 ((x) == CMU_OUTPUT_DIV_64) || \ 588 ((x) == CMU_OUTPUT_DIV_128)) 589 #define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ 590 ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ 591 ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ 592 ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ 593 ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) 594 #define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \ 595 ((x) == CMU_SAFE_CLK_LOSC) || \ 596 ((x) == CMU_SAFE_CLK_PLL)) 597 #define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ 598 ((x) == CMU_BUZZ_DIV_4) || \ 599 ((x) == CMU_BUZZ_DIV_8) || \ 600 ((x) == CMU_BUZZ_DIV_16) || \ 601 ((x) == CMU_BUZZ_DIV_32) || \ 602 ((x) == CMU_BUZZ_DIV_64) || \ 603 ((x) == CMU_BUZZ_DIV_128) || \ 604 ((x) == CMU_BUZZ_DIV_256)) 605 #define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ 606 ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ 607 ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ 608 ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ 609 ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ 610 ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ 611 ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ 612 ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ 613 ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ 614 ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ 615 ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ 616 ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) 617 #define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ 618 ((x) == CMU_LCD_SEL_LOSC) || \ 619 ((x) == CMU_LCD_SEL_LRC) || \ 620 ((x) == CMU_LCD_SEL_ULRC) || \ 621 ((x) == CMU_LCD_SEL_HRC_1M) || \ 622 ((x) == CMU_LCD_SEL_HOSC_1M)) 623 #define IS_CMU_QSPI_CLOCK_SEL(x) (((x) == CMU_QSPI_CLOCK_SEL_PCLK1) || \ 624 ((x) == CMU_QSPI_CLOCK_SEL_HCLK2) || \ 625 ((x) == CMU_QSPI_CLOCK_SEL_HRC) || \ 626 ((x) == CMU_QSPI_CLOCK_SEL_HOSC) || \ 627 ((x) == CMU_QSPI_CLOCK_SEL_PLL1) || \ 628 ((x) == CMU_QSPI_CLOCK_SEL_HOSM)) 629 #define IS_CMU_USB_CLOCK_SEL(x) (((x) == CMU_USB_CLOCK_SEL_HOSC) || \ 630 ((x) == CMU_USB_CLOCK_SEL_HRC) || \ 631 ((x) == CMU_USB_CLOCK_SEL_PCLK1) || \ 632 ((x) == CMU_USB_CLOCK_SEL_PLL1) || \ 633 ((x) == CMU_USB_CLOCK_SEL_HOSM)) 634 #define IS_CMU_USB_DIV(x) (((x) == CMU_USB_DIV_1) || \ 635 ((x) == CMU_USB_DIV_2) || \ 636 ((x) == CMU_USB_DIV_4) || \ 637 ((x) == CMU_USB_DIV_8) || \ 638 ((x) == CMU_USB_DIV_16) || \ 639 ((x) == CMU_USB_DIV_32) || \ 640 ((x) == CMU_USB_DIV_64) || \ 641 ((x) == CMU_USB_DIV_128) || \ 642 ((x) == CMU_USB_DIV_256) || \ 643 ((x) == CMU_USB_DIV_512) || \ 644 ((x) == CMU_USB_DIV_1024) || \ 645 ((x) == CMU_USB_DIV_2048) || \ 646 ((x) == CMU_USB_DIV_4096)) 647 #define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ 648 ((x) == CMU_PERH_CRC) || \ 649 ((x) == CMU_PERH_CALC) || \ 650 ((x) == CMU_PERH_CRYPT) || \ 651 ((x) == CMU_PERH_TRNG) || \ 652 ((x) == CMU_PERH_PIS) || \ 653 ((x) == CMU_PERH_EBI) || \ 654 ((x) == CMU_PERH_QSPI_H) || \ 655 ((x) == CMU_PERH_DMA) || \ 656 ((x) == CMU_PERH_USB) || \ 657 ((x) == CMU_PERH_ECC) || \ 658 ((x) == CMU_PERH_TIMER0) || \ 659 ((x) == CMU_PERH_TIMER1) || \ 660 ((x) == CMU_PERH_TIMER2) || \ 661 ((x) == CMU_PERH_TIMER3) || \ 662 ((x) == CMU_PERH_TIMER4) || \ 663 ((x) == CMU_PERH_TIMER5) || \ 664 ((x) == CMU_PERH_TIMER6) || \ 665 ((x) == CMU_PERH_TIMER7) || \ 666 ((x) == CMU_PERH_UART0) || \ 667 ((x) == CMU_PERH_UART1) || \ 668 ((x) == CMU_PERH_UART2) || \ 669 ((x) == CMU_PERH_UART3) || \ 670 ((x) == CMU_PERH_UART4) || \ 671 ((x) == CMU_PERH_UART5) || \ 672 ((x) == CMU_PERH_SPI0) || \ 673 ((x) == CMU_PERH_SPI1) || \ 674 ((x) == CMU_PERH_SPI2) || \ 675 ((x) == CMU_PERH_I2C0) || \ 676 ((x) == CMU_PERH_I2C1) || \ 677 ((x) == CMU_PERH_CAN) || \ 678 ((x) == CMU_PERH_QSPI_P) || \ 679 ((x) == CMU_PERH_LPTIM0) || \ 680 ((x) == CMU_PERH_LPUART0) || \ 681 ((x) == CMU_PERH_ADC0) || \ 682 ((x) == CMU_PERH_ADC1) || \ 683 ((x) == CMU_PERH_ACMP0) || \ 684 ((x) == CMU_PERH_ACMP1) || \ 685 ((x) == CMU_PERH_OPAMP) || \ 686 ((x) == CMU_PERH_DAC0) || \ 687 ((x) == CMU_PERH_ACMP2) || \ 688 ((x) == CMU_PERH_WWDT) || \ 689 ((x) == CMU_PERH_LCD) || \ 690 ((x) == CMU_PERH_IWDT) || \ 691 ((x) == CMU_PERH_RTC) || \ 692 ((x) == CMU_PERH_TSENSE) || \ 693 ((x) == CMU_PERH_BKPC) || \ 694 ((x) == CMU_PERH_DBGC) || \ 695 ((x) == CMU_PERH_ALL)) 696 #define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ 697 ((x) == CMU_CLOCK_STATE_LOSCACT) || \ 698 ((x) == CMU_CLOCK_STATE_HRCACT) || \ 699 ((x) == CMU_CLOCK_STATE_LRCACT) || \ 700 ((x) == CMU_CLOCK_STATE_ULRCACT) || \ 701 ((x) == CMU_CLOCK_STATE_PLL1ACT) || \ 702 ((x) == CMU_CLOCK_STATE_PLL2ACT) || \ 703 ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ 704 ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ 705 ((x) == CMU_CLOCK_STATE_HRCRDY) || \ 706 ((x) == CMU_CLOCK_STATE_LRCRDY) || \ 707 ((x) == CMU_CLOCK_STATE_PLL1RDY) || \ 708 ((x) == CMU_CLOCK_STATE_PLL2RDY)) 709 #define IS_CMU_STOP1_CLOCK(x) (((x) == CMU_STOP1_CLOCK_LRC) || \ 710 ((x) == CMU_STOP1_CLOCK_HRC_24M) || \ 711 ((x) == CMU_STOP1_CLOCK_HRC_2M) || \ 712 ((x) == CMU_STOP1_CLOCK_HRC_1M) || \ 713 ((x) == CMU_STOP1_CLOCK_HOSC) || \ 714 ((x) == CMU_STOP1_CLOCK_HOSC_1M) || \ 715 ((x) == CMU_STOP1_CLOCK_HOSCM)) 716 /** 717 * @} 718 */ 719 720 /** @addtogroup CMU_Public_Functions 721 * @{ 722 */ 723 /** @addtogroup CMU_Public_Functions_Group1 724 * @{ 725 */ 726 /* System clock configure */ 727 ald_status_t ald_cmu_clock_config_default(void); 728 ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock); 729 void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); 730 uint32_t ald_cmu_get_clock(void); 731 /** 732 * @} 733 */ 734 735 /** @addtogroup CMU_Public_Functions_Group2 736 * @{ 737 */ 738 /* BUS division control */ 739 void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div); 740 uint32_t ald_cmu_get_hclk1_clock(void); 741 uint32_t ald_cmu_get_hclk2_clock(void); 742 uint32_t ald_cmu_get_sys_clock(void); 743 uint32_t ald_cmu_get_pclk1_clock(void); 744 uint32_t ald_cmu_get_pclk2_clock(void); 745 /** 746 * @} 747 */ 748 749 /** @addtogroup CMU_Public_Functions_Group3 750 * @{ 751 */ 752 /* Clock safe configure */ 753 void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); 754 void ald_cmu_losc_safe_config(type_func_t status); 755 void ald_cmu_pll_safe_config(type_func_t status); 756 uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type); 757 flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); 758 void ald_cmu_irq_handler(void); 759 void ald_cmu_irq_cbk(cmu_security_t se); 760 /** 761 * @} 762 */ 763 764 /** @addtogroup CMU_Public_Functions_Group4 765 * @{ 766 */ 767 /* Clock output configure */ 768 void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, 769 cmu_output_high_div_t div, type_func_t status); 770 void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); 771 /** 772 * @} 773 */ 774 775 /** @addtogroup CMU_Public_Functions_Group5 776 * @{ 777 */ 778 /* Peripheral Clock configure */ 779 void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); 780 void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); 781 void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); 782 void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); 783 void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock); 784 void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div); 785 void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); 786 void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock); 787 /** 788 * @} 789 */ 790 /** 791 * @} 792 */ 793 794 /** 795 * @} 796 */ 797 798 /** 799 * @} 800 */ 801 #ifdef __cplusplus 802 } 803 #endif 804 805 #endif /* __ALD_CMU_H__ */ 806