1 /** 2 ********************************************************************************* 3 * 4 * @file ald_pis.h 5 * @brief Header file of PIS driver. 6 * 7 * @version V1.0 8 * @date 27 Nov 2019 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 27 Nov 2019 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_PIS_H__ 34 #define __ALD_PIS_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include "utils.h" 41 42 43 /** @addtogroup ES32FXXX_ALD 44 * @{ 45 */ 46 47 /** @addtogroup PIS 48 * @{ 49 */ 50 51 /** @defgroup PIS_Public_Types PIS Public Types 52 * @verbatim 53 In PIS module, for the convenience of code maintenance, 54 TIMERx is used to indicate the sequence of the timer peripheral. 55 Different product series TIMERx represent different meanings: 56 1. For ES32F36xx series: 57 TIMER0 ----> AD16C4T0 58 TIMER1 ----> AD16C4T1 59 TIMER2 ----> GP32C4T0 60 TIMER3 ----> GP32C4T1 61 62 2. For ES32F393x/ES32F336x/ES32F392x series: 63 TIMER0 ----> GP16C4T0 64 TIMER1 ----> GP16C4T1 65 TIMER2 ----> GP32C4T0 66 TIMER3 ----> GP32C4T1 67 @endverbatim 68 * @{ 69 */ 70 71 /** 72 * @brief Producer entry 73 */ 74 typedef enum { 75 PIS_NON = 0x0U, /**< No async */ 76 PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ 77 PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ 78 PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ 79 PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ 80 PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ 81 PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ 82 PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ 83 PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ 84 PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ 85 PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ 86 PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ 87 PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ 88 PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ 89 PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ 90 PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ 91 PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ 92 PIS_ACMP_OUT0 = 0x30U, /**< Acmp0 output, level,support async */ 93 PIS_ACMP_OUT1 = 0x31U, /**< Acmp1 output, level,support async */ 94 PIS_DAC0_CH0 = 0x40U, /**< Dac0 channel 0, pclk2 pulse,support async */ 95 PIS_DAC0_CH1 = 0x41U, /**< Dac0 channel 1, pclk2 pulse,support async */ 96 PIS_ADC0_INSERT = 0x60U, /**< Adc0 insert, pclk2 pulse,support async */ 97 PIS_ADC0_NORMAL = 0x61U, /**< Adc0 normal, pclk2 pulse,support async */ 98 PIS_ADC0_RESERVE = 0x62U, /**< Adc0 reserve */ 99 PIS_LVD = 0x70U, /**< Lvd, level,support async */ 100 PIS_UART0_RESERVE0 = 0x80U, /**< Uart0 reserve bit 0 */ 101 PIS_UART0_RESERVE1 = 0x81U, /**< Uart0 reserve bit 1*/ 102 PIS_UART0_IRDAOUT = 0x82U, /**< Uart0 irdaout, level,support async */ 103 PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level,support async */ 104 PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level,support async */ 105 PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse,support async */ 106 PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse,support async */ 107 PIS_UART1_RESERVE0 = 0x90U, /**< Uart1 reserve bit 0 */ 108 PIS_UART1_RESERVE1 = 0x91U, /**< Uart1 reserve bit 1*/ 109 PIS_UART1_IRDA = 0x92U, /**< Uart1 irdaout, level,support async */ 110 PIS_UART1_RTS = 0x93U, /**< Uart1 rtsout, level,support async */ 111 PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level,support async */ 112 PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse,support async */ 113 PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse,support async */ 114 PIS_UART2_RESERVE0 = 0xa0U, /**< Uart2 reserve bit 0 */ 115 PIS_UART2_RESERVE1 = 0xa1U, /**< Uart2 reserve bit 1*/ 116 PIS_UART2_IRDA = 0xa2U, /**< Uart2 irdaout, level,support async */ 117 PIS_UART2_RTS = 0xa3U, /**< Uart2 rtsout, level,support async */ 118 PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level,support async */ 119 PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse,support async */ 120 PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse,support async */ 121 PIS_UART3_RESERVE0 = 0xb1U, /**< Uart3 reserve bit 0 */ 122 PIS_UART3_RESERVE1 = 0xb2U, /**< Uart3 reserve bit 1*/ 123 PIS_UART3_IRDA = 0xb3U, /**< Uart3 irdaout, level,support async */ 124 PIS_UART3_RTS = 0xb4U, /**< Uart3 rtsout, level,support async */ 125 PIS_UART3_TXOUT = 0xb5U, /**< Uart3 txout, level,support async */ 126 PIS_UART3_SYN_SEND = 0xb6U, /**< Uart3 syn send, pulse,support async */ 127 PIS_UART3_SYN_RECV = 0xb7U, /**< Uart3 syn recv, pulse,support async */ 128 PIS_UART4_RECV = 0xc0U, /**< uart4 recv, plck1 pulse */ 129 PIS_UART4_SEND = 0xc1U, /**< uart4 send, plck1 pulse */ 130 PIS_UART4_TXOUT = 0xc2U, /**< uart4 txout, plck1 level */ 131 PIS_UART5_RECV = 0xd0U, /**< uart5 recv, plck1 pulse */ 132 PIS_UART5_SEND = 0xd1U, /**< uart5 send, plck1 pulse */ 133 PIS_UART5_TXOUT = 0xd2U, /**< uart5 txout, plck1 level */ 134 PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ 135 PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ 136 PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ 137 PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ 138 PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ 139 PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ 140 PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ 141 PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ 142 PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ 143 PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ 144 PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ 145 PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ 146 PIS_TIMER0_INPUT_1 = 0x122U, /**< Timer0 chan1 input catch, plck1 pulse */ 147 PIS_TIMER0_OUTPUT_1 = 0x123U, /**< Timer0 chan1 output compare, plck1 pulse */ 148 PIS_TIMER0_INPUT_2 = 0x124U, /**< Timer0 chan2 input catch, plck1 pulse */ 149 PIS_TIMER0_OUTPUT_2 = 0x125U, /**< Timer0 chan2 output compare, plck1 pulse */ 150 PIS_TIMER0_INPUT_3 = 0x126U, /**< Timer0 chan3 input catch, plck1 pulse */ 151 PIS_TIMER0_OUTPUT_3 = 0x127U, /**< Timer0 chan3 output compare, plck1 pulse */ 152 PIS_TIMER0_INPUT_4 = 0x128U, /**< Timer0 chan4 input catch, plck1 pulse */ 153 PIS_TIMER0_OUTPUT_4 = 0x129U, /**< Timer0 chan4 output compare, plck1 pulse */ 154 PIS_TIMER1_UPDATA = 0x130U, /**< Timer1 updata, plck1 pulse */ 155 PIS_TIMER1_TRIG = 0x131U, /**< Timer1 trig, plck1 pulse */ 156 PIS_TIMER1_INPUT_1 = 0x132U, /**< Timer1 chan1 input catch, plck1 pulse */ 157 PIS_TIMER1_OUTPUT_1 = 0x133U, /**< Timer1 chan1 output compare, plck1 pulse */ 158 PIS_TIMER1_INPUT_2 = 0x134U, /**< Timer1 chan2 input catch, plck1 pulse */ 159 PIS_TIMER1_OUTPUT_2 = 0x135U, /**< Timer1 chan2 output compare, plck1 pulse */ 160 PIS_TIMER1_INPUT_3 = 0x136U, /**< Timer1 chan3 input catch, plck1 pulse */ 161 PIS_TIMER1_OUTPUT_3 = 0x137U, /**< Timer1 chan3 output compare, plck1 pulse */ 162 PIS_TIMER1_INPUT_4 = 0x138U, /**< Timer1 chan4 input catch, plck1 pulse */ 163 PIS_TIMER1_OUTPUT_4 = 0x139U, /**< Timer1 chan4 output compare, plck1 pulse */ 164 PIS_TIMER2_UPDATA = 0x140U, /**< Timer2 updata, plck1 pulse */ 165 PIS_TIMER2_TRIG = 0x141U, /**< Timer2 trig, plck1 pulse */ 166 PIS_TIMER2_INPUT_1 = 0x142U, /**< Timer2 chan1 input catch, plck1 pulse */ 167 PIS_TIMER2_OUTPUT_1 = 0x143U, /**< Timer2 chan1 output compare, plck1 pulse */ 168 PIS_TIMER2_INPUT_2 = 0x144U, /**< Timer2 chan2 input catch, plck1 pulse */ 169 PIS_TIMER2_OUTPUT_2 = 0x145U, /**< Timer2 chan2 output compare, plck1 pulse */ 170 PIS_TIMER2_INPUT_3 = 0x146U, /**< Timer2 chan3 input catch, plck1 pulse */ 171 PIS_TIMER2_OUTPUT_3 = 0x147U, /**< Timer2 chan3 output compare, plck1 pulse */ 172 PIS_TIMER2_INPUT_4 = 0x148U, /**< Timer2 chan4 input catch, plck1 pulse */ 173 PIS_TIMER2_OUTPUT_4 = 0x149U, /**< Timer2 chan4 output compare, plck1 pulse */ 174 PIS_TIMER3_UPDATA = 0x150U, /**< Timer3 updata, plck1 pulse */ 175 PIS_TIMER3_TRIG = 0x151U, /**< Timer3 trig, plck1 pulse */ 176 PIS_TIMER3_INPUT_1 = 0x152U, /**< Timer3 chan1 input catch, plck1 pulse */ 177 PIS_TIMER3_OUTPUT_1 = 0x153U, /**< Timer3 chan1 output compare, plck1 pulse */ 178 PIS_TIMER3_INPUT_2 = 0x154U, /**< Timer3 chan2 input catch, plck1 pulse */ 179 PIS_TIMER3_OUTPUT_2 = 0x155U, /**< Timer3 chan2 output compare, plck1 pulse */ 180 PIS_TIMER3_INPUT_3 = 0x156U, /**< Timer3 chan3 input catch, plck1 pulse */ 181 PIS_TIMER3_OUTPUT_3 = 0x157U, /**< Timer3 chan3 output compare, plck1 pulse */ 182 PIS_TIMER3_INPUT_4 = 0x158U, /**< Timer3 chan4 input catch, plck1 pulse */ 183 PIS_TIMER3_OUTPUT_4 = 0x159U, /**< Timer3 chan4 output compare, plck1 pulse */ 184 PIS_RTC_CLOCK = 0x160U, /**< Rtc clock, pulse,support async */ 185 PIS_RTC_ALARM = 0x161U, /**< Rtc alarm, pulse,support async */ 186 PIS_LPTIMER0_SYN_UPDATA = 0x170U, /**< Lptimer0 syn updata, pulse,support async */ 187 PIS_LPTIMER0_ASY_UPDATA = 0x171U, /**< Lptimer0 asy updata, pulse,support async */ 188 PIS_LPUART0_ASY_RECV = 0x180U, /**< Lpuart0 asy recv, pulse,support async */ 189 PIS_LPUART0_ASY_SEND = 0x181U, /**< Lpuart0 asy send, pulse,support async */ 190 PIS_LPUART0_SYN_RECV = 0x182U, /**< Lpuart0 syn recv, pulse,support async */ 191 PIS_LPUART0_SYN_SEND = 0x183U, /**< Lpuart0 syn recv, pulse,support async */ 192 PIS_DMA = 0x190U, /**< Dma, pulse,support async */ 193 PIS_ADC1_INSERT = 0x1a0U, /**< Adc1 insert, pclk2 pulse,support async */ 194 PIS_ADC1_NORMAL = 0x1a1U, /**< Adc1 normal, pclk2 pulse,support async */ 195 PIS_ADC1_RESERVE = 0x1a2U, /**< Adc1 reserve */ 196 } pis_src_t; 197 198 /** 199 * @brief Consumer entry 200 */ 201 typedef enum { 202 PIS_CH12_TIMER0_ITR0 = 0x003CU, /** Tim0 internal input chan0 */ 203 PIS_CH13_TIMER0_ITR1 = 0x003DU, /** Tim0 internal input chan1 */ 204 PIS_CH14_TIMER0_ITR2 = 0x003EU, /** Tim0 internal input chan2 */ 205 PIS_CH15_TIMER0_ITR3 = 0x003FU, /** Tim0 internal input chan3 */ 206 PIS_CH12_TIMER1_ITR0 = 0x003CU, /** Tim1 internal input chan0 */ 207 PIS_CH13_TIMER1_ITR1 = 0x003DU, /** Tim1 internal input chan1 */ 208 PIS_CH14_TIMER1_ITR2 = 0x003EU, /** Tim1 internal input chan2 */ 209 PIS_CH15_TIMER1_ITR3 = 0x003FU, /** Tim1 internal input chan3 */ 210 PIS_CH12_TIMER2_ITR0 = 0x003CU, /** Tim2 internal input chan0 */ 211 PIS_CH13_TIMER2_ITR1 = 0x003DU, /** Tim2 internal input chan1 */ 212 PIS_CH14_TIMER2_ITR2 = 0x003EU, /** Tim2 internal input chan2 */ 213 PIS_CH15_TIMER2_ITR3 = 0x003FU, /** Tim2 internal input chan3 */ 214 PIS_CH12_TIMER3_ITR0 = 0x003CU, /** Tim3 internal input chan0 */ 215 PIS_CH13_TIMER3_ITR1 = 0x003DU, /** Tim3 internal input chan1 */ 216 PIS_CH14_TIMER3_ITR2 = 0x003EU, /** Tim3 internal input chan2 */ 217 PIS_CH15_TIMER3_ITR3 = 0x003FU, /** Tim3 internal input chan3 */ 218 PIS_CH6_ADC0_NORMAL = 0x0036U, /** ADC0 normal transform */ 219 PIS_CH7_ADC0_INSERT = 0x0037U, /** ADC0 insert transform */ 220 PIS_CH0_ADC1_NORMAL = 0x0030U, /** ADC1 normal transform */ 221 PIS_CH1_ADC1_INSERT = 0x0031U, /** ADC1 insert transform */ 222 PIS_CH0_LPTIM0_EXT0 = 0x0030U, /** Lptim0 external trigger 0 */ 223 PIS_CH1_LPTIM0_EXT1 = 0x0031U, /** Lptim0 external trigger 1 */ 224 PIS_CH2_LPTIM0_EXT2 = 0x0032U, /** Lptim0 external trigger 2 */ 225 PIS_CH3_LPTIM0_EXT3 = 0x0033U, /** Lptim0 external trigger 3 */ 226 PIS_CH4_LPTIM0_EXT4 = 0x0034U, /** Lptim0 external trigger 4 */ 227 PIS_CH5_LPTIM0_EXT5 = 0x0035U, /** Lptim0 external trigger 5 */ 228 PIS_CH6_LPTIM0_EXT6 = 0x0036U, /** Lptim0 external trigger 6 */ 229 PIS_CH7_LPTIM0_EXT7 = 0x0037U, /** Lptim0 external trigger 7 */ 230 PIS_CH7_DMA_REQUEST = 0x0037U, /** DMA request 7 */ 231 PIS_CH15_LPUART0_RXD = 0x081FU, /**< Lpuart Rx data */ 232 PIS_CH14_UART5_RXD = 0x071EU, /**< Uart5 Rx data */ 233 PIS_CH13_UART4_RXD = 0x061DU, /**< Uart4 Rx data */ 234 PIS_CH12_UART3_RXD = 0x031CU, /**< Uart3 Rx data */ 235 PIS_CH11_UART2_RXD = 0x021BU, /**< Uart2 Rx data */ 236 PIS_CH10_UART1_RXD = 0x011AU, /**< Uart1 Rx data */ 237 PIS_CH9_UART0_RXD = 0x0019U, /**< Uart0 Rx data */ 238 PIS_CH8_TIMER3_CH4IN = 0x1B08U, /**< Tim3 input chan4 */ 239 PIS_CH8_TIMER2_CH4IN = 0x1308U, /**< Tim2 input chan4 */ 240 PIS_CH8_SPI1_CLK = 0x0F18U, /**< Spi1 clk */ 241 PIS_CH7_TIMER3_CH3IN = 0x1A07U, /**< Tim3 input chan3 */ 242 PIS_CH7_TIMER2_CH3IN = 0x1207U, /**< Tim2 input chan3 */ 243 PIS_CH7_SPI1_RX = 0x0E17U, /**< Spi1 rx */ 244 PIS_CH6_TIMER3_CH2IN = 0x1906U, /**< Tim3 input chan2 */ 245 PIS_CH6_TIMER2_CH2IN = 0x1106U, /**< Tim2 input chan2 */ 246 PIS_CH6_SPI0_CLK = 0x0D16U, /**< SPI0 CLK */ 247 PIS_CH5_TIMER3_CH1IN = 0x1805U, /**< Tim3 input chan1 */ 248 PIS_CH5_TIMER2_CH1IN = 0x1005U, /**< Tim2 input chan1 */ 249 PIS_CH5_SPI0_RX = 0x0C15U, /**< SPI0 RX */ 250 PIS_CH4_TIMER1_CH4IN = 0x0B04U, /**< Tim1 input chan4 */ 251 PIS_CH4_TIMER0_CH4IN = 0x0304U, /**< Tim0 input chan4 */ 252 PIS_CH3_TIMER1_CH3IN = 0x0A03U, /**< Tim1 input chan3 */ 253 PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Tim0 input chan3 */ 254 PIS_CH2_TIMER1_CH2IN = 0x0902U, /**< Tim1 input chan2 */ 255 PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Tim0 input chan2 */ 256 PIS_CH1_TIMER1_CH1IN = 0x0801U, /**< Tim1 input chan1 */ 257 PIS_CH0_TIMER0_CH1IN = 0x0000U, /**< Tim0 input chan1 */ 258 PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Tim0 break in */ 259 PIS_CH0_TIMER1_BRKIN = 0x0C00U, /**< Tim1 break in */ 260 PIS_TRIG_RESERVE = 0xFFFFU, /**< Other Consumer */ 261 } pis_trig_t; 262 263 /** 264 * @brief Clock select 265 */ 266 typedef enum { 267 PIS_CLK_PCLK1 = 0U, /**< APB1 peripherals clock */ 268 PIS_CLK_PCLK2 = 1U, /**< APB2 peripherals clock */ 269 PIS_CLK_SYS = 2U, /**< AHB peripherals clock */ 270 PIS_CLK_RESERVE = 3U, /**< reserve clock */ 271 } pis_clock_t; 272 273 /** 274 * @brief Level select 275 */ 276 typedef enum { 277 PIS_EDGE_NONE = 0U, /**< None edge */ 278 PIS_EDGE_UP = 1U, /**< Up edge */ 279 PIS_EDGE_DOWN = 2U, /**< Down edge */ 280 PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ 281 } pis_edge_t; 282 283 /** 284 * @brief Output style 285 */ 286 typedef enum { 287 PIS_OUT_LEVEL = 0U, /**< Level */ 288 PIS_OUT_PULSE = 1U, /**< Pulse */ 289 } pis_output_t; 290 /** 291 * @brief Sync select 292 */ 293 typedef enum { 294 PIS_SYN_DIRECT = 0U, /**< Direct */ 295 PIS_SYN_LEVEL_ASY_APB1 = 1U, /**< Producer level signal and Consumer in APB1 */ 296 PIS_SYN_LEVEL_ASY_APB2 = 2U, /**< Producer level signal and Consumer in APB2 */ 297 PIS_SYN_LEVEL_ASY_AHB = 3U, /**< Producer level signal and Consumer in AHB */ 298 PIS_SYN_PULSE_ASY_APB1 = 4U, /**< Producer Pulse signal and Consumer in APB1 */ 299 PIS_SYN_PULSE_ASY_APB2 = 5U, /**< Producer Pulse signal and Consumer in APB2 */ 300 PIS_SYN_PULSE_ASY_AHB = 6U, /**< Producer Pulse signal and Consumer in AHB */ 301 } pis_syncsel_t; 302 303 /** 304 * @brief Pis channel 305 */ 306 typedef enum { 307 PIS_CH_0 = 0U, /**< Channel 0 */ 308 PIS_CH_1 = 1U, /**< Channel 1 */ 309 PIS_CH_2 = 2U, /**< Channel 2 */ 310 PIS_CH_3 = 3U, /**< Channel 3 */ 311 PIS_CH_4 = 4U, /**< Channel 4 */ 312 PIS_CH_5 = 5U, /**< Channel 5 */ 313 PIS_CH_6 = 6U, /**< Channel 6 */ 314 PIS_CH_7 = 7U, /**< Channel 7 */ 315 PIS_CH_8 = 8U, /**< Channel 8 */ 316 PIS_CH_9 = 9U, /**< Channel 9 */ 317 PIS_CH_10 = 10U,/**< Channel 10 */ 318 PIS_CH_11 = 11U,/**< Channel 11 */ 319 PIS_CH_12 = 12U,/**< Channel 12 */ 320 PIS_CH_13 = 13U,/**< Channel 13 */ 321 PIS_CH_14 = 14U,/**< Channel 14 */ 322 PIS_CH_15 = 15U,/**< Channel 15 */ 323 } pis_ch_t; 324 325 /** 326 * @brief Pis output channel 327 */ 328 typedef enum { 329 PIS_OUT_CH_0 = 0U, /**< Channel 0 */ 330 PIS_OUT_CH_1 = 1U, /**< Channel 1 */ 331 PIS_OUT_CH_2 = 2U, /**< Channel 2 */ 332 PIS_OUT_CH_3 = 3U, /**< Channel 3 */ 333 } pis_out_ch_t; 334 335 /** 336 * @brief Indirect value,no care of it. 337 */ 338 typedef enum { 339 PIS_CON_0 = 0U, /**< Con 0 */ 340 PIS_CON_1 = 1U, /**< Con 1 */ 341 PIS_CON_NONE = 2U, /**< None */ 342 } pis_con_t; 343 344 /** 345 * @brief PIS state structures definition 346 */ 347 typedef enum { 348 PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ 349 PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ 350 PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ 351 PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ 352 PIS_STATE_ERROR = 0x04U, /**< Error */ 353 } pis_state_t; 354 355 /** 356 * @brief PIS modulate target 357 */ 358 typedef enum { 359 PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ 360 PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ 361 PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ 362 PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ 363 PIS_LPUART0_TX = 4U, /**< Modulate lpuart0 tx */ 364 } pis_modu_targ_t; 365 366 /** 367 * @brief PIS modulate level 368 */ 369 typedef enum { 370 PIS_LOW_LEVEL = 0U, /**< Modulate low level */ 371 PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ 372 } pis_modu_level_t; 373 374 /** 375 * @brief PIS modulate source 376 */ 377 typedef enum { 378 PIS_SRC_NONE = 0U, /**< Stop modulate */ 379 PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ 380 PIS_SRC_TIMER1 = 2U, /**< Modulate source is TIMER1 */ 381 PIS_SRC_TIMER2 = 3U, /**< Modulate source is TIMER2 */ 382 PIS_SRC_TIMER3 = 4U, /**< Modulate source is TIMER3 */ 383 PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ 384 PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ 385 PIS_SRC_LPTIM0 = 7U, /**< Modulate source is LPTIM0 */ 386 PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ 387 } pis_modu_src_t; 388 389 /** 390 * @brief PIS modulate channel 391 */ 392 typedef enum { 393 PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ 394 PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ 395 PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ 396 PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ 397 } pis_modu_channel_t; 398 399 /** 400 * @brief PIS input channel chose 401 */ 402 typedef enum { 403 PIS_NONE_INPUT = 0U, /**< Consumer input none */ 404 PIS_PORT_INPUT = 1U, /**< Consumer input choose external port */ 405 PIS_CHAN_INPUT = 2U, /**< Consumer input choose pis channel */ 406 } pis_input_sel_t; 407 408 /** 409 * @brief PIS init structure definition 410 */ 411 typedef struct { 412 pis_src_t producer_src; /**< Producer entry */ 413 pis_output_t producer_signal; /**< Producer signal mode */ 414 pis_clock_t producer_clk; /**< Producer module clock */ 415 pis_edge_t producer_edge; /**< Producer module pin output edge */ 416 pis_trig_t consumer_trig; /**< Consumer entry */ 417 pis_clock_t consumer_clk; /**< Consumer clock */ 418 pis_input_sel_t input_chan; /**< Consumer input channel */ 419 } pis_init_t; 420 421 /** 422 * @brief PIS modulate config structure definition 423 */ 424 typedef struct { 425 pis_modu_targ_t target; /**< Modulate target */ 426 pis_modu_level_t level; /**< Modulate level */ 427 pis_modu_src_t src; /**< Modulate src */ 428 pis_modu_channel_t channel; /**< Modulate channel */ 429 } pis_modulate_config_t; 430 431 /** 432 * @brief PIS Handle Structure definition 433 */ 434 typedef struct pis_handle_s { 435 PIS_TypeDef *perh; /**< Register base address */ 436 pis_init_t init; /**< PIS required parameters */ 437 pis_ch_t consumer_ch; /**< Indirect value, no care of it */ 438 pis_con_t consumer_con; /**< Indirect value, no care of it */ 439 uint8_t consumer_pos; /**< Indirect value, no care of it */ 440 uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ 441 lock_state_t lock; /**< Locking object */ 442 pis_state_t state; /**< PIS operation state */ 443 } pis_handle_t; 444 /** 445 * @} 446 */ 447 448 449 /** @defgroup PIS_Private_Macros PIS Private Macros 450 * @{ 451 */ 452 #define IS_PIS(x) (((x) == PIS)) 453 #define IS_PIS_SRC(x) (((x) == PIS_NON) || \ 454 ((x) == PIS_GPIO_PIN0) || \ 455 ((x) == PIS_GPIO_PIN1) || \ 456 ((x) == PIS_GPIO_PIN2) || \ 457 ((x) == PIS_GPIO_PIN3) || \ 458 ((x) == PIS_GPIO_PIN4) || \ 459 ((x) == PIS_GPIO_PIN5) || \ 460 ((x) == PIS_GPIO_PIN6) || \ 461 ((x) == PIS_GPIO_PIN7) || \ 462 ((x) == PIS_GPIO_PIN8) || \ 463 ((x) == PIS_GPIO_PIN9) || \ 464 ((x) == PIS_GPIO_PIN10) || \ 465 ((x) == PIS_GPIO_PIN11) || \ 466 ((x) == PIS_GPIO_PIN12) || \ 467 ((x) == PIS_GPIO_PIN13) || \ 468 ((x) == PIS_GPIO_PIN14) || \ 469 ((x) == PIS_GPIO_PIN15) || \ 470 ((x) == PIS_ACMP_OUT0) || \ 471 ((x) == PIS_ACMP_OUT1) || \ 472 ((x) == PIS_DAC0_CH0) || \ 473 ((x) == PIS_DAC0_CH1) || \ 474 ((x) == PIS_ADC0_INSERT) || \ 475 ((x) == PIS_ADC0_NORMAL) || \ 476 ((x) == PIS_ADC0_RESERVE) || \ 477 ((x) == PIS_LVD) || \ 478 ((x) == PIS_UART0_RESERVE0) || \ 479 ((x) == PIS_UART0_RESERVE1) || \ 480 ((x) == PIS_UART0_IRDAOUT) || \ 481 ((x) == PIS_UART0_RTSOUT) || \ 482 ((x) == PIS_UART0_TXOUT) || \ 483 ((x) == PIS_UART0_SYN_SEND) || \ 484 ((x) == PIS_UART0_SYN_RECV) || \ 485 ((x) == PIS_UART1_RESERVE0) || \ 486 ((x) == PIS_UART1_RESERVE1) || \ 487 ((x) == PIS_UART1_IRDA) || \ 488 ((x) == PIS_UART1_RTS) || \ 489 ((x) == PIS_UART1_TXOUT) || \ 490 ((x) == PIS_UART1_SYN_SEND) || \ 491 ((x) == PIS_UART1_SYN_RECV) || \ 492 ((x) == PIS_UART2_RESERVE0) || \ 493 ((x) == PIS_UART2_RESERVE1) || \ 494 ((x) == PIS_UART2_IRDA) || \ 495 ((x) == PIS_UART2_RTS) || \ 496 ((x) == PIS_UART2_TXOUT) || \ 497 ((x) == PIS_UART2_SYN_SEND) || \ 498 ((x) == PIS_UART2_SYN_RECV) || \ 499 ((x) == PIS_UART3_RESERVE0) || \ 500 ((x) == PIS_UART3_RESERVE1) || \ 501 ((x) == PIS_UART3_IRDA) || \ 502 ((x) == PIS_UART3_RTS) || \ 503 ((x) == PIS_UART3_TXOUT) || \ 504 ((x) == PIS_UART3_SYN_SEND) || \ 505 ((x) == PIS_UART3_SYN_RECV) || \ 506 ((x) == PIS_UART4_RECV) || \ 507 ((x) == PIS_UART4_SEND) || \ 508 ((x) == PIS_UART4_TXOUT) || \ 509 ((x) == PIS_UART5_RECV) || \ 510 ((x) == PIS_UART5_SEND) || \ 511 ((x) == PIS_UART5_TXOUT) || \ 512 ((x) == PIS_SPI0_RECV) || \ 513 ((x) == PIS_SPI0_SEND) || \ 514 ((x) == PIS_SPI0_NE) || \ 515 ((x) == PIS_SPI1_RECV) || \ 516 ((x) == PIS_SPI1_SEND) || \ 517 ((x) == PIS_SPI1_NE) || \ 518 ((x) == PIS_I2C0_RECV) || \ 519 ((x) == PIS_I2C0_SEND) || \ 520 ((x) == PIS_I2C1_RECV) || \ 521 ((x) == PIS_I2C1_SEND) || \ 522 ((x) == PIS_TIMER0_UPDATA) || \ 523 ((x) == PIS_TIMER0_TRIG) || \ 524 ((x) == PIS_TIMER0_INPUT_1) || \ 525 ((x) == PIS_TIMER0_OUTPUT_1) || \ 526 ((x) == PIS_TIMER0_INPUT_2) || \ 527 ((x) == PIS_TIMER0_OUTPUT_2) || \ 528 ((x) == PIS_TIMER0_INPUT_3) || \ 529 ((x) == PIS_TIMER0_OUTPUT_3) || \ 530 ((x) == PIS_TIMER0_INPUT_4) || \ 531 ((x) == PIS_TIMER0_OUTPUT_4) || \ 532 ((x) == PIS_TIMER1_UPDATA) || \ 533 ((x) == PIS_TIMER1_TRIG) || \ 534 ((x) == PIS_TIMER1_INPUT_1) || \ 535 ((x) == PIS_TIMER1_OUTPUT_1) || \ 536 ((x) == PIS_TIMER1_INPUT_2) || \ 537 ((x) == PIS_TIMER1_OUTPUT_2) || \ 538 ((x) == PIS_TIMER1_INPUT_3) || \ 539 ((x) == PIS_TIMER1_OUTPUT_3) || \ 540 ((x) == PIS_TIMER1_INPUT_4) || \ 541 ((x) == PIS_TIMER1_OUTPUT_4) || \ 542 ((x) == PIS_TIMER2_UPDATA) || \ 543 ((x) == PIS_TIMER2_TRIG) || \ 544 ((x) == PIS_TIMER2_INPUT_1) || \ 545 ((x) == PIS_TIMER2_OUTPUT_1) || \ 546 ((x) == PIS_TIMER2_INPUT_2) || \ 547 ((x) == PIS_TIMER2_OUTPUT_2) || \ 548 ((x) == PIS_TIMER2_INPUT_3) || \ 549 ((x) == PIS_TIMER2_OUTPUT_3) || \ 550 ((x) == PIS_TIMER2_INPUT_4) || \ 551 ((x) == PIS_TIMER2_OUTPUT_4) || \ 552 ((x) == PIS_TIMER3_UPDATA) || \ 553 ((x) == PIS_TIMER3_TRIG) || \ 554 ((x) == PIS_TIMER3_INPUT_1) || \ 555 ((x) == PIS_TIMER3_OUTPUT_1) || \ 556 ((x) == PIS_TIMER3_INPUT_2) || \ 557 ((x) == PIS_TIMER3_OUTPUT_2) || \ 558 ((x) == PIS_TIMER3_INPUT_3) || \ 559 ((x) == PIS_TIMER3_OUTPUT_3) || \ 560 ((x) == PIS_TIMER3_INPUT_4) || \ 561 ((x) == PIS_TIMER3_OUTPUT_4) || \ 562 ((x) == PIS_RTC_CLOCK) || \ 563 ((x) == PIS_RTC_ALARM) || \ 564 ((x) == PIS_LPTIMER0_SYN_UPDATA) || \ 565 ((x) == PIS_LPTIMER0_ASY_UPDATA) || \ 566 ((x) == PIS_LPUART0_ASY_RECV) || \ 567 ((x) == PIS_LPUART0_ASY_SEND) || \ 568 ((x) == PIS_LPUART0_SYN_RECV) || \ 569 ((x) == PIS_LPUART0_SYN_SEND) || \ 570 ((x) == PIS_DMA) || \ 571 ((x) == PIS_ADC1_INSERT) || \ 572 ((x) == PIS_ADC1_NORMAL) || \ 573 ((x) == PIS_ADC1_RESERVE)) 574 #define IS_PIS_TRIG(x) (((x) == PIS_CH12_TIMER0_ITR0) || \ 575 ((x) == PIS_CH13_TIMER0_ITR1) || \ 576 ((x) == PIS_CH14_TIMER0_ITR2) || \ 577 ((x) == PIS_CH15_TIMER0_ITR3) || \ 578 ((x) == PIS_CH12_TIMER1_ITR0) || \ 579 ((x) == PIS_CH13_TIMER1_ITR1) || \ 580 ((x) == PIS_CH14_TIMER1_ITR2) || \ 581 ((x) == PIS_CH15_TIMER1_ITR3) || \ 582 ((x) == PIS_CH12_TIMER2_ITR0) || \ 583 ((x) == PIS_CH13_TIMER2_ITR1) || \ 584 ((x) == PIS_CH14_TIMER2_ITR2) || \ 585 ((x) == PIS_CH15_TIMER2_ITR3) || \ 586 ((x) == PIS_CH12_TIMER3_ITR0) || \ 587 ((x) == PIS_CH13_TIMER3_ITR1) || \ 588 ((x) == PIS_CH14_TIMER3_ITR2) || \ 589 ((x) == PIS_CH15_TIMER3_ITR3) || \ 590 ((x) == PIS_CH6_ADC0_NORMAL ) || \ 591 ((x) == PIS_CH7_ADC0_INSERT) || \ 592 ((x) == PIS_CH0_ADC1_NORMAL) || \ 593 ((x) == PIS_CH1_ADC1_INSERT) || \ 594 ((x) == PIS_CH0_LPTIM0_EXT0) || \ 595 ((x) == PIS_CH1_LPTIM0_EXT1) || \ 596 ((x) == PIS_CH2_LPTIM0_EXT2) || \ 597 ((x) == PIS_CH3_LPTIM0_EXT3) || \ 598 ((x) == PIS_CH4_LPTIM0_EXT4) || \ 599 ((x) == PIS_CH5_LPTIM0_EXT5) || \ 600 ((x) == PIS_CH6_LPTIM0_EXT6) || \ 601 ((x) == PIS_CH7_LPTIM0_EXT7) || \ 602 ((x) == PIS_CH7_DMA_REQUEST) || \ 603 ((x) == PIS_CH15_LPUART0_RXD) || \ 604 ((x) == PIS_CH14_UART5_RXD) || \ 605 ((x) == PIS_CH13_UART4_RXD) || \ 606 ((x) == PIS_CH12_UART3_RXD) || \ 607 ((x) == PIS_CH11_UART2_RXD) || \ 608 ((x) == PIS_CH10_UART1_RXD) || \ 609 ((x) == PIS_CH9_UART0_RXD) || \ 610 ((x) == PIS_CH8_TIMER3_CH4IN) || \ 611 ((x) == PIS_CH8_TIMER2_CH4IN) || \ 612 ((x) == PIS_CH8_SPI1_CLK) || \ 613 ((x) == PIS_CH7_TIMER3_CH3IN) || \ 614 ((x) == PIS_CH7_TIMER2_CH3IN) || \ 615 ((x) == PIS_CH7_SPI1_RX) || \ 616 ((x) == PIS_CH6_TIMER3_CH2IN) || \ 617 ((x) == PIS_CH6_TIMER2_CH2IN) || \ 618 ((x) == PIS_CH6_SPI0_CLK) || \ 619 ((x) == PIS_CH5_TIMER3_CH1IN) || \ 620 ((x) == PIS_CH5_TIMER2_CH1IN) || \ 621 ((x) == PIS_CH5_SPI0_RX) || \ 622 ((x) == PIS_CH4_TIMER1_CH4IN) || \ 623 ((x) == PIS_CH4_TIMER0_CH4IN) || \ 624 ((x) == PIS_CH3_TIMER1_CH3IN) || \ 625 ((x) == PIS_CH3_TIMER0_CH3IN) || \ 626 ((x) == PIS_CH2_TIMER1_CH2IN) || \ 627 ((x) == PIS_CH2_TIMER0_CH2IN) || \ 628 ((x) == PIS_CH1_TIMER1_CH1IN) || \ 629 ((x) == PIS_CH0_TIMER0_CH1IN) || \ 630 ((x) == PIS_CH0_TIMER0_BRKIN) || \ 631 ((x) == PIS_CH0_TIMER1_BRKIN) || \ 632 ((x) == PIS_TRIG_RESERVE) || \ 633 ((x) == PIS_CH8_SPI1_CLK)) 634 #define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ 635 ((x) == PIS_CLK_PCLK2) || \ 636 ((x) == PIS_CLK_SYS)) 637 #define IS_PIS_SIGNAL_MODE(x) (((x) == PIS_OUT_LEVEL) || \ 638 ((x) == PIS_OUT_PULSE)) 639 #define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ 640 ((x) == PIS_EDGE_UP) || \ 641 ((x) == PIS_EDGE_DOWN) || \ 642 ((x) == PIS_EDGE_UP_DOWN)) 643 #define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ 644 ((x) == PIS_OUT_PULSE)) 645 #define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ 646 ((x) == PIS_OUT_CH_1) || \ 647 ((x) == PIS_OUT_CH_2) || \ 648 ((x) == PIS_OUT_CH_3)) 649 #define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ 650 ((x) == PIS_UART1_TX) || \ 651 ((x) == PIS_UART2_TX) || \ 652 ((x) == PIS_UART3_TX) || \ 653 ((x) == PIS_LPUART0_TX)) 654 #define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ 655 ((x) == PIS_HIGH_LEVEL)) 656 #define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ 657 ((x) == PIS_SRC_TIMER0) || \ 658 ((x) == PIS_SRC_TIMER1) || \ 659 ((x) == PIS_SRC_TIMER2) || \ 660 ((x) == PIS_SRC_TIMER3) || \ 661 ((x) == PIS_SRC_TIMER6) || \ 662 ((x) == PIS_SRC_TIMER7) || \ 663 ((x) == PIS_SRC_LPTIM0) || \ 664 ((x) == PIS_SRC_BUZ)) 665 #define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ 666 ((x) == PIS_TIMER_CH2) || \ 667 ((x) == PIS_TIMER_CH3) || \ 668 ((x) == PIS_TIMER_CH4)) 669 /** 670 * @} 671 */ 672 673 /** @addtogroup PIS_Public_Functions 674 * @{ 675 */ 676 677 /** @addtogroup PIS_Public_Functions_Group1 678 * @{ 679 */ 680 ald_status_t ald_pis_create(pis_handle_t *hperh); 681 ald_status_t ald_pis_destroy(pis_handle_t *hperh); 682 /** 683 * @} 684 */ 685 686 /** @addtogroup PIS_Public_Functions_Group2 687 * @{ 688 */ 689 ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); 690 ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); 691 /** 692 * @} 693 */ 694 695 /** @addtogroup PIS_Public_Functions_Group3 696 * @{ 697 */ 698 pis_state_t ald_pis_get_state(pis_handle_t *hperh); 699 /** 700 * @} 701 */ 702 703 /** @addtogroup PIS_Public_Functions_Group4 704 * @{ 705 */ 706 ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); 707 /** 708 * @} 709 */ 710 711 /** 712 * @} 713 */ 714 715 /** 716 * @} 717 */ 718 719 /** 720 * @} 721 */ 722 723 #ifdef __cplusplus 724 } 725 #endif 726 727 #endif /* __ALD_PIS_H__ */ 728