1 /**
2 *********************************************************************************
3 *
4 * @file ald_ebi.c
5 * @brief EBI module driver.
6 *
7 * @version V1.0
8 * @date 20 Jan 2019
9 * @author AE Team
10 * @note
11 * Change Logs:
12 * Date Author Notes
13 * 20 Jan 2019 AE Team The first version
14 *
15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
16 *
17 * SPDX-License-Identifier: Apache-2.0
18 *
19 * Licensed under the Apache License, Version 2.0 (the License); you may
20 * not use this file except in compliance with the License.
21 * You may obtain a copy of the License at
22 *
23 * www.apache.org/licenses/LICENSE-2.0
24 *
25 * Unless required by applicable law or agreed to in writing, software
26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
28 * See the License for the specific language governing permissions and
29 * limitations under the License.
30 **********************************************************************************
31 */
32
33 #include "ald_conf.h"
34
35 /** @addtogroup ES32FXXX_ALD
36 * @{
37 */
38
39 /** @defgroup EBI EBI
40 * @brief EBI module driver
41 * @{
42 */
43 #ifdef ALD_EBI
44
45 /** @defgroup EBI_Public_Functions EBI Public Functions
46 * @{
47 */
48
49 /** @defgroup EBI_Public_Functions_Group1 NOR-FLASH SRAM initialize functions
50 * @brief NOR-FLASH SRAM initialize functions
51 * @{
52 */
53 /**
54 * @brief Initialize the EBI_NOR_SRAM device according to the specified
55 * control parameters in the EBI_NOR_SRAM_InitTypeDef
56 * @param dev: Pointer to NOR_SRAM device instance
57 * @param init: Pointer to NOR_SRAM Initialization structure
58 * @retval None
59 */
ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef * dev,ald_ebi_nor_sram_init_t * init)60 void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
61 {
62 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
63 assert_param(IS_EBI_NORSRAM_BANK(init->bank));
64 assert_param(IS_EBI_MUX(init->mux));
65 assert_param(IS_EBI_MEMORY(init->type));
66 assert_param(IS_EBI_NORSRAM_MEMORY_WIDTH(init->width));
67 assert_param(IS_EBI_BURSTMODE(init->acc_mode));
68 assert_param(IS_EBI_WAIT_POLARITY(init->polarity));
69 assert_param(IS_EBI_WRAP_MODE(init->wrap_mode));
70 assert_param(IS_EBI_WAIT_SIGNAL_ACTIVE(init->active));
71 assert_param(IS_EBI_WRITE_OPERATION(init->write));
72 assert_param(IS_EBI_WAITE_SIGNAL(init->signal));
73 assert_param(IS_EBI_EXTENDED_MODE(init->ext_mode));
74 assert_param(IS_EBI_ASYNWAIT(init->wait));
75 assert_param(IS_EBI_WRITE_BURST(init->burst));
76
77 /* Disable NORSRAM device */
78 ald_ebi_nor_sram_disable(dev, init->bank);
79
80 /* Set NORSRAM device control parameters */
81 if (init->type == EBI_MEMORY_TYPE_NOR) {
82 MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)((uint32_t)EBI_NORSRAM_FLASH_ACCESS_ENABLE
83 | (uint32_t)init->mux
84 | (uint32_t)init->type
85 | (uint32_t)init->width
86 | (uint32_t)init->acc_mode
87 | (uint32_t)init->polarity
88 | (uint32_t)init->wrap_mode
89 | (uint32_t)init->active
90 | (uint32_t)init->write
91 | (uint32_t)init->signal
92 | (uint32_t)init->ext_mode
93 | (uint32_t)init->wait
94 | (uint32_t)init->burst));
95 }
96 else {
97 MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)(EBI_NORSRAM_FLASH_ACCESS_DISABLE
98 | (uint32_t)init->mux
99 | (uint32_t)init->type
100 | (uint32_t)init->width
101 | (uint32_t)init->acc_mode
102 | (uint32_t)init->polarity
103 | (uint32_t)init->wrap_mode
104 | (uint32_t)init->active
105 | (uint32_t)init->write
106 | (uint32_t)init->signal
107 | (uint32_t)init->ext_mode
108 | (uint32_t)init->wait
109 | (uint32_t)init->burst));
110 }
111 }
112
113 /**
114 * @brief Initialize the EBI_NOR_SRAM Timing according to the specified
115 * parameters in the EBI_NOR_SRAM_TimingTypeDef
116 * @param dev: Pointer to NOR_SRAM device instance
117 * @param timing: Pointer to NOR_SRAM Timing structure
118 * @param bank: NOR_SRAM bank number
119 * @retval None
120 */
ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef * dev,ald_ebi_nor_sram_timing_t * timing,uint32_t bank)121 void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
122 {
123 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
124 assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
125 assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
126 assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
127 assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
128 assert_param(IS_EBI_DATA_LATENCY(timing->latency));
129 assert_param(IS_EBI_ACCESS_MODE(timing->mode));
130 assert_param(IS_EBI_NORSRAM_BANK(bank));
131
132 /* Set EBI_NORSRAM device timing parameters */
133 MODIFY_REG(dev->BTCR[bank + 1U], BTR_CLEAR_MASK, \
134 (uint32_t)(timing->addr_setup | \
135 ((timing->addr_hold) << EBI_BTRx_ADDHOLD_POSS) | \
136 ((timing->data_setup) << EBI_BTRx_DATAHOLD_POSS) | \
137 ((timing->bus_dur) << EBI_BTRx_BUSTURN_POSS) | \
138 (((timing->div) - 1U) << EBI_BTRx_CLKDIV_POSS) | \
139 (((timing->latency) - 1U) << EBI_BTRx_DATALAT_POSS) | \
140 (timing->mode)));
141 }
142
143 /**
144 * @brief Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified
145 * parameters in the EBI_NOR_SRAM_TimingTypeDef
146 * @param dev: Pointer to NOR_SRAM device instance
147 * @param timing: Pointer to NOR_SRAM Timing structure
148 * @param bank: NOR_SRAM bank number
149 * @param mode EBI Extended Mode
150 * This parameter can be one of the following values:
151 * @arg EBI_EXTENDED_MODE_DISABLE
152 * @arg EBI_EXTENDED_MODE_ENABLE
153 * @retval None
154 */
ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef * dev,ald_ebi_nor_sram_timing_t * timing,uint32_t bank,uint32_t mode)155 void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
156 {
157 assert_param(IS_EBI_EXTENDED_MODE(mode));
158
159 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
160 if (mode == EBI_EXTENDED_MODE_ENABLE) {
161 assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(dev));
162 assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
163 assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
164 assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
165 assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
166 assert_param(IS_EBI_ACCESS_MODE(timing->mode));
167 assert_param(IS_EBI_NORSRAM_BANK(bank));
168
169 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
170 MODIFY_REG(dev->BWTR[bank], BWTR_CLEAR_MASK, \
171 (uint32_t)(timing->addr_setup | \
172 ((timing->addr_hold) << EBI_BWRTRx_ADDHOLD_POSS) | \
173 ((timing->data_setup) << EBI_BWRTRx_DATAHOLD_POSS) | \
174 timing->mode | \
175 ((timing->bus_dur) << EBI_BWRTRx_BUSTURN_POSS)));
176 }
177 else {
178 dev->BWTR[bank] = 0x0FFFFFFFU;
179 }
180 }
181
182 /**
183 * @brief DeInitialize the EBI_NOR_SRAM peripheral
184 * @param dev: Pointer to NOR_SRAM device instance
185 * @param e_dev: Pointer to NOR_SRAM extended mode device instance
186 * @param bank: NOR_SRAM bank number
187 * @retval ald status
188 */
ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef * dev,EBI_NOR_SRAM_EXTENDED_TypeDef * e_dev,uint32_t bank)189 ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
190 {
191 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
192 assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(e_dev));
193 assert_param(IS_EBI_NORSRAM_BANK(bank));
194
195 /* Disable the EBI_NOR/SRAM device */
196 ald_ebi_nor_sram_disable(dev, bank);
197
198 /* De-initialize the EBI_NOR/SRAM device */
199 if (bank == EBI_NORSRAM_BANK1)
200 dev->BTCR[bank] = 0x000030DBU;
201 else
202 dev->BTCR[bank] = 0x000030D2U;
203
204 dev->BTCR[bank + 1U] = 0x0FFFFFFFU;
205 e_dev->BWTR[bank] = 0x0FFFFFFFU;
206
207 return OK;
208 }
209 /**
210 * @}
211 */
212
213 /** @defgroup EBI_Public_Functions_Group2 NOR-FLASH SRAM control functions
214 * @brief NOR-FLASH SRAM control functions
215 * @{
216 */
217 /**
218 * @brief Enable the NOR/SRAM device access.
219 * @param dev: NOR/SRAM Instance
220 * @param bank: NOR/SRAM Bank
221 * @retval none
222 */
ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef * dev,uint32_t bank)223 void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
224 {
225 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
226 assert_param(IS_EBI_NORSRAM_BANK(bank));
227
228 SET_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
229 }
230
231 /**
232 * @brief Disable the NORSRAM device access.
233 * @param dev: EBI_NORSRAM Instance
234 * @param bank: EBI_NORSRAM Bank
235 * @retval none
236 */
ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef * dev,uint32_t bank)237 void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
238 {
239 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
240 assert_param(IS_EBI_NORSRAM_BANK(bank));
241
242 CLEAR_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
243 }
244
245 /**
246 * @brief Enables dynamically NOR-FLASH/SRAM write operation.
247 * @param dev: Pointer to NOR/SRAM device instance
248 * @param bank: NOR/SRAM bank number
249 * @retval void
250 */
ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef * dev,uint32_t bank)251 void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
252 {
253 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
254 assert_param(IS_EBI_NORSRAM_BANK(bank));
255
256 /* Enable write operation */
257 SET_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
258 }
259
260 /**
261 * @brief Disables dynamically EBI_NORSRAM write operation.
262 * @param dev: Pointer to NORSRAM device instance
263 * @param bank: NORSRAM bank number
264 * @retval None
265 */
ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef * dev,uint32_t bank)266 void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
267 {
268 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
269 assert_param(IS_EBI_NORSRAM_BANK(bank));
270
271 /* Disable write operation */
272 CLEAR_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
273 }
274 /**
275 * @}
276 */
277
278 /** @defgroup EBI_Public_Functions_Group3 NAND-FLASH initialize functions
279 * @brief NAND-FLASH initialize functions
280 * @{
281 */
282 /**
283 * @brief Initializes the EBI_NAND device according to the specified
284 * control parameters in the EBI_NAND_HandleTypeDef
285 * @param dev: Pointer to NAND device instance
286 * @param init: Pointer to NAND Initialization structure
287 * @retval None
288 */
ald_ebi_nand_init(EBI_NAND_TypeDef * dev,ald_ebi_nand_init_t * init)289 void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
290 {
291 assert_param(IS_EBI_NAND_DEVICE(dev));
292 assert_param(IS_EBI_NAND_BANK(init->bank));
293 assert_param(IS_EBI_WAIT_FEATURE(init->wait));
294 assert_param(IS_EBI_NAND_MEMORY_WIDTH(init->width));
295 assert_param(IS_EBI_ECC_STATE(init->ecc));
296 assert_param(IS_EBI_ECCPAGE_SIZE(init->size));
297 assert_param(IS_EBI_TCLR_TIME(init->cle_time));
298 assert_param(IS_EBI_TAR_TIME(init->ale_time));
299
300 /* Set NAND device control parameters */
301 if (init->bank == EBI_NAND_BANK2) {
302 MODIFY_REG(dev->PCTRLR2, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait |
303 (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND |
304 (uint32_t)init->width |
305 (uint32_t)init->ecc |
306 (uint32_t)init->size |
307 (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
308 (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
309 }
310 else {
311 MODIFY_REG(dev->PCTRLR3, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait |
312 (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND |
313 (uint32_t)init->width |
314 (uint32_t)init->ecc |
315 (uint32_t)init->size |
316 (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
317 (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
318 }
319 }
320
321 /**
322 * @brief Initializes the EBI_NAND Common space Timing according to the specified
323 * parameters in the EBI_NAND_TimingTypeDef
324 * @param dev: Pointer to NAND device instance
325 * @param timing: Pointer to NAND timing structure
326 * @param bank: NAND bank number
327 * @retval None
328 */
ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef * dev,ald_ebi_nand_timing_t * timing,uint32_t bank)329 void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
330 {
331 assert_param(IS_EBI_NAND_DEVICE(dev));
332 assert_param(IS_EBI_SETUP_TIME(timing->time));
333 assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
334 assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
335 assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
336 assert_param(IS_EBI_NAND_BANK(bank));
337
338 /* Set EBI_NAND device timing parameters */
339 if (bank == EBI_NAND_BANK2) {
340 MODIFY_REG(dev->PMEMR2, PMEMR_CLEAR_MASK, (timing->time | \
341 ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
342 ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
343 ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS)));
344 }
345 else {
346 MODIFY_REG(dev->PMEMR3, PMEMR_CLEAR_MASK, (timing->time | \
347 ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
348 ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
349 ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS)));
350 }
351 }
352
353 /**
354 * @brief Initializes the EBI_NAND Attribute space Timing according to the specified
355 * parameters in the EBI_NAND_TimingTypeDef
356 * @param dev: Pointer to NAND device instance
357 * @param timing: Pointer to NAND timing structure
358 * @param bank: NAND bank number
359 * @retval None
360 */
ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef * dev,ald_ebi_nand_timing_t * timing,uint32_t bank)361 void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
362 {
363 assert_param(IS_EBI_NAND_DEVICE(dev));
364 assert_param(IS_EBI_SETUP_TIME(timing->time));
365 assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
366 assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
367 assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
368 assert_param(IS_EBI_NAND_BANK(bank));
369
370 /* Set FMC_NAND device timing parameters */
371 if (bank == EBI_NAND_BANK2) {
372 MODIFY_REG(dev->PATTR2, PATTR_CLEAR_MASK, (timing->time | \
373 ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
374 ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
375 ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS)));
376 }
377 else {
378 MODIFY_REG(dev->PATTR3, PATTR_CLEAR_MASK, (timing->time | \
379 ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
380 ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
381 ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS)));
382 }
383 }
384
385 /**
386 * @brief DeInitializes the EBI_NAND device
387 * @param dev: Pointer to NAND device instance
388 * @param bank: NAND bank number
389 * @retval None
390 */
ald_ebi_nand_deinit(EBI_NAND_TypeDef * dev,uint32_t bank)391 void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
392 {
393 assert_param(IS_EBI_NAND_DEVICE(dev));
394 assert_param(IS_EBI_NAND_BANK(bank));
395
396 /* Disable the NAND Bank */
397 ald_ebi_nand_disable(dev, bank);
398
399 /* De-initialize the NAND Bank */
400 if (bank == EBI_NAND_BANK2) {
401 /* Set the EBI_NAND_BANK2 registers to their reset values */
402 WRITE_REG(dev->PCTRLR2, 0x00000018U);
403 WRITE_REG(dev->STAR2, 0x00000040U);
404 WRITE_REG(dev->PMEMR2, 0xFCFCFCFCU);
405 WRITE_REG(dev->PATTR2, 0xFCFCFCFCU);
406 }
407 /* EBI_Bank3_NAND */
408 else {
409 /* Set the EBI_NAND_BANK3 registers to their reset values */
410 WRITE_REG(dev->PCTRLR3, 0x00000018U);
411 WRITE_REG(dev->STAR3, 0x00000040U);
412 WRITE_REG(dev->PMEMR3, 0xFCFCFCFCU);
413 WRITE_REG(dev->PATTR3, 0xFCFCFCFCU);
414 }
415 }
416 /**
417 * @}
418 */
419
420 /** @defgroup EBI_Public_Functions_Group4 NAND-FLASH control functions
421 * @brief NAND-FLASH control functions
422 * @{
423 */
424 /**
425 * @brief Enable the NAND device access
426 * @param dev: EBI_NAND Instance
427 * @param bank: EBI_NAND Bank
428 * @retval None
429 */
ald_ebi_nand_enable(EBI_NAND_TypeDef * dev,uint32_t bank)430 void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
431 {
432 assert_param(IS_EBI_NAND_DEVICE(dev));
433 assert_param(IS_EBI_NAND_BANK(bank));
434
435 if (bank == EBI_NAND_BANK2)
436 SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
437 else
438 SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
439 }
440
441 /**
442 * @brief Disable the NAND device access.
443 * @param dev: EBI_NAND Instance
444 * @param bank: EBI_NAND Bank
445 * @retval None
446 */
ald_ebi_nand_disable(EBI_NAND_TypeDef * dev,uint32_t bank)447 void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
448 {
449 assert_param(IS_EBI_NAND_DEVICE(dev));
450 assert_param(IS_EBI_NAND_BANK(bank));
451
452 if (bank == EBI_NAND_BANK2)
453 CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
454 else
455 CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
456 }
457
458 /**
459 * @brief Enable the NAND device interrupt.
460 * @param dev: EBI_NAND Instance
461 * @param bank: EBI_NAND Bank
462 * @param it: EBI_NAND interrupt
463 * This parameter can be any combination of the following values:
464 * @arg EBI_IT_RISING_EDGE: Interrupt rising edge.
465 * @arg EBI_IT_LEVEL: Interrupt level.
466 * @arg EBI_IT_FALLING_EDGE: Interrupt falling edge.
467 * @retval None
468 */
ald_ebi_nand_enable_it(EBI_NAND_TypeDef * dev,uint32_t bank,ebi_it_t it)469 void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
470 {
471 assert_param(IS_EBI_NAND_DEVICE(dev));
472 assert_param(IS_EBI_NAND_BANK(bank));
473
474 if (bank == EBI_NAND_BANK2)
475 SET_BIT(dev->STAR2, it);
476 else
477 SET_BIT(dev->STAR3, it);
478 }
479
480 /**
481 * @brief Disable the NAND device interrupt.
482 * @param dev: EBI_NAND Instance
483 * @param bank: EBI_NAND Bank
484 * @param it: EBI_NAND interrupt
485 * This parameter can be any combination of the following values:
486 * @arg EBI_IT_RISING_EDGE: Interrupt rising edge.
487 * @arg EBI_IT_LEVEL: Interrupt level.
488 * @arg EBI_IT_FALLING_EDGE: Interrupt falling edge.
489 * @retval None
490 */
ald_ebi_nand_disable_it(EBI_NAND_TypeDef * dev,uint32_t bank,ebi_it_t it)491 void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
492 {
493 assert_param(IS_EBI_NAND_DEVICE(dev));
494 assert_param(IS_EBI_NAND_BANK(bank));
495
496 if (bank == EBI_NAND_BANK2)
497 CLEAR_BIT(dev->STAR2, it);
498 else
499 CLEAR_BIT(dev->STAR3, it);
500 }
501
502 /**
503 * @brief Enables dynamically EBI_NAND ECC feature.
504 * @param dev: Pointer to NAND device instance
505 * @param bank: NAND bank number
506 * @retval None
507 */
ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef * dev,uint32_t bank)508 void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
509 {
510 assert_param(IS_EBI_NAND_DEVICE(dev));
511 assert_param(IS_EBI_NAND_BANK(bank));
512
513 /* Enable ECC feature */
514 if (bank == EBI_NAND_BANK2)
515 SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
516 else
517 SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
518 }
519
520 /**
521 * @brief Disables dynamically EBI_NAND ECC feature.
522 * @param dev: Pointer to NAND device instance
523 * @param bank: NAND bank number
524 * @retval None
525 */
ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef * dev,uint32_t bank)526 void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
527 {
528 assert_param(IS_EBI_NAND_DEVICE(dev));
529 assert_param(IS_EBI_NAND_BANK(bank));
530
531 /* Disable ECC feature */
532 if (bank == EBI_NAND_BANK2)
533 CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
534 else
535 CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
536 }
537
538 /**
539 * @brief Disables dynamically EBI_NAND ECC feature.
540 * @param dev: Pointer to NAND device instance
541 * @param val: Pointer to ECC value
542 * @param bank: NAND bank number
543 * @param timeout: Timeout wait value
544 * @retval ALD status
545 */
ald_ebi_nand_get_ecc(EBI_NAND_TypeDef * dev,uint32_t * val,uint32_t bank,uint32_t timeout)546 ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
547 {
548 uint32_t tick;
549
550 assert_param(IS_EBI_NAND_DEVICE(dev));
551 assert_param(IS_EBI_NAND_BANK(bank));
552
553 tick = ald_get_tick();
554
555 /* Wait until FIFO is empty */
556 while (ald_ebi_nand_get_flag(dev, bank, EBI_FLAG_FEMPT) == RESET) {
557 if (timeout != ALD_MAX_DELAY) {
558 if ((timeout == 0U) || ((ald_get_tick() - tick) > timeout))
559 return TIMEOUT;
560 }
561 }
562
563 if (bank == EBI_NAND_BANK2)
564 *val = (uint32_t)dev->ECCRESULT2;
565 else
566 *val = (uint32_t)dev->ECCRESULT3;
567
568 return OK;
569 }
570
571 /**
572 * @brief Get flag status of the NAND device.
573 * @param dev: EBI_NAND Instance
574 * @param bank : EBI_NAND Bank
575 * @param flag : EBI_NAND flag
576 * This parameter can be any combination of the following values:
577 * @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
578 * @arg EBI_FLAG_LEVEL: Interrupt level edge flag.
579 * @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
580 * @arg EBI_FLAG_FEMPT: FIFO empty flag.
581 * @retval Status:
582 * - 0: RESET
583 * - 1: SET
584 */
ald_ebi_nand_get_flag(EBI_NAND_TypeDef * dev,uint32_t bank,ebi_flag_t flag)585 flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
586 {
587 assert_param(IS_EBI_NAND_DEVICE(dev));
588 assert_param(IS_EBI_NAND_BANK(bank));
589
590 if (bank == EBI_NAND_BANK2) {
591 if (dev->STAR2 & flag)
592 return SET;
593 } else {
594 if (dev->STAR3 & flag)
595 return SET;
596 }
597
598 return RESET;
599 }
600
601 /**
602 * @brief Clear flag status of the NAND device.
603 * @param dev: EBI_NAND Instance
604 * @param bank: EBI_NAND Bank
605 * @param flag: EBI_NAND flag
606 * This parameter can be any combination of the following values:
607 * @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
608 * @arg EBI_FLAG_LEVEL: Interrupt level edge flag.
609 * @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
610 * @arg EBI_FLAG_FEMPT: FIFO empty flag.
611 * @retval None
612 */
ald_ebi_nand_clear_flag(EBI_NAND_TypeDef * dev,uint32_t bank,ebi_flag_t flag)613 void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
614 {
615 assert_param(IS_EBI_NAND_DEVICE(dev));
616 assert_param(IS_EBI_NAND_BANK(bank));
617
618 /* Enable ECC feature */
619 if (bank == EBI_NAND_BANK2)
620 CLEAR_BIT(dev->STAR2, flag);
621 else
622 CLEAR_BIT(dev->STAR3, flag);
623 }
624 /**
625 * @}
626 */
627
628 /** @defgroup EBI_Public_Functions_Group5 LCD initialize functions
629 * @brief LCD initialize functions
630 * @{
631 */
632 /**
633 * @brief Initializes the EBI_LCD device according to the specified
634 * control parameters in the nor_lcd_handle_t
635 * @param hlcd: Pointer to LCD device instance
636 * @retval None
637 */
ald_ebi_lcd_init(ebi_lcd_handle_t * hlcd)638 void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd)
639 {
640 assert_param(IS_EBI_LCD_DEVICE(hlcd->inst));
641 assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
642 assert_param(IS_EBI_HORIZONTAL_SYNCH(hlcd->init.h_polarity));
643 assert_param(IS_EBI_VERTICAL_SYNCH(hlcd->init.v_polarity));
644 assert_param(IS_EBI_DATA_ENABLE(hlcd->init.data_polarity));
645 assert_param(IS_EBI_LCD_ENABLE(hlcd->init.enable));
646 assert_param(IS_EBI_DATA_CLOCK(hlcd->init.clk_polarity));
647 assert_param(IS_EBI_LCD_DATASETUP_TIME(hlcd->init.setup));
648 assert_param(IS_EBI_HYSNC_PULSE_WIDTH(hlcd->init.h_width));
649 assert_param(IS_EBI_VSYNC_PULSE_WIDTH(hlcd->init.v_width));
650 assert_param(IS_EBI_FRAME_LINE_NUMBER(hlcd->init.nr_line));
651 assert_param(IS_EBI_FRAME_PIXEL_NUMBER(hlcd->init.nr_pixel));
652
653 MODIFY_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], LCDCTRL_CLEAR_MASK,
654 ((uint32_t)hlcd->init.h_polarity |
655 (uint32_t)hlcd->init.v_polarity |
656 hlcd->init.data_polarity |
657 hlcd->init.enable |
658 hlcd->init.clk_polarity |
659 hlcd->init.setup << EBI_LCDCTRLx_DATASETUP_POSS |
660 hlcd->init.h_width << EBI_LCDCTRLx_VSYNCWID_POSS |
661 hlcd->init.v_width << EBI_LCDCTRLx_HSYNCWID_POSS));
662
663 WRITE_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4 + 1],
664 (hlcd->init.nr_line << EBI_LCDSTx_LINECNT_POSS |
665 hlcd->init.nr_pixel << EBI_LCDSTx_PXLCNT_POSS));
666 }
667
668 /**
669 * @brief Reset the EBI_LCD
670 * @param hlcd: Pointer to LCD device instance
671 * @retval None
672 */
ald_ebi_lcd_reset(ebi_lcd_handle_t * hlcd)673 void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd)
674 {
675 assert_param(IS_EBI_LCD_RESET(hlcd->init.reset));
676 assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
677
678 SET_BIT(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], hlcd->init.reset);
679 }
680
681 /**
682 * @}
683 */
684 /**
685 * @}
686 */
687 #endif
688 /**
689 * @}
690 */
691 /**
692 * @}
693 */
694