1 /** 2 ********************************************************************************* 3 * 4 * @file ald_dma.h 5 * @brief DMA module Library. 6 * 7 * @version V1.0 8 * @date 16 Feb. 2023 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 16 Feb. 2023 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_DMA_H__ 34 #define __ALD_DMA_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif /* __cplusplus */ 39 40 #include "ald_utils.h" 41 42 /** @addtogroup ES32VF2264_ALD 43 * @{ 44 */ 45 46 /** @addtogroup DMA 47 * @{ 48 */ 49 50 /** 51 * @defgroup DMA_Public_Macros DMA Public Macros 52 * @{ 53 */ 54 #define ALD_DMA_CH_COUNT 7U 55 /** 56 * @} 57 */ 58 59 /** 60 * @defgroup DMA_Public_Types DMA Public Types 61 * @{ 62 */ 63 64 /** 65 * @brief Input source to DMA channel 66 */ 67 typedef enum { 68 ALD_DMA_MSEL_NONE = 0x0U, /**< NONE */ 69 ALD_DMA_MSEL_GPIO = 0x1U, /**< GPIO */ 70 ALD_DMA_MSEL_ADC = 0x2U, /**< ADC */ 71 ALD_DMA_MSEL_CRC = 0x3U, /**< CRC */ 72 ALD_DMA_MSEL_EUART0 = 0x4U, /**< EUART0 */ 73 ALD_DMA_MSEL_EUART1 = 0x5U, /**< EUART1 */ 74 ALD_DMA_MSEL_CUART0 = 0x6U, /**< CUART0 */ 75 ALD_DMA_MSEL_CUART1 = 0x7U, /**< CUART1 */ 76 ALD_DMA_MSEL_CUART2 = 0x8U, /**< CUART2 */ 77 ALD_DMA_MSEL_SPI0 = 0x9U, /**< SPI0 */ 78 ALD_DMA_MSEL_SPI1 = 0xAU, /**< SPI1 */ 79 ALD_DMA_MSEL_I2C0 = 0xBU, /**< I2C0 */ 80 ALD_DMA_MSEL_I2C1 = 0xCU, /**< I2C1 */ 81 ALD_DMA_MSEL_AD16C4T = 0xDU, /**< AD16C4T */ 82 ALD_DMA_MSEL_GP16C4T0= 0xEU, /**< GP16C4T0 */ 83 ALD_DMA_MSEL_GP16C4T1= 0xFU, /**< GP16C4T1 */ 84 ALD_DMA_MSEL_GP16C4T2= 0x10U, /**< GP16C4T2 */ 85 ALD_DMA_MSEL_PIS = 0x11U, /**< PIS */ 86 ALD_DMA_MSEL_BS16T = 0x12U, /**< BS16T */ 87 } ald_dma_msel_t; 88 89 /** 90 * @brief Input signal to DMA channel 91 */ 92 typedef enum { 93 ALD_DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ 94 ALD_DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ 95 ALD_DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ 96 ALD_DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ 97 ALD_DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ 98 ALD_DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ 99 ALD_DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ 100 ALD_DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ 101 ALD_DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ 102 ALD_DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ 103 ALD_DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ 104 ALD_DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ 105 ALD_DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ 106 ALD_DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ 107 ALD_DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ 108 ALD_DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ 109 ALD_DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ 110 ALD_DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ 111 ALD_DMA_MSIGSEL_CRC = 0x0U, /**< CRC */ 112 ALD_DMA_MSIGSEL_UART_RNR = 0x0U, /**< UART reveive */ 113 ALD_DMA_MSIGSEL_UART_TXEMPTY = 0x1U, /**< UART transmit */ 114 ALD_DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ 115 ALD_DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ 116 ALD_DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ 117 ALD_DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ 118 ALD_DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ 119 ALD_DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ 120 ALD_DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ 121 ALD_DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ 122 ALD_DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ 123 ALD_DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ 124 ALD_DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ 125 ALD_DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ 126 ALD_DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ 127 ALD_DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ 128 ALD_DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ 129 ALD_DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ 130 ALD_DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ 131 ALD_DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ 132 ALD_DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ 133 ALD_DMA_MSIGSEL_BSTIM = 0x0U, /**< BSTIM */ 134 } ald_dma_msigsel_t; 135 136 /** 137 * @brief Priority of DMA channel 138 */ 139 typedef enum 140 { 141 ALD_DMA_LOW_PRIORITY = 0, 142 ALD_DMA_MEDIUM_PRIORITY = 1, 143 ALD_DMA_HIGH_PRIORUTY = 2, 144 ALD_DMA_HIGHEST_PRIORITY = 3 145 } ald_dma_priority_t; 146 147 /** 148 * @brief data increment 149 */ 150 typedef enum 151 { 152 ALD_DMA_DATA_INC_DISABLE = 0x0U, 153 ALD_DMA_DATA_INC_ENABLE = 0x1U, 154 } ald_dma_data_inc_t; 155 156 /** 157 * @brief Data size 158 */ 159 typedef enum { 160 ALD_DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ 161 ALD_DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ 162 ALD_DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ 163 } ald_dma_data_size_t; 164 165 /** 166 * @brief Interrupt flag trigger mode 167 */ 168 typedef enum 169 { 170 ALD_DMA_IT_FLAG_TC = 0x0U, /**< DMA transfer complete interrupt */ 171 ALD_DMA_IT_FLAG_HT = 0x1U, /**< DMA transfer half complete interrupt */ 172 } ald_dma_it_flag_t; 173 174 /** 175 * @brief Control how many DMA transfers can occur 176 * before the controller re-arbitrates 177 */ 178 typedef enum { 179 ALD_DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ 180 ALD_DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ 181 ALD_DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ 182 ALD_DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ 183 ALD_DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ 184 ALD_DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ 185 ALD_DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ 186 ALD_DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ 187 ALD_DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ 188 ALD_DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ 189 ALD_DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ 190 } ald_dma_arbiter_config_t; 191 192 /** 193 * @brief Callback function pointer and param 194 */ 195 typedef struct { 196 void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */ 197 void (*cplt_ht_cbk)(void* arg); /**< DMA transfers half complete callback */ 198 void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */ 199 void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */ 200 } ald_dma_call_back_t; 201 202 /** 203 * @brief DMA channal configure structure 204 */ 205 typedef struct { 206 void *src; /**< Source data begin pointer */ 207 void *dst; /**< Destination data begin pointer */ 208 uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ 209 ald_dma_data_size_t src_data_width; /**< Source data width */ 210 ald_dma_data_size_t dst_data_width; /**< Dest data width */ 211 ald_dma_data_inc_t src_inc; /**< Source increment type */ 212 ald_dma_data_inc_t dst_inc; /**< Destination increment type */ 213 ald_dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates */ 214 ald_dma_priority_t priority; /**< High priority or default priority */ 215 TypeFunc mem_to_mem; /**< Enable/disable memory to memory mode */ 216 TypeFunc circle_mode; /**< Enable/disable circular mode */ 217 ald_dma_msel_t msel; /**< Input source to DMA channel */ 218 ald_dma_msigsel_t msigsel; /**< Input signal to DMA channel */ 219 uint8_t channel; /**< Channel index */ 220 } ald_dma_config_t; 221 222 /** @defgroup ALD_DMA_Public_Constants DMA Public Constants 223 * @{ 224 */ 225 /** 226 * brief ALD_DMA_CHANNEL DMA channel 227 */ 228 #define ALD_DMA_CH_0 0x0U /**< Channel 0 */ 229 #define ALD_DMA_CH_1 0x1U /**< Channel 1 */ 230 #define ALD_DMA_CH_2 0x2U /**< Channel 2 */ 231 #define ALD_DMA_CH_3 0x3U /**< Channel 3 */ 232 #define ALD_DMA_CH_4 0x4U /**< Channel 4 */ 233 #define ALD_DMA_CH_5 0x5U /**< Channel 5 */ 234 #define ALD_DMA_CH_6 0x6U /**< Channel 6 */ 235 /** 236 * @} 237 */ 238 239 /** 240 * @brief DMA handle structure definition 241 */ 242 typedef struct { 243 DMA_TypeDef *perh; /**< DMA registers base address */ 244 ald_dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ 245 void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */ 246 void (*cplt_ht_cbk)(void *arg); /**< DMA transfers half complete callback */ 247 void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */ 248 void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */ 249 } ald_dma_handle_t; 250 251 /** 252 * @} 253 */ 254 255 /** 256 * @defgroup DMA_Private_Macros DMA Private Macros 257 * @{ 258 */ 259 #define IS_DMA_MSEL_TYPE(x) ((x) <= ALD_DMA_MSEL_BS16T) 260 #define IS_DMA_MSIGSEL_TYPE(x) ((x) <= ALD_DMA_MSIGSEL_EXTI_15) 261 #define IS_DMA_DATAINC_TYPE(x) (((x) == ALD_DMA_DATA_INC_DISABLE) || \ 262 ((x) == ALD_DMA_DATA_INC_ENABLE)) 263 #define IS_DMA_DATASIZE_TYPE(x) (((x) == ALD_DMA_DATA_SIZE_BYTE) || \ 264 ((x) == ALD_DMA_DATA_SIZE_HALFWORD) || \ 265 ((x) == ALD_DMA_DATA_SIZE_WORD)) 266 #define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == ALD_DMA_R_POWER_1) || \ 267 ((x) == ALD_DMA_R_POWER_2) || \ 268 ((x) == ALD_DMA_R_POWER_4) || \ 269 ((x) == ALD_DMA_R_POWER_8) || \ 270 ((x) == ALD_DMA_R_POWER_16) || \ 271 ((x) == ALD_DMA_R_POWER_32) || \ 272 ((x) == ALD_DMA_R_POWER_64) || \ 273 ((x) == ALD_DMA_R_POWER_128) || \ 274 ((x) == ALD_DMA_R_POWER_256) || \ 275 ((x) == ALD_DMA_R_POWER_512) || \ 276 ((x) == ALD_DMA_R_POWER_1024)) 277 #define IS_DMA_PRIORITY_TYPE(x) (((x) == ALD_DMA_LOW_PRIORITY) || \ 278 ((x) == ALD_DMA_MEDIUM_PRIORITY) || \ 279 ((x) == ALD_DMA_HIGH_PRIORUTY) || \ 280 ((x) == ALD_DMA_HIGHEST_PRIORITY)) 281 #define IS_DMA_IT_TYPE(x) (((x) == ALD_DMA_IT_FLAG_TC) || \ 282 ((x) == ALD_DMA_IT_FLAG_HT)) 283 #define IS_DMA(x) ((x) == DMA) 284 #define IS_DMA_CHANNEL(x) ((x) <= ALD_DMA_CH_6) 285 #define IS_DMA_DATA_SIZE(x) ((x) <= 65535) 286 /** 287 * @} 288 */ 289 290 /** 291 * @addtogroup DMA_Public_Functions 292 * @{ 293 */ 294 295 /** @addtogroup DMA_Public_Functions_Group1 296 * @{ 297 */ 298 /* Initialization functions */ 299 extern void ald_dma_config_base(ald_dma_config_t *config); 300 extern void ald_dma_config_basic(ald_dma_handle_t *hperh); 301 extern void ald_dma_config_basic_easy(void *src, void *dst, uint16_t size, ald_dma_msel_t msel, 302 ald_dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); 303 extern void ald_dma_irq_handler(void); 304 extern void ald_dma_reset(void); 305 extern void ald_dma_init(void); 306 extern void ald_dma_config_struct(ald_dma_config_t *p); 307 /** 308 * @} 309 */ 310 311 312 /** @addtogroup DMA_Public_Functions_Group2 313 * @{ 314 */ 315 /* DMA control functions */ 316 extern void ald_dma_channel_config(uint8_t channel, type_func_t state); 317 void ald_dma_interrupt_config(uint8_t channel, ald_dma_it_flag_t it, type_func_t state); 318 extern it_status_t ald_dma_get_it_status(uint8_t channel, ald_dma_it_flag_t it); 319 extern flag_status_t ald_dma_get_flag_status(uint8_t channel, ald_dma_it_flag_t it); 320 extern void ald_dma_clear_flag_status(uint8_t channel, ald_dma_it_flag_t it); 321 /** 322 * @} 323 */ 324 325 /** 326 * @} 327 */ 328 329 330 /** 331 * @} 332 */ 333 334 /** 335 * @} 336 */ 337 338 #ifdef __cplusplus 339 } 340 #endif /* __cplusplus */ 341 342 #endif /*__ALD_DMA_H__ */ 343