1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef _FSL_PHY_H_ 31 #define _FSL_PHY_H_ 32 33 #include "fsl_enet.h" 34 35 /*! 36 * @addtogroup phy_driver 37 * @{ 38 */ 39 40 /******************************************************************************* 41 * Definitions 42 ******************************************************************************/ 43 44 /*! @brief PHY driver version */ 45 #define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ 46 47 /*! @brief Defines the PHY registers. */ 48 #define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ 49 #define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ 50 #define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ 51 #define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ 52 #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ 53 #define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ 54 #define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ 55 56 #define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ 57 58 /*! @brief Defines the mask flag in basic control register. */ 59 #define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ 60 #define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ 61 #define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ 62 #define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ 63 #define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ 64 #define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ 65 66 /*!@brief Defines the mask flag of operation mode in control two register*/ 67 #define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ 68 #define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ 69 #define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ 70 #define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ 71 #define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ 72 #define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ 73 74 /*! @brief Defines the mask flag in basic status register. */ 75 #define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ 76 #define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ 77 #define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ 78 79 /*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ 80 #define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ 81 #define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ 82 #define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ 83 #define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ 84 #define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ 85 86 /*! @brief Defines the PHY status. */ 87 enum _phy_status 88 { 89 kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ 90 kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ 91 }; 92 93 /*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ 94 typedef enum _phy_speed 95 { 96 kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ 97 kPHY_Speed100M /*!< ENET PHY 100M speed. */ 98 } phy_speed_t; 99 100 /*! @brief Defines the PHY link duplex. */ 101 typedef enum _phy_duplex 102 { 103 kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ 104 kPHY_FullDuplex /*!< ENET PHY full duplex. */ 105 } phy_duplex_t; 106 107 /*! @brief Defines the PHY loopback mode. */ 108 typedef enum _phy_loop 109 { 110 kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ 111 kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ 112 } phy_loop_t; 113 114 /******************************************************************************* 115 * API 116 ******************************************************************************/ 117 118 #if defined(__cplusplus) 119 extern "C" { 120 #endif 121 122 /*! 123 * @name PHY Driver 124 * @{ 125 */ 126 127 /*! 128 * @brief Initializes PHY. 129 * 130 * This function initialize the SMI interface and initialize PHY. 131 * The SMI is the MII management interface between PHY and MAC, which should be 132 * firstly initialized before any other operation for PHY. 133 * 134 * @param base ENET peripheral base address. 135 * @param phyAddr The PHY address. 136 * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. 137 * @retval kStatus_Success PHY initialize success 138 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 139 * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail 140 */ 141 status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); 142 143 /*! 144 * @brief PHY Write function. This function write data over the SMI to 145 * the specified PHY register. This function is called by all PHY interfaces. 146 * 147 * @param base ENET peripheral base address. 148 * @param phyAddr The PHY address. 149 * @param phyReg The PHY register. 150 * @param data The data written to the PHY register. 151 * @retval kStatus_Success PHY write success 152 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 153 */ 154 status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); 155 156 /*! 157 * @brief PHY Read function. This interface read data over the SMI from the 158 * specified PHY register. This function is called by all PHY interfaces. 159 * 160 * @param base ENET peripheral base address. 161 * @param phyAddr The PHY address. 162 * @param phyReg The PHY register. 163 * @param dataPtr The address to store the data read from the PHY register. 164 * @retval kStatus_Success PHY read success 165 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 166 */ 167 status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); 168 169 /*! 170 * @brief Enables/disables PHY loopback. 171 * 172 * @param base ENET peripheral base address. 173 * @param phyAddr The PHY address. 174 * @param mode The loopback mode to be enabled, please see "phy_loop_t". 175 * the two loopback mode should not be both set. when one loopback mode is set 176 * the other one should be disabled. 177 * @param enable True to enable, false to disable. 178 * @retval kStatus_Success PHY loopback success 179 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 180 */ 181 status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable); 182 183 /*! 184 * @brief Gets the PHY link status. 185 * 186 * @param base ENET peripheral base address. 187 * @param phyAddr The PHY address. 188 * @param status The link up or down status of the PHY. 189 * - true the link is up. 190 * - false the link is down. 191 * @retval kStatus_Success PHY get link status success 192 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 193 */ 194 status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); 195 196 /*! 197 * @brief Gets the PHY link speed and duplex. 198 * 199 * @param base ENET peripheral base address. 200 * @param phyAddr The PHY address. 201 * @param speed The address of PHY link speed. 202 * @param duplex The link duplex of PHY. 203 * @retval kStatus_Success PHY get link speed and duplex success 204 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 205 */ 206 status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); 207 208 /* @} */ 209 210 #if defined(__cplusplus) 211 } 212 #endif 213 214 /*! @}*/ 215 216 #endif /* _FSL_PHY_H_ */ 217