1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "fsl_vref.h"
32
33 /*******************************************************************************
34 * Prototypes
35 ******************************************************************************/
36
37 /*!
38 * @brief Gets the instance from the base address
39 *
40 * @param base VREF peripheral base address
41 *
42 * @return The VREF instance
43 */
44 static uint32_t VREF_GetInstance(VREF_Type *base);
45
46 /*******************************************************************************
47 * Variables
48 ******************************************************************************/
49
50 /*! @brief Pointers to VREF bases for each instance. */
51 static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS;
52
53 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
54 /*! @brief Pointers to VREF clocks for each instance. */
55 static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS;
56 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
57
58 /*******************************************************************************
59 * Code
60 ******************************************************************************/
61
VREF_GetInstance(VREF_Type * base)62 static uint32_t VREF_GetInstance(VREF_Type *base)
63 {
64 uint32_t instance;
65
66 /* Find the instance index from base address mappings. */
67 for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++)
68 {
69 if (s_vrefBases[instance] == base)
70 {
71 break;
72 }
73 }
74
75 assert(instance < ARRAY_SIZE(s_vrefBases));
76
77 return instance;
78 }
79
VREF_Init(VREF_Type * base,const vref_config_t * config)80 void VREF_Init(VREF_Type *base, const vref_config_t *config)
81 {
82 assert(config != NULL);
83
84 uint8_t reg = 0U;
85
86 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
87 /* Ungate clock for VREF */
88 CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
89 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
90
91 /* Configure VREF to a known state */
92 #if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC
93 /* Set chop oscillator bit */
94 base->TRM |= VREF_TRM_CHOPEN_MASK;
95 #endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
96 /* Get current SC register */
97 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
98 reg = base->VREFH_SC;
99 #else
100 reg = base->SC;
101 #endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
102 /* Clear old buffer mode selection bits */
103 reg &= ~VREF_SC_MODE_LV_MASK;
104 /* Set buffer Mode selection and Regulator enable bit */
105 reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U);
106 #if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION
107 /* Set second order curvature compensation enable bit */
108 reg |= VREF_SC_ICOMPEN(1U);
109 #endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */
110 /* Enable VREF module */
111 reg |= VREF_SC_VREFEN(1U);
112 /* Update bit-field from value to Status and Control register */
113 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
114 base->VREFH_SC = reg;
115 #else
116 base->SC = reg;
117 #endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
118 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
119 reg = base->VREFL_TRM;
120 /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */
121 reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK);
122 /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */
123 reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef);
124 base->VREFL_TRM = reg;
125 #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
126
127 #if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
128 reg = base->TRM4;
129 /* Clear old select internal voltage reference bit (2.1V) */
130 reg &= ~VREF_TRM4_VREF2V1_EN_MASK;
131 /* Select internal voltage reference (2.1V) */
132 reg |= VREF_TRM4_VREF2V1_EN(config->enable2V1VoltRef);
133 base->TRM4 = reg;
134 #endif /* FSL_FEATURE_VREF_HAS_TRM4 */
135
136 /* Wait until internal voltage stable */
137 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
138 while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
139 #else
140 while ((base->SC & VREF_SC_VREFST_MASK) == 0)
141 #endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
142 {
143 }
144 }
145
VREF_Deinit(VREF_Type * base)146 void VREF_Deinit(VREF_Type *base)
147 {
148 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
149 /* Gate clock for VREF */
150 CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]);
151 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
152 }
153
VREF_GetDefaultConfig(vref_config_t * config)154 void VREF_GetDefaultConfig(vref_config_t *config)
155 {
156 assert(config);
157
158 /* Set High power buffer mode in */
159 #if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
160 config->bufferMode = kVREF_ModeHighPowerBuffer;
161 #else
162 config->bufferMode = kVREF_ModeTightRegulationBuffer;
163 #endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
164
165 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
166 /* Select internal voltage reference */
167 config->enableExternalVoltRef = false;
168 /* Set VREFL (0.4 V) reference buffer disable */
169 config->enableLowRef = false;
170 #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
171
172 #if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
173 /* Disable internal voltage reference (2.1V) */
174 config->enable2V1VoltRef = false;
175 #endif /* FSL_FEATURE_VREF_HAS_TRM4 */
176 }
177
VREF_SetTrimVal(VREF_Type * base,uint8_t trimValue)178 void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue)
179 {
180 uint8_t reg = 0U;
181
182 /* Set TRIM bits value in voltage reference */
183 reg = base->TRM;
184 reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue));
185 base->TRM = reg;
186 /* Wait until internal voltage stable */
187 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
188 while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
189 #else
190 while ((base->SC & VREF_SC_VREFST_MASK) == 0)
191 #endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
192 {
193 }
194 }
195
196 #if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
VREF_SetTrim2V1Val(VREF_Type * base,uint8_t trimValue)197 void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue)
198 {
199 uint8_t reg = 0U;
200
201 /* Set TRIM bits value in voltage reference (2V1) */
202 reg = base->TRM4;
203 reg = ((reg & ~VREF_TRM4_TRIM2V1_MASK) | VREF_TRM4_TRIM2V1(trimValue));
204 base->TRM4 = reg;
205 /* Wait until internal voltage stable */
206 while ((base->SC & VREF_SC_VREFST_MASK) == 0)
207 {
208 }
209 }
210 #endif /* FSL_FEATURE_VREF_HAS_TRM4 */
211
212 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
VREF_SetLowReferenceTrimVal(VREF_Type * base,uint8_t trimValue)213 void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue)
214 {
215 /* The values 111b and 110b are NOT valid/allowed */
216 assert((trimValue != 0x7U) && (trimValue != 0x6U));
217
218 uint8_t reg = 0U;
219
220 /* Set TRIM bits value in low voltage reference */
221 reg = base->VREFL_TRM;
222 reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue));
223 base->VREFL_TRM = reg;
224 /* Wait until internal voltage stable */
225
226 while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
227 {
228 }
229 }
230 #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
231