1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2021-03-04     Carl    the first version
9  *
10  */
11 
12 #include <rtthread.h>
13 #include "ft_printf.h"
14 #include "ft_assert.h"
15 #include "ft_cpu.h"
16 #include "ft_psci.h"
17 #include "ft_parameters.h"
18 #include "board.h"
19 #include "gtimer.h"
20 #include "ft_generic_timer.h"
21 #include <gicv3.h>
22 
23 #include "interrupt.h"
24 #include <mmu.h>
25 #include "cp15.h"
26 #include "ft2004.h"
27 
28 #define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC)
29 
30 struct mem_desc platform_mem_desc[] = {
31     {0x80000000,
32      0x80000000 + 0x7f000000,
33      0x80000000,
34      DDR_MEM},
35     {0, //< QSPI
36      0x1FFFFFFF,
37      0,
38      DEVICE_MEM},
39     {0x20000000, //<! LPC
40      0x27FFFFFF,
41      0x20000000,
42      DEVICE_MEM},
43     {FT_DEV_BASE_ADDR, //<! Device register
44      FT_DEV_END_ADDR,
45      FT_DEV_BASE_ADDR,
46      DEVICE_MEM},
47     {0x30000000, //<! debug
48      0x39FFFFFF,
49      0x30000000,
50      DEVICE_MEM},
51     {0x3A000000, //<! Internal register space in the on-chip network
52      0x3AFFFFFF,
53      0x3A000000,
54      DEVICE_MEM},
55     {FT_PCI_CONFIG_BASEADDR,
56      FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
57      FT_PCI_CONFIG_BASEADDR,
58      DEVICE_MEM},
59     {FT_PCI_IO_CONFIG_BASEADDR,
60      FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
61      FT_PCI_IO_CONFIG_BASEADDR,
62      DEVICE_MEM},
63     {FT_PCI_MEM32_BASEADDR,
64      FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
65      FT_PCI_MEM32_BASEADDR,
66      DEVICE_MEM},
67 };
68 
69 const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
70 
71 static rt_uint32_t timerStep;
72 
rt_hw_timer_isr(int vector,void * parameter)73 void rt_hw_timer_isr(int vector, void *parameter)
74 {
75     gtimer_set_load_value(timerStep);
76     rt_tick_increase();
77 }
78 
rt_hw_timer_init(void)79 int rt_hw_timer_init(void)
80 {
81     rt_hw_interrupt_install(30, rt_hw_timer_isr, RT_NULL, "tick");
82     rt_hw_interrupt_umask(30);
83     timerStep = gtimer_get_counter_frequency();
84     timerStep /= RT_TICK_PER_SECOND;
85     gtimer_set_load_value(timerStep);
86     gtimer_set_control(1);
87     return 0;
88 }
89 INIT_BOARD_EXPORT(rt_hw_timer_init);
90 
AssertCallback(const char * File,s32 Line)91 static void AssertCallback(const char *File, s32 Line)
92 {
93     Ft_printf("Assert Error is %s : %d \r\n", File, Line);
94 }
95 
96 #ifdef RT_USING_SMP
97 void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
98 #endif
99 
100 /**
101  * This function will initialize hardware board
102  */
rt_hw_board_init(void)103 void rt_hw_board_init(void)
104 {
105     /* bsp debug */
106     FCpu_SpinLockInit();
107     Ft_GenericTimer_Init(0, RT_NULL);
108     Ft_vsprintfRegister((vsprintf_p)rt_vsprintf);
109     Ft_assertSetCallBack((Ft_assertCallback)AssertCallback);
110 
111     /* interrupt init */
112     arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 0, 0);
113 
114 #if RT_CPUS_NR == 2
115     Ft_printf("arm_gic_redist_address_set is 2 \r\n");
116     arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
117 #elif RT_CPUS_NR == 3
118     arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
119     arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 2 * (2U << 16), 2);
120 #elif RT_CPUS_NR == 4
121     arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + (2U << 16), 1);
122     arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 2 * (2U << 16), 2);
123     arm_gic_redist_address_set(0, FT_GICV3_RD_BASEADDRESS + 3 * (2U << 16), 3);
124 #endif
125 
126     rt_hw_interrupt_init();
127 
128     rt_components_board_init();
129     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
130 
131 /* 初始化内存池 */
132 #ifdef RT_USING_HEAP
133     rt_system_heap_init(HEAP_BEGIN, HEAP_END);
134 #endif
135 
136 #ifdef RT_USING_SMP
137     /* install IPI handle */
138     rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
139     rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
140     rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
141 #endif
142 }
143 
ft_reset(void)144 static void ft_reset(void)
145 {
146     FPsci_Reset();
147 }
148 MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
149 
150 /*@}*/
151