1 /** 2 ****************************************************************************** 3 * @file ft32f0xx_adc.h 4 * @author FMD AE 5 * @brief This file contains all the functions prototypes for the ADC firmware 6 * library 7 * @version V1.0.0 8 * @data 2021-07-01 9 ****************************************************************************** 10 */ 11 12 /* Define to prevent recursive inclusion -------------------------------------*/ 13 #ifndef __FT32F0XX_ADC_H 14 #define __FT32F0XX_ADC_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* Includes ------------------------------------------------------------------*/ 21 #include "ft32f0xx.h" 22 23 /** @addtogroup ADC 24 * @{ 25 */ 26 27 /* Exported types ------------------------------------------------------------*/ 28 29 /** 30 * @brief ADC Init structure definition 31 */ 32 33 typedef struct 34 { 35 uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. 36 This parameter can be a value of @ref ADC_Resolution */ 37 38 FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in 39 Continuous or Single mode. 40 This parameter can be set to ENABLE or DISABLE. */ 41 42 uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the 43 trigger of a regular group. This parameter can be a value 44 of @ref ADC_external_trigger_edge_conversion */ 45 46 uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog 47 to digital conversion of regular channels. This parameter 48 can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */ 49 50 uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. 51 This parameter can be a value of @ref ADC_data_align */ 52 53 uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned 54 in the sequence. 55 This parameter can be a value of @ref ADC_Scan_Direction */ 56 }ADC_InitTypeDef; 57 58 59 /* Exported constants --------------------------------------------------------*/ 60 61 /** @defgroup ADC_Exported_Constants 62 * @{ 63 */ 64 #define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) 65 66 /** @defgroup ADC_JitterOff 67 * @{ 68 */ 69 /* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */ 70 #define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2 71 #define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4 72 73 #define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET) 74 75 /** 76 * @} 77 */ 78 79 /** @defgroup ADC_ClockMode 80 * @{ 81 */ 82 #define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */ 83 #define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */ 84 #define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */ 85 #define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\ 86 ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\ 87 ((CLOCK) == ADC_ClockMode_SynClkDiv4)) 88 89 /** 90 * @} 91 */ 92 93 /** @defgroup ADC_Resolution 94 * @{ 95 */ 96 #define ADC_Resolution_12b ((uint32_t)0x00000000) 97 #define ADC_Resolution_10b ADC_CFGR1_RES_0 98 #define ADC_Resolution_8b ADC_CFGR1_RES_1 99 #define ADC_Resolution_6b ADC_CFGR1_RES 100 101 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ 102 ((RESOLUTION) == ADC_Resolution_10b) || \ 103 ((RESOLUTION) == ADC_Resolution_8b) || \ 104 ((RESOLUTION) == ADC_Resolution_6b)) 105 106 /** 107 * @} 108 */ 109 110 /** @defgroup ADC_external_trigger_edge_conversion 111 * @{ 112 */ 113 #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) 114 #define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0 115 #define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1 116 #define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN 117 118 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ 119 ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ 120 ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ 121 ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) 122 /** 123 * @} 124 */ 125 126 /** @defgroup ADC_external_trigger_sources_for_channels_conversion 127 * @{ 128 */ 129 130 /* TIM1 */ 131 #define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) 132 #define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0 133 134 /* TIM2 */ 135 #define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1 136 137 /* TIM3 */ 138 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)) 139 140 /* TIM15 */ 141 #define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2 142 143 #define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \ 144 ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \ 145 ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \ 146 ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \ 147 ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) 148 /** 149 * @} 150 */ 151 152 /** @defgroup ADC_data_align 153 * @{ 154 */ 155 156 #define ADC_DataAlign_Right ((uint32_t)0x00000000) 157 #define ADC_DataAlign_Left ADC_CFGR1_ALIGN 158 159 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ 160 ((ALIGN) == ADC_DataAlign_Left)) 161 /** 162 * @} 163 */ 164 165 /** @defgroup ADC_Scan_Direction 166 * @{ 167 */ 168 169 #define ADC_ScanDirection_Upward ((uint32_t)0x00000000) 170 #define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR 171 172 #define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \ 173 ((DIRECTION) == ADC_ScanDirection_Backward)) 174 /** 175 * @} 176 */ 177 178 /** @defgroup ADC_DMA_Mode 179 * @{ 180 */ 181 182 #define ADC_DMAMode_OneShot ((uint32_t)0x00000000) 183 #define ADC_DMAMode_Circular ADC_CFGR1_DMACFG 184 185 #define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \ 186 ((MODE) == ADC_DMAMode_Circular)) 187 /** 188 * @} 189 */ 190 191 /** @defgroup ADC_analog_watchdog_selection 192 * @{ 193 */ 194 195 #define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000) 196 #define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000) 197 #define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000) 198 #define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000) 199 #define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000) 200 #define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000) 201 #define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000) 202 #define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000) 203 #define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000) 204 #define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000) 205 #define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) 206 #define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) 207 #define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) 208 #define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) 209 #define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) 210 #define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) 211 #define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000) 212 #define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000) 213 #define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000) 214 215 216 #define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ 217 ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \ 218 ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \ 219 ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \ 220 ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \ 221 ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \ 222 ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \ 223 ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \ 224 ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \ 225 ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \ 226 ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \ 227 ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \ 228 ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \ 229 ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \ 230 ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \ 231 ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \ 232 ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \ 233 ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \ 234 ((CHANNEL) == ADC_AnalogWatchdog_Channel_18)) 235 /** 236 * @} 237 */ 238 239 /** @defgroup ADC_sampling_times 240 * @{ 241 */ 242 243 #define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) 244 #define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) 245 #define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) 246 #define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) 247 #define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) 248 #define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) 249 #define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) 250 #define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) 251 252 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \ 253 ((TIME) == ADC_SampleTime_7_5Cycles) || \ 254 ((TIME) == ADC_SampleTime_13_5Cycles) || \ 255 ((TIME) == ADC_SampleTime_28_5Cycles) || \ 256 ((TIME) == ADC_SampleTime_41_5Cycles) || \ 257 ((TIME) == ADC_SampleTime_55_5Cycles) || \ 258 ((TIME) == ADC_SampleTime_71_5Cycles) || \ 259 ((TIME) == ADC_SampleTime_239_5Cycles)) 260 /** 261 * @} 262 */ 263 264 /** @defgroup ADC_thresholds 265 * @{ 266 */ 267 268 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) 269 270 /** 271 * @} 272 */ 273 274 /** @defgroup ADC_channels 275 * @{ 276 */ 277 278 #define ADC_Channel_0 ADC_CHSELR_CHSEL0 279 #define ADC_Channel_1 ADC_CHSELR_CHSEL1 280 #define ADC_Channel_2 ADC_CHSELR_CHSEL2 281 #define ADC_Channel_3 ADC_CHSELR_CHSEL3 282 #define ADC_Channel_4 ADC_CHSELR_CHSEL4 283 #define ADC_Channel_5 ADC_CHSELR_CHSEL5 284 #define ADC_Channel_6 ADC_CHSELR_CHSEL6 285 #define ADC_Channel_7 ADC_CHSELR_CHSEL7 286 #define ADC_Channel_8 ADC_CHSELR_CHSEL8 287 #define ADC_Channel_9 ADC_CHSELR_CHSEL9 288 #define ADC_Channel_10 ADC_CHSELR_CHSEL10 289 #define ADC_Channel_11 ADC_CHSELR_CHSEL11 290 #define ADC_Channel_12 ADC_CHSELR_CHSEL12 291 #define ADC_Channel_13 ADC_CHSELR_CHSEL13 292 #define ADC_Channel_14 ADC_CHSELR_CHSEL14 293 #define ADC_Channel_15 ADC_CHSELR_CHSEL15 294 #define ADC_Channel_16 ADC_CHSELR_CHSEL16 295 #define ADC_Channel_17 ADC_CHSELR_CHSEL17 296 #define ADC_Channel_18 ADC_CHSELR_CHSEL18 297 #define ADC_Channel_19 ADC_CHSELR_CHSEL19 298 #define ADC_Channel_20 ADC_CHSELR_CHSEL20 299 #define ADC_Channel_21 ADC_CHSELR_CHSEL21 300 301 #define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16) 302 #define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17) 303 #if defined (FT32F072xB) 304 #define ADC_Channel_OP1 ((uint32_t)ADC_Channel_18) 305 #define ADC_Channel_OP2 ((uint32_t)ADC_Channel_19) 306 #define ADC_Channel_IOSH1 ((uint32_t)ADC_Channel_20) 307 #define ADC_Channel_IOSH2 ((uint32_t)ADC_Channel_21) 308 309 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFC00000) == (uint32_t)RESET)) 310 311 #else 312 #define ADC_Channel_IOSH ((uint32_t)ADC_Channel_18) 313 #define ADC_Channel_OP ((uint32_t)ADC_Channel_19) 314 315 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF00000) == (uint32_t)RESET)) 316 317 #endif 318 319 320 321 #if defined (FT32F072xB) 322 /** 323 * @}ADC_IOSH1_SMPSEL 324 */ 325 #define ADC_IOSH1_SMPSEL_PB1 ((uint32_t)0x00000000) 326 #define ADC_IOSH1_SMPSEL_OP1OUT ((uint32_t)0x00000400) 327 328 #define ADC_IOSH2_SMPSEL_PB0 ((uint32_t)0x00000000) 329 #define ADC_IOSH2_SMPSEL_OP2OUT ((uint32_t)0x00004000) 330 331 #define IS_ADC_SMPSEL(SEL) ( ((SEL) == ADC_IOSH2_SMPSEL_PB1) || \ 332 ((SEL) == ADC_IOSH2_SMPSEL_OP1OUT) || \ 333 ((SEL) == ADC_IOSH1_SMPSEL_OP2OUT) ) 334 /** 335 * @}IS_ADC_SMPEN 336 */ 337 #define ADC_IOSH1_SMPEN ((uint32_t)0x00000200) 338 #define ADC_IOSH2_SMPEN ((uint32_t)0x00002000) 339 340 #define IS_ADC_SMPEN(SMPEN) ( ((SMPEN) == ADC_IOSH1_SMPEN) || \ 341 ((SMPEN) == ADC_IOSH2_SMPEN) ) 342 /** 343 * @}IS_ADC_SMPMOD 344 */ 345 #define IS_ADC_SMPMOD(SMPMOD) ( ((SMPMOD) == ADC_CR2_IOSH1_SMPMOD) || \ 346 ((SMPMOD) == ADC_CR2_IOSH2_SMPMOD) ) 347 348 #define ADC_SMP_SOFTWARE_MODE ((uint32_t)0x00000000) 349 #define ADC_SMP_HARDWARE_MODE ((uint32_t)0x00000001) 350 351 #define IS_ADC_MODE(MODE) ( ((MODE) == ADC_SMP_SOFTWARE_MODE) || \ 352 ((MODE) == ADC_SMP_HARDWARE_MODE) ) 353 354 /** 355 * @}IS_ADC_AMPEN 356 */ 357 #define ADC_IOSH1_AMPEN ((uint32_t)0x00000100) 358 #define ADC_IOSH2_AMPEN ((uint32_t)0x00001000) 359 360 #define IS_ADC_AMPEN(AMPEN) ( ((AMPEN) == ADC_IOSH1_AMPEN) || \ 361 ((AMPEN) == ADC_IOSH2_AMPEN) ) 362 /** 363 * @}IS_ADC_EXTDLY 364 */ 365 #define IS_ADC_EXTDLY(EXTDLY) ( ((EXTDLY) >=0 ) && ((EXTDLY) <= 0x000003FF)) 366 367 /** 368 * @}IS_ADC_RTEN 369 */ 370 #define IS_ADC_RTEN(RTEN) ( ((RTEN) == ADC_RTENR_RTEN) || \ 371 ((RTEN) == ADC_RTENR_RTEN_0) || \ 372 ((RTEN) == ADC_RTENR_RTEN_1) || \ 373 ((RTEN) == ADC_RTENR_RTEN_2) || \ 374 ((RTEN) == ADC_RTENR_RTEN_3) || \ 375 ((RTEN) == ADC_RTENR_RTEN_4) || \ 376 ((RTEN) == ADC_RTENR_RTEN_5) || \ 377 ((RTEN) == ADC_RTENR_RTEN_6) || \ 378 ((RTEN) == ADC_RTENR_RTEN_7) || \ 379 ((RTEN) == ADC_RTENR_RTEN_8) || \ 380 ((RTEN) == ADC_RTENR_RTEN_9) || \ 381 ((RTEN) == ADC_RTENR_RTEN_10) || \ 382 ((RTEN) == ADC_RTENR_RTEN_11) || \ 383 ((RTEN) == ADC_RTENR_RTEN_12) || \ 384 ((RTEN) == ADC_RTENR_RTEN_13) || \ 385 ((RTEN) == ADC_RTENR_RTEN_14) || \ 386 ((RTEN) == ADC_RTENR_RTEN_15) || \ 387 ((RTEN) == ADC_RTENR_RTEN_16) || \ 388 ((RTEN) == ADC_RTENR_RTEN_17) || \ 389 ((RTEN) == ADC_RTENR_RTEN_18) ) 390 391 /** 392 * @}IS_ADC_FTEN 393 */ 394 #define IS_ADC_FTEN(FTEN) ( ((FTEN) == ADC_FTENR_FTEN) || \ 395 ((FTEN) == ADC_FTENR_FTEN_0) || \ 396 ((FTEN) == ADC_FTENR_FTEN_1) || \ 397 ((FTEN) == ADC_FTENR_FTEN_2) || \ 398 ((FTEN) == ADC_FTENR_FTEN_3) || \ 399 ((FTEN) == ADC_FTENR_FTEN_4) || \ 400 ((FTEN) == ADC_FTENR_FTEN_5) || \ 401 ((FTEN) == ADC_FTENR_FTEN_6) || \ 402 ((FTEN) == ADC_FTENR_FTEN_7) || \ 403 ((FTEN) == ADC_FTENR_FTEN_8) || \ 404 ((FTEN) == ADC_FTENR_FTEN_9) || \ 405 ((FTEN) == ADC_FTENR_FTEN_10) || \ 406 ((FTEN) == ADC_FTENR_FTEN_11) || \ 407 ((FTEN) == ADC_FTENR_FTEN_12) || \ 408 ((FTEN) == ADC_FTENR_FTEN_13) || \ 409 ((FTEN) == ADC_FTENR_FTEN_14) || \ 410 ((FTEN) == ADC_FTENR_FTEN_15) || \ 411 ((FTEN) == ADC_FTENR_FTEN_16) || \ 412 ((FTEN) == ADC_FTENR_FTEN_17) || \ 413 ((FTEN) == ADC_FTENR_FTEN_18)) 414 415 #else 416 /** 417 * @}IS_ADC_AMPEN 418 */ 419 #define ADC_IOSH1_AMPEN ((uint32_t)0x00000100) 420 #define ADC_IOSH_AMPEN ADC_IOSH1_AMPEN 421 422 #define IS_ADC_AMPEN(AMPEN) ( ((AMPEN) == ADC_IOSH1_AMPEN)) 423 424 /** 425 * @}IS_ADC_SMPEN 426 */ 427 #define ADC_IOSH1_SMPEN ((uint32_t)0x00000200) 428 #define ADC_IOSH_SMPEN ADC_IOSH1_SMPEN 429 430 #define IS_ADC_SMPEN(SMPEN) ( ((SMPEN) == ADC_IOSH1_SMPEN) ) 431 432 #endif 433 434 435 /** 436 * @} 437 */ 438 439 /** @defgroup ADC_interrupts_definition 440 * @{ 441 */ 442 443 #define ADC_IT_ADRDY ADC_IER_ADRDYIE 444 #define ADC_IT_EOSMP ADC_IER_EOSMPIE 445 #define ADC_IT_EOC ADC_IER_EOCIE 446 #define ADC_IT_EOSEQ ADC_IER_EOSEQIE 447 #define ADC_IT_OVR ADC_IER_OVRIE 448 #define ADC_IT_AWD ADC_IER_AWDIE 449 450 #define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) 451 452 #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \ 453 ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \ 454 ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD)) 455 456 #define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) 457 458 /** 459 * @} 460 */ 461 462 /** @defgroup ADC_flags_definition 463 * @{ 464 */ 465 466 #define ADC_FLAG_ADRDY ADC_ISR_ADRDY 467 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP 468 #define ADC_FLAG_EOC ADC_ISR_EOC 469 #define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ 470 #define ADC_FLAG_OVR ADC_ISR_OVR 471 #define ADC_FLAG_AWD ADC_ISR_AWD 472 473 #define ADC_FLAG_ADEN ((uint32_t)0x01000001) 474 #define ADC_FLAG_ADDIS ((uint32_t)0x01000002) 475 #define ADC_FLAG_ADSTART ((uint32_t)0x01000004) 476 #define ADC_FLAG_ADSTP ((uint32_t)0x01000010) 477 #define ADC_FLAG_ADCAL ((uint32_t)0x81000000) 478 479 #define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET)) 480 481 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ 482 ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \ 483 ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \ 484 ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \ 485 ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \ 486 ((FLAG) == ADC_FLAG_ADCAL)) 487 488 489 490 491 492 #define ADC_Vrefsel_0_625V ((uint32_t)0x00000002) 493 #define ADC_Vrefsel_1_5V ((uint32_t)0x00000006) 494 #define ADC_Vrefsel_2_5V ((uint32_t)0x0000000A) 495 #define ADC_Vrefsel_VDDA ((uint32_t)(~(uint32_t)0x0000000E)) 496 #define IS_ADC_Vrefsel(Vref) ( ( (Vref) == ADC_Vrefsel_0_625V) || \ 497 ( (Vref) == ADC_Vrefsel_1_5V ) || \ 498 ( (Vref) == ADC_Vrefsel_2_5V ) || \ 499 ( (Vref) == ADC_Vrefsel_VDDA ) ) 500 501 #define ADC_VrefEN ((uint32_t)0x00000002) 502 503 504 /** 505 * @} 506 */ 507 508 /** 509 * @} 510 */ 511 512 /* Exported macro ------------------------------------------------------------*/ 513 /* Exported functions ------------------------------------------------------- */ 514 515 /* Function used to set the ADC configuration to the default reset state *****/ 516 void ADC_DeInit(ADC_TypeDef* ADCx); 517 518 /* Initialization and Configuration functions *********************************/ 519 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); 520 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); 521 void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode); 522 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); 523 /* This Function is obsolete and maintained for legacy purpose only. 524 ADC_ClockModeConfig() function should be used instead */ 525 void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState); 526 527 /* Power saving functions *****************************************************/ 528 void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 529 void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 530 531 /* Analog Watchdog configuration functions ************************************/ 532 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 533 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); 534 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel); 535 void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 536 537 /* Temperature Sensor , Vrefint and Vbat management function ... ******************/ 538 void ADC_TempSensorCmd(FunctionalState NewState); 539 void ADC_VrefintCmd(FunctionalState NewState); 540 void ADC_VbatCmd(FunctionalState NewState); 541 void ADC_VrefDecibCmd(FunctionalState NewState); 542 void ADC_IoshSmpCmd(uint32_t SmpEn, FunctionalState NewState); 543 void ADC_IoshAmpCmd(uint32_t AmpEn, FunctionalState NewState); 544 545 /* Channels Configuration functions *******************************************/ 546 void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime); 547 void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 548 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 549 void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 550 uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx); 551 void ADC_StopOfConversion(ADC_TypeDef* ADCx); 552 void ADC_StartOfConversion(ADC_TypeDef* ADCx); 553 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); 554 555 #if defined (FT32F072xB) 556 void ADC_IoshSmpSel(uint32_t Ioshx, uint32_t SmpSel); 557 void ADC_IoshSmpMod(uint32_t SmpModBit, uint32_t Mode); 558 void ADC_ExtModeCmd(FunctionalState NewState); 559 void ADC_TrgdDisSmpCmd(FunctionalState NewState); 560 void ADC_ExtDlyConfig(uint32_t ExtDly); 561 void ADC_RtenCmd(uint32_t Rtenx, FunctionalState NewState); 562 void ADC_FtenCmd(uint32_t Ftenx, FunctionalState NewState); 563 564 #endif 565 566 567 /* Regular Channels DMA Configuration functions *******************************/ 568 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); 569 void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode); 570 571 /* Interrupts and flags management functions **********************************/ 572 void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); 573 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); 574 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); 575 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); 576 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); 577 void ADC_VrefselConfig(uint32_t ADC_Vrefsel); 578 #ifdef __cplusplus 579 } 580 #endif 581 582 #endif /*__ft32F0XX_ADC_H */ 583 584 /** 585 * @} 586 */ 587 588 /** 589 * @} 590 */ 591 592 /************************ (C) COPYRIGHT FMD *****END OF FILE****/ 593