1 /** 2 ****************************************************************************** 3 * @file ft32f0xx_dma.h 4 * @author FMD AE 5 * @brief This file contains all the functions prototypes for the DMA firmware 6 * library. 7 * @version V1.0.0 8 * @data 2021-07-01 9 ****************************************************************************** 10 */ 11 12 /* Define to prevent recursive inclusion -------------------------------------*/ 13 #ifndef __FT32F0XX_DMA_H 14 #define __FT32F0XX_DMA_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* Includes ------------------------------------------------------------------*/ 21 #include "ft32f0xx.h" 22 23 24 /** @addtogroup DMA 25 * @{ 26 */ 27 /* Exported types ------------------------------------------------------------*/ 28 29 /** 30 * @brief DMA Init structures definition 31 */ 32 typedef struct 33 { 34 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ 35 36 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ 37 38 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. 39 This parameter can be a value of @ref DMA_data_transfer_direction */ 40 41 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. 42 The data unit is equal to the configuration set in DMA_PeripheralDataSize 43 or DMA_MemoryDataSize members depending in the transfer direction */ 44 45 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. 46 This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 47 48 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. 49 This parameter can be a value of @ref DMA_memory_incremented_mode */ 50 51 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. 52 This parameter can be a value of @ref DMA_peripheral_data_size */ 53 54 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. 55 This parameter can be a value of @ref DMA_memory_data_size */ 56 57 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. 58 This parameter can be a value of @ref DMA_circular_normal_mode 59 @note: The circular buffer mode cannot be used if the memory-to-memory 60 data transfer is configured on the selected Channel */ 61 62 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. 63 This parameter can be a value of @ref DMA_priority_level */ 64 65 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. 66 This parameter can be a value of @ref DMA_memory_to_memory */ 67 }DMA_InitTypeDef; 68 69 /* Exported constants --------------------------------------------------------*/ 70 71 /** @defgroup DMA_Exported_Constants 72 * @{ 73 */ 74 75 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ 76 ((PERIPH) == DMA1_Channel2) || \ 77 ((PERIPH) == DMA1_Channel3) || \ 78 ((PERIPH) == DMA1_Channel4) || \ 79 ((PERIPH) == DMA1_Channel5) || \ 80 ((PERIPH) == DMA1_Channel6) || \ 81 ((PERIPH) == DMA1_Channel7) || \ 82 ((PERIPH) == DMA2_Channel1) || \ 83 ((PERIPH) == DMA2_Channel2) || \ 84 ((PERIPH) == DMA2_Channel3) || \ 85 ((PERIPH) == DMA2_Channel4) || \ 86 ((PERIPH) == DMA2_Channel5)) 87 88 /** @defgroup DMA_data_transfer_direction 89 * @{ 90 */ 91 92 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) 93 #define DMA_DIR_PeripheralDST DMA_CCR_DIR 94 95 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ 96 ((DIR) == DMA_DIR_PeripheralDST)) 97 /** 98 * @} 99 */ 100 101 /** @defgroup DMA_peripheral_incremented_mode 102 * @{ 103 */ 104 105 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 106 #define DMA_PeripheralInc_Enable DMA_CCR_PINC 107 108 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ 109 ((STATE) == DMA_PeripheralInc_Enable)) 110 /** 111 * @} 112 */ 113 114 /** @defgroup DMA_memory_incremented_mode 115 * @{ 116 */ 117 118 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 119 #define DMA_MemoryInc_Enable DMA_CCR_MINC 120 121 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ 122 ((STATE) == DMA_MemoryInc_Enable)) 123 /** 124 * @} 125 */ 126 127 /** @defgroup DMA_peripheral_data_size 128 * @{ 129 */ 130 131 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 132 #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 133 #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 134 135 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ 136 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ 137 ((SIZE) == DMA_PeripheralDataSize_Word)) 138 /** 139 * @} 140 */ 141 142 /** @defgroup DMA_memory_data_size 143 * @{ 144 */ 145 146 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 147 #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 148 #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 149 150 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ 151 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ 152 ((SIZE) == DMA_MemoryDataSize_Word)) 153 /** 154 * @} 155 */ 156 157 /** @defgroup DMA_circular_normal_mode 158 * @{ 159 */ 160 161 #define DMA_Mode_Normal ((uint32_t)0x00000000) 162 #define DMA_Mode_Circular DMA_CCR_CIRC 163 164 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) 165 /** 166 * @} 167 */ 168 169 /** @defgroup DMA_priority_level 170 * @{ 171 */ 172 173 #define DMA_Priority_VeryHigh DMA_CCR_PL 174 #define DMA_Priority_High DMA_CCR_PL_1 175 #define DMA_Priority_Medium DMA_CCR_PL_0 176 #define DMA_Priority_Low ((uint32_t)0x00000000) 177 178 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ 179 ((PRIORITY) == DMA_Priority_High) || \ 180 ((PRIORITY) == DMA_Priority_Medium) || \ 181 ((PRIORITY) == DMA_Priority_Low)) 182 /** 183 * @} 184 */ 185 186 /** @defgroup DMA_memory_to_memory 187 * @{ 188 */ 189 190 #define DMA_M2M_Disable ((uint32_t)0x00000000) 191 #define DMA_M2M_Enable DMA_CCR_MEM2MEM 192 193 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) 194 195 /** 196 * @} 197 */ 198 199 /** @defgroup DMA_Remap_Config 200 * @{ 201 */ 202 #define DMAx_CHANNEL1_RMP 0x00000000 203 #define DMAx_CHANNEL2_RMP 0x10000000 204 #define DMAx_CHANNEL3_RMP 0x20000000 205 #define DMAx_CHANNEL4_RMP 0x30000000 206 #define DMAx_CHANNEL5_RMP 0x40000000 207 #define DMAx_CHANNEL6_RMP 0x50000000 208 #define DMAx_CHANNEL7_RMP 0x60000000 209 210 211 #define IS_DMA_ALL_LIST(LIST) (((LIST) == DMA1) || \ 212 ((LIST) == DMA2)) 213 214 /****************** DMA1 remap bit field definition********************/ 215 /* DMA1 - Channel 1 */ 216 #define DMA1_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ 217 #define DMA1_CH1_ADC (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ 218 #define DMA1_CH1_TIM17_CH1 (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ 219 #define DMA1_CH1_TIM17_UP (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ 220 #define DMA1_CH1_USART1_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ 221 #define DMA1_CH1_USART2_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ 222 #define DMA1_CH1_USART3_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ 223 #define DMA1_CH1_USART4_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ 224 #define DMA1_CH1_USART5_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ 225 #define DMA1_CH1_USART6_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ 226 #define DMA1_CH1_USART7_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ 227 #define DMA1_CH1_USART8_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ 228 /* DMA1 - Channel 2 */ 229 #define DMA1_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ 230 #define DMA1_CH2_ADC (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ 231 #define DMA1_CH2_I2C1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ 232 #define DMA1_CH2_SPI1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI_1RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ 233 #define DMA1_CH2_TIM1_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ 234 #define DMA1_CH2_TIM17_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ 235 #define DMA1_CH2_TIM17_UP (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ 236 #define DMA1_CH2_USART1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ 237 #define DMA1_CH2_USART2_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ 238 #define DMA1_CH2_USART3_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ 239 #define DMA1_CH2_USART4_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ 240 #define DMA1_CH2_USART5_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ 241 #define DMA1_CH2_USART6_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ 242 #define DMA1_CH2_USART7_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ 243 #define DMA1_CH2_USART8_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ 244 /* DMA1 - Channel 3 */ 245 #define DMA1_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMAx */ 246 #define DMA1_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ 247 #define DMA1_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ 248 #define DMA1_CH3_I2C1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ 249 #define DMA1_CH3_SPI1_TX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ 250 #define DMA1_CH3_TIM1_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ 251 #define DMA1_CH3_TIM2_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ 252 #define DMA1_CH3_TIM16_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ 253 #define DMA1_CH3_TIM16_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ 254 #define DMA1_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ 255 #define DMA1_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ 256 #define DMA1_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ 257 #define DMA1_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ 258 #define DMA1_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ 259 #define DMA1_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ 260 #define DMA1_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ 261 #define DMA1_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ 262 /* DMA1 - Channel 4 */ 263 #define DMA1_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ 264 #define DMA1_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ 265 #define DMA1_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ 266 #define DMA1_CH4_I2C2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ 267 #define DMA1_CH4_SPI2_RX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ 268 #define DMA1_CH4_TIM2_CH4 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ 269 #define DMA1_CH4_TIM3_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ 270 #define DMA1_CH4_TIM3_TRIG (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ 271 #define DMA1_CH4_TIM16_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ 272 #define DMA1_CH4_TIM16_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ 273 #define DMA1_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ 274 #define DMA1_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ 275 #define DMA1_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ 276 #define DMA1_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ 277 #define DMA1_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ 278 #define DMA1_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ 279 #define DMA1_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ 280 #define DMA1_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ 281 /* DMA1 - Channel 5 */ 282 #define DMA1_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ 283 #define DMA1_CH5_I2C2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ 284 #define DMA1_CH5_SPI2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ 285 #define DMA1_CH5_TIM1_CH3 (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ 286 #define DMA1_CH5_USART1_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ 287 #define DMA1_CH5_USART2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ 288 #define DMA1_CH5_USART3_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ 289 #define DMA1_CH5_USART4_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ 290 #define DMA1_CH5_USART5_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ 291 #define DMA1_CH5_USART6_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ 292 #define DMA1_CH5_USART7_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ 293 #define DMA1_CH5_USART8_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ 294 /* DMA1 - Channel 6 */ 295 #define DMA1_CH6_DEFAULT (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ 296 #define DMA1_CH6_I2C1_TX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ 297 #define DMA1_CH6_SPI2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ 298 #define DMA1_CH6_TIM1_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ 299 #define DMA1_CH6_TIM1_CH2 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ 300 #define DMA1_CH6_TIM1_CH3 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ 301 #define DMA1_CH6_TIM3_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ 302 #define DMA1_CH6_TIM3_TRIG (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ 303 #define DMA1_CH6_TIM16_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ 304 #define DMA1_CH6_TIM16_UP (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ 305 #define DMA1_CH6_USART1_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ 306 #define DMA1_CH6_USART2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ 307 #define DMA1_CH6_USART3_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ 308 #define DMA1_CH6_USART4_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ 309 #define DMA1_CH6_USART5_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ 310 #define DMA1_CH6_USART6_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ 311 #define DMA1_CH6_USART7_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ 312 #define DMA1_CH6_USART8_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ 313 /* DMA1 - Channel 7 */ 314 #define DMA1_CH7_DEFAULT (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ 315 #define DMA1_CH7_I2C1_RX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ 316 #define DMA1_CH7_SPI2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ 317 #define DMA1_CH7_TIM2_CH2 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ 318 #define DMA1_CH7_TIM2_CH4 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ 319 #define DMA1_CH7_TIM17_CH1 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ 320 #define DMA1_CH7_TIM17_UP (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ 321 #define DMA1_CH7_USART1_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ 322 #define DMA1_CH7_USART2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ 323 #define DMA1_CH7_USART3_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ 324 #define DMA1_CH7_USART4_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ 325 #define DMA1_CH7_USART5_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ 326 #define DMA1_CH7_USART6_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ 327 #define DMA1_CH7_USART7_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ 328 #define DMA1_CH7_USART8_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ 329 330 #define IS_DMA1_REMAP(REMAP) ((REMAP == DMA1_CH1_DEFAULT) ||\ 331 (REMAP == DMA1_CH1_ADC) ||\ 332 (REMAP == DMA1_CH1_TIM17_CH1) ||\ 333 (REMAP == DMA1_CH1_TIM17_UP) ||\ 334 (REMAP == DMA1_CH1_USART1_RX) ||\ 335 (REMAP == DMA1_CH1_USART2_RX) ||\ 336 (REMAP == DMA1_CH1_USART3_RX) ||\ 337 (REMAP == DMA1_CH1_USART4_RX) ||\ 338 (REMAP == DMA1_CH1_USART5_RX) ||\ 339 (REMAP == DMA1_CH1_USART6_RX) ||\ 340 (REMAP == DMA1_CH1_USART7_RX) ||\ 341 (REMAP == DMA1_CH1_USART8_RX) ||\ 342 (REMAP == DMA1_CH2_DEFAULT) ||\ 343 (REMAP == DMA1_CH2_ADC) ||\ 344 (REMAP == DMA1_CH2_I2C1_TX) ||\ 345 (REMAP == DMA1_CH2_SPI1_RX) ||\ 346 (REMAP == DMA1_CH2_TIM1_CH1) ||\ 347 (REMAP == DMA1_CH2_I2C1_TX) ||\ 348 (REMAP == DMA1_CH2_TIM17_CH1) ||\ 349 (REMAP == DMA1_CH2_TIM17_UP) ||\ 350 (REMAP == DMA1_CH2_USART1_TX) ||\ 351 (REMAP == DMA1_CH2_USART2_TX) ||\ 352 (REMAP == DMA1_CH2_USART3_TX) ||\ 353 (REMAP == DMA1_CH2_USART4_TX) ||\ 354 (REMAP == DMA1_CH2_USART5_TX) ||\ 355 (REMAP == DMA1_CH2_USART6_TX) ||\ 356 (REMAP == DMA1_CH2_USART7_TX) ||\ 357 (REMAP == DMA1_CH2_USART8_TX) ||\ 358 (REMAP == DMA1_CH3_DEFAULT) ||\ 359 (REMAP == DMA1_CH3_TIM6_UP) ||\ 360 (REMAP == DMA1_CH3_DAC_CH1) ||\ 361 (REMAP == DMA1_CH3_I2C1_RX) ||\ 362 (REMAP == DMA1_CH3_SPI1_TX) ||\ 363 (REMAP == DMA1_CH3_TIM1_CH2) ||\ 364 (REMAP == DMA1_CH3_TIM2_CH2) ||\ 365 (REMAP == DMA1_CH3_TIM16_CH1) ||\ 366 (REMAP == DMA1_CH3_TIM16_UP) ||\ 367 (REMAP == DMA1_CH3_USART1_RX) ||\ 368 (REMAP == DMA1_CH3_USART2_RX) ||\ 369 (REMAP == DMA1_CH3_USART3_RX) ||\ 370 (REMAP == DMA1_CH3_USART4_RX) ||\ 371 (REMAP == DMA1_CH3_USART5_RX) ||\ 372 (REMAP == DMA1_CH3_USART6_RX) ||\ 373 (REMAP == DMA1_CH3_USART7_RX) ||\ 374 (REMAP == DMA1_CH3_USART8_RX) ||\ 375 (REMAP == DMA1_CH4_DEFAULT) ||\ 376 (REMAP == DMA1_CH4_TIM7_UP) ||\ 377 (REMAP == DMA1_CH4_DAC_CH2) ||\ 378 (REMAP == DMA1_CH4_I2C2_TX) ||\ 379 (REMAP == DMA1_CH4_SPI2_RX) ||\ 380 (REMAP == DMA1_CH4_TIM2_CH4) ||\ 381 (REMAP == DMA1_CH4_TIM3_CH1) ||\ 382 (REMAP == DMA1_CH4_TIM3_TRIG) ||\ 383 (REMAP == DMA1_CH4_TIM16_CH1) ||\ 384 (REMAP == DMA1_CH4_TIM16_UP) ||\ 385 (REMAP == DMA1_CH4_USART1_TX) ||\ 386 (REMAP == DMA1_CH4_USART2_TX) ||\ 387 (REMAP == DMA1_CH4_USART3_TX) ||\ 388 (REMAP == DMA1_CH4_USART4_TX) ||\ 389 (REMAP == DMA1_CH4_USART5_TX) ||\ 390 (REMAP == DMA1_CH4_USART6_TX) ||\ 391 (REMAP == DMA1_CH4_USART7_TX) ||\ 392 (REMAP == DMA1_CH4_USART8_TX) ||\ 393 (REMAP == DMA1_CH5_DEFAULT) ||\ 394 (REMAP == DMA1_CH5_I2C2_RX) ||\ 395 (REMAP == DMA1_CH5_SPI2_TX) ||\ 396 (REMAP == DMA1_CH5_TIM1_CH3) ||\ 397 (REMAP == DMA1_CH5_USART1_RX) ||\ 398 (REMAP == DMA1_CH5_USART2_RX) ||\ 399 (REMAP == DMA1_CH5_USART3_RX) ||\ 400 (REMAP == DMA1_CH5_USART4_RX) ||\ 401 (REMAP == DMA1_CH5_USART5_RX) ||\ 402 (REMAP == DMA1_CH5_USART6_RX) ||\ 403 (REMAP == DMA1_CH5_USART7_RX) ||\ 404 (REMAP == DMA1_CH5_USART8_RX) ||\ 405 (REMAP == DMA1_CH6_DEFAULT) ||\ 406 (REMAP == DMA1_CH6_I2C1_TX) ||\ 407 (REMAP == DMA1_CH6_SPI2_RX) ||\ 408 (REMAP == DMA1_CH6_TIM1_CH1) ||\ 409 (REMAP == DMA1_CH6_TIM1_CH2) ||\ 410 (REMAP == DMA1_CH6_TIM1_CH3) ||\ 411 (REMAP == DMA1_CH6_TIM3_CH1) ||\ 412 (REMAP == DMA1_CH6_TIM3_TRIG) ||\ 413 (REMAP == DMA1_CH6_TIM16_CH1) ||\ 414 (REMAP == DMA1_CH6_TIM16_UP) ||\ 415 (REMAP == DMA1_CH6_USART1_RX) ||\ 416 (REMAP == DMA1_CH6_USART2_RX) ||\ 417 (REMAP == DMA1_CH6_USART3_RX) ||\ 418 (REMAP == DMA1_CH6_USART4_RX) ||\ 419 (REMAP == DMA1_CH6_USART5_RX) ||\ 420 (REMAP == DMA1_CH6_USART6_RX) ||\ 421 (REMAP == DMA1_CH6_USART7_RX) ||\ 422 (REMAP == DMA1_CH6_USART8_RX) ||\ 423 (REMAP == DMA1_CH7_DEFAULT) ||\ 424 (REMAP == DMA1_CH7_I2C1_RX) ||\ 425 (REMAP == DMA1_CH7_SPI2_TX) ||\ 426 (REMAP == DMA1_CH7_TIM2_CH2) ||\ 427 (REMAP == DMA1_CH7_TIM2_CH4) ||\ 428 (REMAP == DMA1_CH7_TIM17_CH1) ||\ 429 (REMAP == DMA1_CH7_TIM17_UP) ||\ 430 (REMAP == DMA1_CH7_USART1_TX) ||\ 431 (REMAP == DMA1_CH7_USART2_TX) ||\ 432 (REMAP == DMA1_CH7_USART3_TX) ||\ 433 (REMAP == DMA1_CH7_USART4_TX) ||\ 434 (REMAP == DMA1_CH7_USART5_TX) ||\ 435 (REMAP == DMA1_CH7_USART6_TX) ||\ 436 (REMAP == DMA1_CH7_USART7_TX) ||\ 437 (REMAP == DMA1_CH7_USART8_TX)) 438 439 /****************** DMA2 remap bit field definition********************/ 440 /* DMA2 - Channel 1 */ 441 #define DMA2_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ 442 #define DMA2_CH1_I2C2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ 443 #define DMA2_CH1_USART1_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ 444 #define DMA2_CH1_USART2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ 445 #define DMA2_CH1_USART3_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ 446 #define DMA2_CH1_USART4_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ 447 #define DMA2_CH1_USART5_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ 448 #define DMA2_CH1_USART6_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ 449 #define DMA2_CH1_USART7_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ 450 #define DMA2_CH1_USART8_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ 451 /* DMA2 - Channel 2 */ 452 #define DMA2_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ 453 #define DMA2_CH2_I2C2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ 454 #define DMA2_CH2_USART1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ 455 #define DMA2_CH2_USART2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ 456 #define DMA2_CH2_USART3_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ 457 #define DMA2_CH2_USART4_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ 458 #define DMA2_CH2_USART5_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ 459 #define DMA2_CH2_USART6_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ 460 #define DMA2_CH2_USART7_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ 461 #define DMA2_CH2_USART8_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ 462 /* DMA2 - Channel 3 */ 463 #define DMA2_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ 464 #define DMA2_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ 465 #define DMA2_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ 466 #define DMA2_CH3_SPI1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ 467 #define DMA2_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ 468 #define DMA2_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ 469 #define DMA2_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ 470 #define DMA2_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ 471 #define DMA2_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ 472 #define DMA2_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ 473 #define DMA2_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ 474 #define DMA2_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ 475 /* DMA2 - Channel 4 */ 476 #define DMA2_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ 477 #define DMA2_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ 478 #define DMA2_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ 479 #define DMA2_CH4_SPI1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ 480 #define DMA2_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ 481 #define DMA2_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ 482 #define DMA2_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ 483 #define DMA2_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ 484 #define DMA2_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ 485 #define DMA2_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ 486 #define DMA2_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ 487 #define DMA2_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ 488 /* DMA2 - Channel 5 */ 489 #define DMA2_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ 490 #define DMA2_CH5_ADC (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ 491 #define DMA2_CH5_USART1_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ 492 #define DMA2_CH5_USART2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ 493 #define DMA2_CH5_USART3_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ 494 #define DMA2_CH5_USART4_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ 495 #define DMA2_CH5_USART5_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ 496 #define DMA2_CH5_USART6_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ 497 #define DMA2_CH5_USART7_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ 498 #define DMA2_CH5_USART8_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ 499 500 #define IS_DMA2_REMAP(REMAP) ((REMAP == DMA2_CH1_DEFAULT) ||\ 501 (REMAP == DMA2_CH1_I2C2_TX) ||\ 502 (REMAP == DMA2_CH1_USART1_TX) ||\ 503 (REMAP == DMA2_CH1_USART2_TX) ||\ 504 (REMAP == DMA2_CH1_USART3_TX) ||\ 505 (REMAP == DMA2_CH1_USART4_TX) ||\ 506 (REMAP == DMA2_CH1_USART5_TX) ||\ 507 (REMAP == DMA2_CH1_USART6_TX) ||\ 508 (REMAP == DMA2_CH1_USART7_TX) ||\ 509 (REMAP == DMA2_CH1_USART8_TX) ||\ 510 (REMAP == DMA2_CH2_DEFAULT) ||\ 511 (REMAP == DMA2_CH2_I2C2_RX) ||\ 512 (REMAP == DMA2_CH2_USART1_RX) ||\ 513 (REMAP == DMA2_CH2_USART2_RX) ||\ 514 (REMAP == DMA2_CH2_USART3_RX) ||\ 515 (REMAP == DMA2_CH2_USART4_RX) ||\ 516 (REMAP == DMA2_CH2_USART5_RX) ||\ 517 (REMAP == DMA2_CH2_USART6_RX) ||\ 518 (REMAP == DMA2_CH2_USART7_RX) ||\ 519 (REMAP == DMA2_CH2_USART8_RX) ||\ 520 (REMAP == DMA2_CH3_DEFAULT) ||\ 521 (REMAP == DMA2_CH3_TIM6_UP) ||\ 522 (REMAP == DMA2_CH3_DAC_CH1) ||\ 523 (REMAP == DMA2_CH3_SPI1_RX) ||\ 524 (REMAP == DMA2_CH3_USART1_RX) ||\ 525 (REMAP == DMA2_CH3_USART2_RX) ||\ 526 (REMAP == DMA2_CH3_USART3_RX) ||\ 527 (REMAP == DMA2_CH3_USART4_RX) ||\ 528 (REMAP == DMA2_CH3_USART5_RX) ||\ 529 (REMAP == DMA2_CH3_USART6_RX) ||\ 530 (REMAP == DMA2_CH3_USART7_RX) ||\ 531 (REMAP == DMA2_CH3_USART8_RX) ||\ 532 (REMAP == DMA2_CH4_DEFAULT) ||\ 533 (REMAP == DMA2_CH4_TIM7_UP) ||\ 534 (REMAP == DMA2_CH4_DAC_CH2) ||\ 535 (REMAP == DMA2_CH4_SPI1_TX) ||\ 536 (REMAP == DMA2_CH4_USART1_TX) ||\ 537 (REMAP == DMA2_CH4_USART2_TX) ||\ 538 (REMAP == DMA2_CH4_USART3_TX) ||\ 539 (REMAP == DMA2_CH4_USART4_TX) ||\ 540 (REMAP == DMA2_CH4_USART5_TX) ||\ 541 (REMAP == DMA2_CH4_USART6_TX) ||\ 542 (REMAP == DMA2_CH4_USART7_TX) ||\ 543 (REMAP == DMA2_CH4_USART8_TX) ||\ 544 (REMAP == DMA2_CH5_DEFAULT) ||\ 545 (REMAP == DMA2_CH5_ADC) ||\ 546 (REMAP == DMA2_CH5_USART1_TX) ||\ 547 (REMAP == DMA2_CH5_USART2_TX) ||\ 548 (REMAP == DMA2_CH5_USART3_TX) ||\ 549 (REMAP == DMA2_CH5_USART4_TX) ||\ 550 (REMAP == DMA2_CH5_USART5_TX) ||\ 551 (REMAP == DMA2_CH5_USART6_TX) ||\ 552 (REMAP == DMA2_CH5_USART7_TX) ||\ 553 (REMAP == DMA2_CH5_USART8_TX )) 554 555 /** 556 * @} 557 */ 558 559 /** @defgroup DMA_interrupts_definition 560 * @{ 561 */ 562 563 #define DMA_IT_TC DMA_CCR_TCIE 564 #define DMA_IT_HT DMA_CCR_HTIE 565 #define DMA_IT_TE DMA_CCR_TEIE 566 567 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) 568 569 #define DMA1_IT_GL1 DMA_ISR_GIF1 570 #define DMA1_IT_TC1 DMA_ISR_TCIF1 571 #define DMA1_IT_HT1 DMA_ISR_HTIF1 572 #define DMA1_IT_TE1 DMA_ISR_TEIF1 573 #define DMA1_IT_GL2 DMA_ISR_GIF2 574 #define DMA1_IT_TC2 DMA_ISR_TCIF2 575 #define DMA1_IT_HT2 DMA_ISR_HTIF2 576 #define DMA1_IT_TE2 DMA_ISR_TEIF2 577 #define DMA1_IT_GL3 DMA_ISR_GIF3 578 #define DMA1_IT_TC3 DMA_ISR_TCIF3 579 #define DMA1_IT_HT3 DMA_ISR_HTIF3 580 #define DMA1_IT_TE3 DMA_ISR_TEIF3 581 #define DMA1_IT_GL4 DMA_ISR_GIF4 582 #define DMA1_IT_TC4 DMA_ISR_TCIF4 583 #define DMA1_IT_HT4 DMA_ISR_HTIF4 584 #define DMA1_IT_TE4 DMA_ISR_TEIF4 585 #define DMA1_IT_GL5 DMA_ISR_GIF5 586 #define DMA1_IT_TC5 DMA_ISR_TCIF5 587 #define DMA1_IT_HT5 DMA_ISR_HTIF5 588 #define DMA1_IT_TE5 DMA_ISR_TEIF5 589 #define DMA1_IT_GL6 DMA_ISR_GIF6 590 #define DMA1_IT_TC6 DMA_ISR_TCIF6 591 #define DMA1_IT_HT6 DMA_ISR_HTIF6 592 #define DMA1_IT_TE6 DMA_ISR_TEIF6 593 #define DMA1_IT_GL7 DMA_ISR_GIF7 594 #define DMA1_IT_TC7 DMA_ISR_TCIF7 595 #define DMA1_IT_HT7 DMA_ISR_HTIF7 596 #define DMA1_IT_TE7 DMA_ISR_TEIF7 597 598 #define DMA2_IT_GL1 ((uint32_t)0x10000001) 599 #define DMA2_IT_TC1 ((uint32_t)0x10000002) 600 #define DMA2_IT_HT1 ((uint32_t)0x10000004) 601 #define DMA2_IT_TE1 ((uint32_t)0x10000008) 602 #define DMA2_IT_GL2 ((uint32_t)0x10000010) 603 #define DMA2_IT_TC2 ((uint32_t)0x10000020) 604 #define DMA2_IT_HT2 ((uint32_t)0x10000040) 605 #define DMA2_IT_TE2 ((uint32_t)0x10000080) 606 #define DMA2_IT_GL3 ((uint32_t)0x10000100) 607 #define DMA2_IT_TC3 ((uint32_t)0x10000200) 608 #define DMA2_IT_HT3 ((uint32_t)0x10000400) 609 #define DMA2_IT_TE3 ((uint32_t)0x10000800) 610 #define DMA2_IT_GL4 ((uint32_t)0x10001000) 611 #define DMA2_IT_TC4 ((uint32_t)0x10002000) 612 #define DMA2_IT_HT4 ((uint32_t)0x10004000) 613 #define DMA2_IT_TE4 ((uint32_t)0x10008000) 614 #define DMA2_IT_GL5 ((uint32_t)0x10010000) 615 #define DMA2_IT_TC5 ((uint32_t)0x10020000) 616 #define DMA2_IT_HT5 ((uint32_t)0x10040000) 617 #define DMA2_IT_TE5 ((uint32_t)0x10080000) 618 619 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) 620 621 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ 622 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ 623 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ 624 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ 625 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ 626 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ 627 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ 628 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ 629 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ 630 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ 631 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ 632 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ 633 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ 634 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ 635 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ 636 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ 637 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ 638 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ 639 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ 640 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ 641 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ 642 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ 643 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ 644 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) 645 646 /** 647 * @} 648 */ 649 650 /** @defgroup DMA_flags_definition 651 * @{ 652 */ 653 #define DMA1_FLAG_GL1 DMA_ISR_GIF1 654 #define DMA1_FLAG_TC1 DMA_ISR_TCIF1 655 #define DMA1_FLAG_HT1 DMA_ISR_HTIF1 656 #define DMA1_FLAG_TE1 DMA_ISR_TEIF1 657 #define DMA1_FLAG_GL2 DMA_ISR_GIF2 658 #define DMA1_FLAG_TC2 DMA_ISR_TCIF2 659 #define DMA1_FLAG_HT2 DMA_ISR_HTIF2 660 #define DMA1_FLAG_TE2 DMA_ISR_TEIF2 661 #define DMA1_FLAG_GL3 DMA_ISR_GIF3 662 #define DMA1_FLAG_TC3 DMA_ISR_TCIF3 663 #define DMA1_FLAG_HT3 DMA_ISR_HTIF3 664 #define DMA1_FLAG_TE3 DMA_ISR_TEIF3 665 #define DMA1_FLAG_GL4 DMA_ISR_GIF4 666 #define DMA1_FLAG_TC4 DMA_ISR_TCIF4 667 #define DMA1_FLAG_HT4 DMA_ISR_HTIF4 668 #define DMA1_FLAG_TE4 DMA_ISR_TEIF4 669 #define DMA1_FLAG_GL5 DMA_ISR_GIF5 670 #define DMA1_FLAG_TC5 DMA_ISR_TCIF5 671 #define DMA1_FLAG_HT5 DMA_ISR_HTIF5 672 #define DMA1_FLAG_TE5 DMA_ISR_TEIF5 673 #define DMA1_FLAG_GL6 DMA_ISR_GIF6 674 #define DMA1_FLAG_TC6 DMA_ISR_TCIF6 675 #define DMA1_FLAG_HT6 DMA_ISR_HTIF6 676 #define DMA1_FLAG_TE6 DMA_ISR_TEIF6 677 #define DMA1_FLAG_GL7 DMA_ISR_GIF7 678 #define DMA1_FLAG_TC7 DMA_ISR_TCIF7 679 #define DMA1_FLAG_HT7 DMA_ISR_HTIF7 680 #define DMA1_FLAG_TE7 DMA_ISR_TEIF7 681 682 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) 683 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) 684 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) 685 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) 686 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) 687 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) 688 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) 689 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) 690 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) 691 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) 692 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) 693 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) 694 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) 695 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) 696 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) 697 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) 698 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) 699 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) 700 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) 701 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) 702 703 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) 704 705 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ 706 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ 707 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ 708 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ 709 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ 710 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ 711 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ 712 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ 713 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ 714 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ 715 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ 716 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ 717 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ 718 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ 719 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ 720 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ 721 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ 722 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ 723 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ 724 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ 725 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ 726 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ 727 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ 728 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) 729 /** 730 * @} 731 */ 732 733 /** @defgroup DMA_Buffer_Size 734 * @{ 735 */ 736 737 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 738 739 /** 740 * @} 741 */ 742 743 /** 744 * @} 745 */ 746 747 /* Exported macro ------------------------------------------------------------*/ 748 /* Exported functions ------------------------------------------------------- */ 749 750 /* Function used to set the DMA configuration to the default reset state ******/ 751 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); 752 753 /* Initialization and Configuration functions *********************************/ 754 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); 755 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); 756 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); 757 758 /* Data Counter functions******************************************************/ 759 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 760 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); 761 762 /* Interrupts and flags management functions **********************************/ 763 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); 764 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); 765 void DMA_ClearFlag(uint32_t DMAy_FLAG); 766 ITStatus DMA_GetITStatus(uint32_t DMAy_IT); 767 void DMA_ClearITPendingBit(uint32_t DMAy_IT); 768 769 #ifdef __cplusplus 770 } 771 #endif 772 773 #endif /*__FT32F0XX_DMA_H */ 774 775 /** 776 * @} 777 */ 778 779 /** 780 * @} 781 */ 782 783 /************************ (C) COPYRIGHT FMD *****END OF FILE****/ 784