1 /** 2 ****************************************************************************** 3 * @file ft32f0xx_spi.h 4 * @author FMD AE 5 * @brief This file contains all the functions prototypes for the SPI 6 * firmware library. 7 * @version V1.0.0 8 * @data 2021-07-01 9 ****************************************************************************** 10 */ 11 12 13 /* Define to prevent recursive inclusion -------------------------------------*/ 14 #ifndef __FT32F0XX_SPI_H 15 #define __FT32F0XX_SPI_H 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* Includes ------------------------------------------------------------------*/ 22 #include "ft32f0xx.h" 23 24 25 /** @addtogroup SPI 26 * @{ 27 */ 28 29 /* Exported types ------------------------------------------------------------*/ 30 31 /** 32 * @brief SPI Init structure definition 33 */ 34 35 typedef struct 36 { 37 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. 38 This parameter can be a value of @ref SPI_data_direction */ 39 40 uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). 41 This parameter can be a value of @ref SPI_mode */ 42 43 uint16_t SPI_DataSize; /*!< Specifies the SPI data size. 44 This parameter can be a value of @ref SPI_data_size */ 45 46 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. 47 This parameter can be a value of @ref SPI_Clock_Polarity */ 48 49 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. 50 This parameter can be a value of @ref SPI_Clock_Phase */ 51 52 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by 53 hardware (NSS pin) or by software using the SSI bit. 54 This parameter can be a value of @ref SPI_Slave_Select_management */ 55 56 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 57 used to configure the transmit and receive SCK clock. 58 This parameter can be a value of @ref SPI_BaudRate_Prescaler 59 @note The communication clock is derived from the master 60 clock. The slave clock does not need to be set. */ 61 62 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 63 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 64 65 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ 66 }SPI_InitTypeDef; 67 68 69 /* Exported constants --------------------------------------------------------*/ 70 71 /** @defgroup SPI_Exported_Constants 72 * @{ 73 */ 74 75 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ 76 ((PERIPH) == SPI2)) 77 78 #define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) 79 80 /** @defgroup SPI_data_direction 81 * @{ 82 */ 83 84 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 85 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 86 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 87 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 88 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ 89 ((MODE) == SPI_Direction_2Lines_RxOnly) || \ 90 ((MODE) == SPI_Direction_1Line_Rx) || \ 91 ((MODE) == SPI_Direction_1Line_Tx)) 92 /** 93 * @} 94 */ 95 96 /** @defgroup SPI_mode 97 * @{ 98 */ 99 100 #define SPI_Mode_Master ((uint16_t)0x0104) 101 #define SPI_Mode_Slave ((uint16_t)0x0000) 102 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 103 ((MODE) == SPI_Mode_Slave)) 104 /** 105 * @} 106 */ 107 108 /** @defgroup SPI_data_size 109 * @{ 110 */ 111 112 #define SPI_DataSize_4b ((uint16_t)0x0300) 113 #define SPI_DataSize_5b ((uint16_t)0x0400) 114 #define SPI_DataSize_6b ((uint16_t)0x0500) 115 #define SPI_DataSize_7b ((uint16_t)0x0600) 116 #define SPI_DataSize_8b ((uint16_t)0x0700) 117 #define SPI_DataSize_9b ((uint16_t)0x0800) 118 #define SPI_DataSize_10b ((uint16_t)0x0900) 119 #define SPI_DataSize_11b ((uint16_t)0x0A00) 120 #define SPI_DataSize_12b ((uint16_t)0x0B00) 121 #define SPI_DataSize_13b ((uint16_t)0x0C00) 122 #define SPI_DataSize_14b ((uint16_t)0x0D00) 123 #define SPI_DataSize_15b ((uint16_t)0x0E00) 124 #define SPI_DataSize_16b ((uint16_t)0x0F00) 125 #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ 126 ((SIZE) == SPI_DataSize_5b) || \ 127 ((SIZE) == SPI_DataSize_6b) || \ 128 ((SIZE) == SPI_DataSize_7b) || \ 129 ((SIZE) == SPI_DataSize_8b) || \ 130 ((SIZE) == SPI_DataSize_9b) || \ 131 ((SIZE) == SPI_DataSize_10b) || \ 132 ((SIZE) == SPI_DataSize_11b) || \ 133 ((SIZE) == SPI_DataSize_12b) || \ 134 ((SIZE) == SPI_DataSize_13b) || \ 135 ((SIZE) == SPI_DataSize_14b) || \ 136 ((SIZE) == SPI_DataSize_15b) || \ 137 ((SIZE) == SPI_DataSize_16b)) 138 /** 139 * @} 140 */ 141 142 /** @defgroup SPI_CRC_length 143 * @{ 144 */ 145 146 #define SPI_CRCLength_8b ((uint16_t)0x0000) 147 #define SPI_CRCLength_16b SPI_CR1_CRCL 148 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ 149 ((LENGTH) == SPI_CRCLength_16b)) 150 /** 151 * @} 152 */ 153 154 /** @defgroup SPI_Clock_Polarity 155 * @{ 156 */ 157 158 #define SPI_CPOL_Low ((uint16_t)0x0000) 159 #define SPI_CPOL_High SPI_CR1_CPOL 160 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 161 ((CPOL) == SPI_CPOL_High)) 162 /** 163 * @} 164 */ 165 166 /** @defgroup SPI_Clock_Phase 167 * @{ 168 */ 169 170 #define SPI_CPHA_1Edge ((uint16_t)0x0000) 171 #define SPI_CPHA_2Edge SPI_CR1_CPHA 172 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 173 ((CPHA) == SPI_CPHA_2Edge)) 174 /** 175 * @} 176 */ 177 178 /** @defgroup SPI_Slave_Select_management 179 * @{ 180 */ 181 182 #define SPI_NSS_Soft SPI_CR1_SSM 183 #define SPI_NSS_Hard ((uint16_t)0x0000) 184 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 185 ((NSS) == SPI_NSS_Hard)) 186 /** 187 * @} 188 */ 189 190 /** @defgroup SPI_BaudRate_Prescaler 191 * @{ 192 */ 193 194 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 195 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 196 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 197 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 198 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 199 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 200 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 201 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 202 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 203 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 204 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 205 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 206 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 207 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 208 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 209 ((PRESCALER) == SPI_BaudRatePrescaler_256)) 210 /** 211 * @} 212 */ 213 214 /** @defgroup SPI_MSB_LSB_transmission 215 * @{ 216 */ 217 218 #define SPI_FirstBit_MSB ((uint16_t)0x0000) 219 #define SPI_FirstBit_LSB SPI_CR1_LSBFIRST 220 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 221 ((BIT) == SPI_FirstBit_LSB)) 222 /** 223 * @} 224 */ 225 226 /** @defgroup SPI_I2S_Mode 227 * @{ 228 */ 229 230 #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 231 #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 232 #define I2S_Mode_MasterTx ((uint16_t)0x0200) 233 #define I2S_Mode_MasterRx ((uint16_t)0x0300) 234 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ 235 ((MODE) == I2S_Mode_SlaveRx) || \ 236 ((MODE) == I2S_Mode_MasterTx)|| \ 237 ((MODE) == I2S_Mode_MasterRx)) 238 /** 239 * @} 240 */ 241 242 /** @defgroup SPI_I2S_Standard 243 * @{ 244 */ 245 246 #define I2S_Standard_Phillips ((uint16_t)0x0000) 247 #define I2S_Standard_MSB ((uint16_t)0x0010) 248 #define I2S_Standard_LSB ((uint16_t)0x0020) 249 #define I2S_Standard_PCMShort ((uint16_t)0x0030) 250 #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 251 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ 252 ((STANDARD) == I2S_Standard_MSB) || \ 253 ((STANDARD) == I2S_Standard_LSB) || \ 254 ((STANDARD) == I2S_Standard_PCMShort) || \ 255 ((STANDARD) == I2S_Standard_PCMLong)) 256 /** 257 * @} 258 */ 259 260 /** @defgroup SPI_I2S_Data_Format 261 * @{ 262 */ 263 264 #define I2S_DataFormat_16b ((uint16_t)0x0000) 265 #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 266 #define I2S_DataFormat_24b ((uint16_t)0x0003) 267 #define I2S_DataFormat_32b ((uint16_t)0x0005) 268 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ 269 ((FORMAT) == I2S_DataFormat_16bextended) || \ 270 ((FORMAT) == I2S_DataFormat_24b) || \ 271 ((FORMAT) == I2S_DataFormat_32b)) 272 /** 273 * @} 274 */ 275 276 /** @defgroup SPI_I2S_MCLK_Output 277 * @{ 278 */ 279 280 #define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE 281 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 282 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ 283 ((OUTPUT) == I2S_MCLKOutput_Disable)) 284 /** 285 * @} 286 */ 287 288 /** @defgroup SPI_I2S_Audio_Frequency 289 * @{ 290 */ 291 292 #define I2S_AudioFreq_192k ((uint32_t)192000) 293 #define I2S_AudioFreq_96k ((uint32_t)96000) 294 #define I2S_AudioFreq_48k ((uint32_t)48000) 295 #define I2S_AudioFreq_44k ((uint32_t)44100) 296 #define I2S_AudioFreq_32k ((uint32_t)32000) 297 #define I2S_AudioFreq_22k ((uint32_t)22050) 298 #define I2S_AudioFreq_16k ((uint32_t)16000) 299 #define I2S_AudioFreq_11k ((uint32_t)11025) 300 #define I2S_AudioFreq_8k ((uint32_t)8000) 301 #define I2S_AudioFreq_Default ((uint32_t)2) 302 303 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ 304 ((FREQ) <= I2S_AudioFreq_192k)) || \ 305 ((FREQ) == I2S_AudioFreq_Default)) 306 /** 307 * @} 308 */ 309 310 /** @defgroup SPI_I2S_Clock_Polarity 311 * @{ 312 */ 313 314 #define I2S_CPOL_Low ((uint16_t)0x0000) 315 #define I2S_CPOL_High SPI_I2SCFGR_CKPOL 316 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ 317 ((CPOL) == I2S_CPOL_High)) 318 /** 319 * @} 320 */ 321 322 /** @defgroup SPI_FIFO_reception_threshold 323 * @{ 324 */ 325 326 #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) 327 #define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH 328 #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ 329 ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) 330 /** 331 * @} 332 */ 333 334 /** @defgroup SPI_I2S_DMA_transfer_requests 335 * @{ 336 */ 337 338 #define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN 339 #define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN 340 #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) 341 /** 342 * @} 343 */ 344 345 /** @defgroup SPI_last_DMA_transfers 346 * @{ 347 */ 348 349 #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) 350 #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) 351 #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) 352 #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) 353 #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ 354 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ 355 ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ 356 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) 357 /** 358 * @} 359 */ 360 /** @defgroup SPI_NSS_internal_software_management 361 * @{ 362 */ 363 364 #define SPI_NSSInternalSoft_Set SPI_CR1_SSI 365 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 366 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 367 ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 368 /** 369 * @} 370 */ 371 372 /** @defgroup SPI_CRC_Transmit_Receive 373 * @{ 374 */ 375 376 #define SPI_CRC_Tx ((uint8_t)0x00) 377 #define SPI_CRC_Rx ((uint8_t)0x01) 378 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) 379 /** 380 * @} 381 */ 382 383 /** @defgroup SPI_direction_transmit_receive 384 * @{ 385 */ 386 387 #define SPI_Direction_Rx ((uint16_t)0xBFFF) 388 #define SPI_Direction_Tx ((uint16_t)0x4000) 389 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 390 ((DIRECTION) == SPI_Direction_Tx)) 391 /** 392 * @} 393 */ 394 395 /** @defgroup SPI_I2S_interrupts_definition 396 * @{ 397 */ 398 399 #define SPI_I2S_IT_TXE ((uint8_t)0x71) 400 #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 401 #define SPI_I2S_IT_ERR ((uint8_t)0x50) 402 403 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ 404 ((IT) == SPI_I2S_IT_RXNE) || \ 405 ((IT) == SPI_I2S_IT_ERR)) 406 407 #define I2S_IT_UDR ((uint8_t)0x53) 408 #define SPI_IT_MODF ((uint8_t)0x55) 409 #define SPI_I2S_IT_OVR ((uint8_t)0x56) 410 #define SPI_I2S_IT_FRE ((uint8_t)0x58) 411 412 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ 413 ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ 414 ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) 415 /** 416 * @} 417 */ 418 419 420 /** @defgroup SPI_transmission_fifo_status_level 421 * @{ 422 */ 423 424 #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) 425 #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) 426 #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) 427 #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) 428 429 /** 430 * @} 431 */ 432 433 /** @defgroup SPI_reception_fifo_status_level 434 * @{ 435 */ 436 #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) 437 #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) 438 #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) 439 #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) 440 441 /** 442 * @} 443 */ 444 445 446 /** @defgroup SPI_I2S_flags_definition 447 * @{ 448 */ 449 450 #define SPI_I2S_FLAG_RXNE SPI_SR_RXNE 451 #define SPI_I2S_FLAG_TXE SPI_SR_TXE 452 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE 453 #define I2S_FLAG_UDR SPI_SR_UDR 454 #define SPI_FLAG_CRCERR SPI_SR_CRCERR 455 #define SPI_FLAG_MODF SPI_SR_MODF 456 #define SPI_I2S_FLAG_OVR SPI_SR_OVR 457 #define SPI_I2S_FLAG_BSY SPI_SR_BSY 458 #define SPI_I2S_FLAG_FRE SPI_SR_FRE 459 460 461 462 #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) 463 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ 464 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ 465 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ 466 ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ 467 ((FLAG) == I2S_FLAG_UDR)) 468 /** 469 * @} 470 */ 471 472 /** @defgroup SPI_CRC_polynomial 473 * @{ 474 */ 475 476 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 477 /** 478 * @} 479 */ 480 481 /** 482 * @} 483 */ 484 485 /* Exported macro ------------------------------------------------------------*/ 486 /* Exported functions ------------------------------------------------------- */ 487 488 /* Initialization and Configuration functions *********************************/ 489 void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 490 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 491 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 492 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 493 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 494 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 495 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 496 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); 497 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 498 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 499 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 500 501 /* Data transfers functions ***************************************************/ 502 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); 503 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); 504 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); 505 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); 506 507 /* Hardware CRC Calculation functions *****************************************/ 508 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); 509 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 510 void SPI_TransmitCRC(SPI_TypeDef* SPIx); 511 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 512 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 513 514 /* DMA transfers management functions *****************************************/ 515 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 516 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); 517 518 /* Interrupts and flags management functions **********************************/ 519 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 520 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); 521 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); 522 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 523 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 524 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 525 526 #ifdef __cplusplus 527 } 528 #endif 529 530 #endif /*__FT32F0XX_SPI_H */ 531 532 /** 533 * @} 534 */ 535 536 /** 537 * @} 538 */ 539 540 /************************ (C) COPYRIGHT FMD *****END OF FILE****/ 541