1 /**
2 ******************************************************************************
3 * @file ft32f0xx_dma.c
4 * @author FMD AE
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Direct Memory Access controller (DMA):
7 * + Initialization and Configuration
8 * + Data Counter
9 * + Interrupts and flags management
10 * @version V1.0.0
11 * @data 2021-07-01
12 ******************************************************************************
13 */
14
15
16 /* Includes ------------------------------------------------------------------*/
17 #include "ft32f0xx_dma.h"
18
19
20 /** @defgroup DMA
21 * @brief DMA driver modules
22 * @{
23 */
24
25 /* Private typedef -----------------------------------------------------------*/
26 /* Private define ------------------------------------------------------------*/
27 #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
28 #define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */
29
30 /* DMA1 Channelx interrupt pending bit masks */
31 #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
32 #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
33 #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
34 #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
35 #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
36 #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
37 #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
38
39 /* DMA2 Channelx interrupt pending bit masks:*/
40 #define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
41 #define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
42 #define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
43 #define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
44 #define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
45
46
47
48 /**
49 * @brief Deinitializes the DMAy Channelx registers to their default reset
50 * values.
51 * @param DMAy_Channelx: where y can be 1 to select the DMA and
52 * x can be 1 to 7 for DMA1 to select the DMA Channel.
53 * @note
54 * @retval None
55 */
DMA_DeInit(DMA_Channel_TypeDef * DMAy_Channelx)56 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
57 {
58 /* Check the parameters */
59 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
60
61 /* Disable the selected DMAy Channelx */
62 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
63
64 /* Reset DMAy Channelx control register */
65 DMAy_Channelx->CCR = 0;
66
67 /* Reset DMAy Channelx remaining bytes register */
68 DMAy_Channelx->CNDTR = 0;
69
70 /* Reset DMAy Channelx peripheral address register */
71 DMAy_Channelx->CPAR = 0;
72
73 /* Reset DMAy Channelx memory address register */
74 DMAy_Channelx->CMAR = 0;
75
76 if (DMAy_Channelx == DMA1_Channel1)
77 {
78 /* Reset interrupt pending bits for DMA1 Channel1 */
79 DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
80 }
81 else if (DMAy_Channelx == DMA1_Channel2)
82 {
83 /* Reset interrupt pending bits for DMA1 Channel2 */
84 DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
85 }
86 else if (DMAy_Channelx == DMA1_Channel3)
87 {
88 /* Reset interrupt pending bits for DMA1 Channel3 */
89 DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
90 }
91 else if (DMAy_Channelx == DMA1_Channel4)
92 {
93 /* Reset interrupt pending bits for DMA1 Channel4 */
94 DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
95 }
96 else if (DMAy_Channelx == DMA1_Channel5)
97 {
98 /* Reset interrupt pending bits for DMA1 Channel5 */
99 DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
100 }
101 // else if (DMAy_Channelx == DMA1_Channel6)
102 // {
103 // /* Reset interrupt pending bits for DMA1 Channel6 */
104 // DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
105 // }
106 // else if (DMAy_Channelx == DMA1_Channel7)
107 // {
108 // /* Reset interrupt pending bits for DMA1 Channel7 */
109 // DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
110 // }
111 }
112
113 /**
114 * @brief Initializes the DMAy Channelx according to the specified parameters
115 * in the DMA_InitStruct.
116 * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
117 * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
118 * @note
119 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
120 * the configuration information for the specified DMA Channel.
121 * @retval None
122 */
DMA_Init(DMA_Channel_TypeDef * DMAy_Channelx,DMA_InitTypeDef * DMA_InitStruct)123 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
124 {
125 uint32_t tmpreg = 0;
126
127 /* Check the parameters */
128 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
129 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
130 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
131 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
132 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
133 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
134 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
135 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
136 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
137 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
138
139 /*--------------------------- DMAy Channelx CCR Configuration ----------------*/
140 /* Get the DMAy_Channelx CCR value */
141 tmpreg = DMAy_Channelx->CCR;
142
143 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
144 tmpreg &= CCR_CLEAR_MASK;
145
146 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
147 /* Set DIR bit according to DMA_DIR value */
148 /* Set CIRC bit according to DMA_Mode value */
149 /* Set PINC bit according to DMA_PeripheralInc value */
150 /* Set MINC bit according to DMA_MemoryInc value */
151 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
152 /* Set MSIZE bits according to DMA_MemoryDataSize value */
153 /* Set PL bits according to DMA_Priority value */
154 /* Set the MEM2MEM bit according to DMA_M2M value */
155 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
156 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
157 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
158 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
159
160 /* Write to DMAy Channelx CCR */
161 DMAy_Channelx->CCR = tmpreg;
162
163 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
164 /* Write to DMAy Channelx CNDTR */
165 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
166
167 /*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
168 /* Write to DMAy Channelx CPAR */
169 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
170
171 /*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
172 /* Write to DMAy Channelx CMAR */
173 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
174 }
175
176 /**
177 * @brief Fills each DMA_InitStruct member with its default value.
178 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
179 * be initialized.
180 * @retval None
181 */
DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct)182 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
183 {
184 /*-------------- Reset DMA init structure parameters values ------------------*/
185 /* Initialize the DMA_PeripheralBaseAddr member */
186 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
187 /* Initialize the DMA_MemoryBaseAddr member */
188 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
189 /* Initialize the DMA_DIR member */
190 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
191 /* Initialize the DMA_BufferSize member */
192 DMA_InitStruct->DMA_BufferSize = 0;
193 /* Initialize the DMA_PeripheralInc member */
194 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
195 /* Initialize the DMA_MemoryInc member */
196 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
197 /* Initialize the DMA_PeripheralDataSize member */
198 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
199 /* Initialize the DMA_MemoryDataSize member */
200 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
201 /* Initialize the DMA_Mode member */
202 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
203 /* Initialize the DMA_Priority member */
204 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
205 /* Initialize the DMA_M2M member */
206 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
207 }
208
209 /**
210 * @brief Enables or disables the specified DMAy Channelx.
211 * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
212 * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
213 * @param NewState: new state of the DMAy Channelx.
214 * This parameter can be: ENABLE or DISABLE.
215 * @retval None
216 */
DMA_Cmd(DMA_Channel_TypeDef * DMAy_Channelx,FunctionalState NewState)217 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
218 {
219 /* Check the parameters */
220 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
221 assert_param(IS_FUNCTIONAL_STATE(NewState));
222
223 if (NewState != DISABLE)
224 {
225 /* Enable the selected DMAy Channelx */
226 DMAy_Channelx->CCR |= DMA_CCR_EN;
227 }
228 else
229 {
230 /* Disable the selected DMAy Channelx */
231 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
232 }
233 }
234 /**
235 * @}
236 */
237
238
239
240 /**
241 * @brief Sets the number of data units in the current DMAy Channelx transfer.
242 * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
243 * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
244
245 * @param DataNumber: The number of data units in the current DMAy Channelx
246 * transfer.
247 * @note This function can only be used when the DMAy_Channelx is disabled.
248 * @retval None.
249 */
DMA_SetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx,uint16_t DataNumber)250 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
251 {
252 /* Check the parameters */
253 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
254
255 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
256 /* Write to DMAy Channelx CNDTR */
257 DMAy_Channelx->CNDTR = DataNumber;
258 }
259
260 /**
261 * @brief Returns the number of remaining data units in the current
262 * DMAy Channelx transfer.
263 * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
264 * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
265 * @retval The number of remaining data units in the current DMAy Channelx
266 * transfer.
267 */
DMA_GetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx)268 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
269 {
270 /* Check the parameters */
271 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
272 /* Return the number of remaining data units for DMAy Channelx */
273 return ((uint16_t)(DMAy_Channelx->CNDTR));
274 }
275
276 /**
277 * @}
278 */
279
280
281 /**
282 * @brief Enables or disables the specified DMAy Channelx interrupts.
283 * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
284 * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel.
285 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
286 * or disabled.
287 * This parameter can be any combination of the following values:
288 * @arg DMA_IT_TC: Transfer complete interrupt mask
289 * @arg DMA_IT_HT: Half transfer interrupt mask
290 * @arg DMA_IT_TE: Transfer error interrupt mask
291 * @param NewState: new state of the specified DMA interrupts.
292 * This parameter can be: ENABLE or DISABLE.
293 * @retval None
294 */
DMA_ITConfig(DMA_Channel_TypeDef * DMAy_Channelx,uint32_t DMA_IT,FunctionalState NewState)295 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
296 {
297 /* Check the parameters */
298 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
299 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
300 assert_param(IS_FUNCTIONAL_STATE(NewState));
301
302 if (NewState != DISABLE)
303 {
304 /* Enable the selected DMA interrupts */
305 DMAy_Channelx->CCR |= DMA_IT;
306 }
307 else
308 {
309 /* Disable the selected DMA interrupts */
310 DMAy_Channelx->CCR &= ~DMA_IT;
311 }
312 }
313
314 /**
315 * @brief Checks whether the specified DMAy Channelx flag is set or not.
316 * @param DMA_FLAG: specifies the flag to check.
317 * This parameter can be one of the following values:
318 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
319 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
320 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
321 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
322 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
323 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
324 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
325 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
326 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
327 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
328 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
329 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
330 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
331 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
332 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
333 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
334 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
335 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
336 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
337 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
338 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag
339 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag
340 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag
341 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag
342 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag
343 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag
344 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag
345 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag
346 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag
347 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag
348 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag
349 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag
350 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag
351 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag
352 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag
353 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag
354 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag
355 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag
356 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag
357 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag
358 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag
359 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag
360 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag
361 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag
362 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag
363 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag
364 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag
365 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag
366 * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the ot
367 * relative to the same channel is set (Transfer Complete, Half-transfer
368 * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
369 * DMAy_FLAG_TEx).
370 *
371 * @retval The new state of DMA_FLAG (SET or RESET).
372 */
DMA_GetFlagStatus(uint32_t DMAy_FLAG)373 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
374 {
375 FlagStatus bitstatus = RESET;
376 uint32_t tmpreg = 0;
377
378 /* Check the parameters */
379 assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
380
381 /* Calculate the used DMAy */
382 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
383 {
384 ;
385 }
386 else
387 {
388 /* Get DMA1 ISR register value */
389 tmpreg = DMA1->ISR ;
390 }
391
392 /* Check the status of the specified DMAy flag */
393 if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
394 {
395 /* DMAy_FLAG is set */
396 bitstatus = SET;
397 }
398 else
399 {
400 /* DMAy_FLAG is reset */
401 bitstatus = RESET;
402 }
403
404 /* Return the DMAy_FLAG status */
405 return bitstatus;
406 }
407
408 /**
409 * @brief Clears the DMAy Channelx's pending flags.
410 * @param DMA_FLAG: specifies the flag to clear.
411 * This parameter can be any combination (for the same DMA) of the following values:
412 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
413 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
414 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
415 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
416 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
417 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
418 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
419 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
420 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
421 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
422 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
423 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
424 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
425 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
426 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
427 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
428 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
429 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
430 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
431 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
432 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag
433 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag
434 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag
435 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag
436 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag
437 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag
438 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag
439 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag
440 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag
441 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag
442 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag
443 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag
444 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag
445 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag
446 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag
447 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag
448 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag
449 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag
450 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag
451 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag
452 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag
453 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag
454 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag
455 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag
456 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag
457 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag
458 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag
459 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag
460 *
461 * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
462 * relative to the same channel (Transfer Complete, Half-transfer Complete and
463 * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
464 *
465 * @retval None
466 */
DMA_ClearFlag(uint32_t DMAy_FLAG)467 void DMA_ClearFlag(uint32_t DMAy_FLAG)
468 {
469 /* Check the parameters */
470 assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
471
472 /* Calculate the used DMAy */
473 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
474 {
475 ;
476 }
477 else
478 {
479 /* Clear the selected DMAy flags */
480 DMA1->IFCR = DMAy_FLAG;
481 }
482 }
483
484 /**
485 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
486 * @param DMA_IT: specifies the DMA interrupt source to check.
487 * This parameter can be one of the following values:
488 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
489 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
490 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
491 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
492 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
493 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
494 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
495 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
496 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
497 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
498 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
499 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
500 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
501 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
502 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
503 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
504 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
505 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
506 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
507 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
508 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt
509 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt
510 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt
511 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt
512 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt
513 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt
514 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt
515 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt
516 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt
517 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt
518 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt
519 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt
520 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt
521 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt
522 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt
523 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt
524 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt
525 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt
526 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt
527 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt
528 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt
529 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt
530 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt
531 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt
532 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt
533 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt
534 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt
535 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt
536 * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
537 * interrupts relative to the same channel is set (Transfer Complete,
538 * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
539 * DMAy_IT_HTx or DMAy_IT_TEx).
540 *
541 * @retval The new state of DMA_IT (SET or RESET).
542 */
DMA_GetITStatus(uint32_t DMAy_IT)543 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
544 {
545 ITStatus bitstatus = RESET;
546 uint32_t tmpreg = 0;
547
548 /* Check the parameters */
549 assert_param(IS_DMA_GET_IT(DMAy_IT));
550
551 /* Calculate the used DMA */
552 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
553 {
554 ;
555 }
556 else
557 {
558 /* Get DMA1 ISR register value */
559 tmpreg = DMA1->ISR;
560 }
561
562 /* Check the status of the specified DMAy interrupt */
563 if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
564 {
565 /* DMAy_IT is set */
566 bitstatus = SET;
567 }
568 else
569 {
570 /* DMAy_IT is reset */
571 bitstatus = RESET;
572 }
573 /* Return the DMAy_IT status */
574 return bitstatus;
575 }
576
577 /**
578 * @brief Clears the DMAy Channelx's interrupt pending bits.
579 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
580 * This parameter can be any combination (for the same DMA) of the following values:
581 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
582 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
583 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
584 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
585 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
586 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
587 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
588 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
589 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
590 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
591 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
592 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
593 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
594 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
595 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
596 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
597 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
598 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
599 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
600 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
601 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt
602 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt
603 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt
604 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt
605 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt
606 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt
607 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt
608 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt
609 * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
610 * interrupts relative to the same channel (Transfer Complete, Half-transfer
611 * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
612 * DMAy_IT_TEx).
613 *
614 * @retval None
615 */
DMA_ClearITPendingBit(uint32_t DMAy_IT)616 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
617 {
618 /* Check the parameters */
619 assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
620
621 /* Calculate the used DMAy */
622 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
623 {
624 ;
625 }
626 else
627 {
628 /* Clear the selected DMAy interrupt pending bits */
629 DMA1->IFCR = DMAy_IT;
630 }
631 }
632
633 /**
634 * @}
635 */
636
637 /**
638 * @}
639 */
640
641 /**
642 * @}
643 */
644
645 /**
646 * @}
647 */
648
649 /************************ (C) COPYRIGHT FMD *****END OF FILE****/
650