1 /**
2 ******************************************************************************
3 * @file ft32f0xx_syscfg.c
4 * @author FMD AE
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the SYSCFG peripheral:
7 * + Remapping the memory mapped at 0x00000000
8 * + Remapping the DMA channels
9 * + Enabling I2C fast mode plus driving capability for I2C pins
10 * + Configuring the EXTI lines connection to the GPIO port
11 * + Configuring the CFGR2 features (Connecting some internal signal
12 * to the break input of TIM1)
13 * @version V1.0.0
14 * @data 2021-07-01
15 ******************************************************************************
16 */
17 /* Includes ------------------------------------------------------------------*/
18 #include "ft32f0xx_syscfg.h"
19
20 /**
21 * @brief Deinitializes the SYSCFG registers to their default reset values.
22 * @param None
23 * @retval None
24 * @note MEM_MODE bits are not affected by APB reset.
25 * @note MEM_MODE bits took the value from the user option bytes.
26 * @note CFGR2 register is not affected by APB reset.
27 * @note CLABBB configuration bits are locked when set.
28 * @note To unlock the configuration, perform a system reset.
29 */
SYSCFG_DeInit(void)30 void SYSCFG_DeInit(void)
31 {
32 /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
33 SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
34 /* Set EXTICRx registers to reset value */
35 SYSCFG->EXTICR[0] = 0;
36 SYSCFG->EXTICR[1] = 0;
37 SYSCFG->EXTICR[2] = 0;
38 SYSCFG->EXTICR[3] = 0;
39 /* Set CFGR2 register to reset value: clear SRAM parity error flag */
40 SYSCFG->CFGR2 |= 0;
41 }
42
43 /**
44 * @brief Configures the memory mapping at address 0x00000000.
45 * @param SYSCFG_MemoryRemap: selects the memory remapping.
46 * This parameter can be one of the following values:
47 * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
48 * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
49 * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
50 * @retval None
51 */
SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)52 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
53 {
54 uint32_t tmpctrl = 0;
55
56 /* Check the parameter */
57 assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
58
59 /* Get CFGR1 register value */
60 tmpctrl = SYSCFG->CFGR1;
61
62 /* Clear MEM_MODE bits */
63 tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
64
65 /* Set the new MEM_MODE bits value */
66 tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
67
68 /* Set CFGR1 register with the new memory remap configuration */
69 SYSCFG->CFGR1 = tmpctrl;
70 }
71
72 /**
73 * @brief Configure the DMA channels remapping.
74 * @param SYSCFG_DMARemap: selects the DMA channels remap.
75 * This parameter can be one of the following values:
76 * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
77 * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
78 * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
79 * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
80 * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
81 * @param NewState: new state of the DMA channel remapping.
82 * This parameter can be: ENABLE or DISABLE.
83 * @note When enabled, DMA channel of the selected peripheral is remapped
84 * @note When disabled, Default DMA channel is mapped to the selected peripheral
85 * @note By default TIM17 DMA requests is mapped to channel 1,
86 * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
87 * TIM17 DMA requests to channel 2 and use
88 * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
89 * TIM17 DMA requests to channel 1 (default mapping)
90 * @retval None
91 */
SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap,FunctionalState NewState)92 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
93 {
94 /* Check the parameters */
95 assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
96 assert_param(IS_FUNCTIONAL_STATE(NewState));
97
98 if (NewState != DISABLE)
99 {
100 /* Remap the DMA channel */
101 SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
102 }
103 else
104 {
105 /* use the default DMA channel mapping */
106 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
107 }
108 }
109
110 /**
111 * @brief Configure the I2C fast mode plus driving capability.
112 * @param SYSCFG_I2CFastModePlus: selects the pin.
113 * This parameter can be one of the following values:
114 * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
115 * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
116 * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
117 * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
118 * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9
119 * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10
120 * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7
121 * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
122 *
123 * @param NewState: new state of the DMA channel remapping.
124 * This parameter can be: ENABLE or DISABLE.
125 * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin
126 * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin
127 * @note For I2C1, fast mode plus driving capability can be enabled on all selected
128 * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
129 * on each one of the following pins PB6, PB7, PB8 and PB9.
130 * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
131 * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
132 * @note For all I2C2 pins fast mode plus driving capability can be enabled
133 * only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
134 * @retval None
135 */
SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus,FunctionalState NewState)136 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
137 {
138 /* Check the parameters */
139 assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
140 assert_param(IS_FUNCTIONAL_STATE(NewState));
141
142 if (NewState != DISABLE)
143 {
144 /* Enable fast mode plus driving capability for selected pin */
145 SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
146 }
147 else
148 {
149 /* Disable fast mode plus driving capability for selected pin */
150 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
151 }
152 }
153
154 /** @brief select the modulation envelope source
155 * @param SYSCFG_IRDAEnv: select the envelope source.
156 * This parameter can be a value
157 * @arg SYSCFG_IRDA_ENV_SEL_TIM16
158 * @arg SYSCFG_IRDA_ENV_SEL_USART1
159 * @arg SYSCFG_IRDA_ENV_SEL_USART2
160 * @retval None
161 */
SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv)162 void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv)
163 {
164 /* Check the parameters */
165 assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv));
166
167 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL);
168 SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv);
169 }
170
171 /**
172 * @brief Selects the GPIO pin used as EXTI Line.
173 * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
174 * for EXTI lines where x can be (A, B, C, D, E or F).
175 * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
176 * @note This parameter can be EXTI_PinSourcex where x can be:
177 * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
178 * @retval None
179 */
SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx,uint8_t EXTI_PinSourcex)180 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
181 {
182 uint32_t tmp = 0x00;
183
184 /* Check the parameters */
185 assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
186 assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
187
188 tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
189 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
190 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
191 }
192
193 /**
194 * @brief Connect the selected parameter to the break input of TIM1.
195 * @note The selected configuration is locked and can be unlocked by system reset
196 * @param SYSCFG_Break: selects the configuration to be connected to break
197 * input of TIM1
198 * This parameter can be any combination of the following values:
199 * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1
200 * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
201 * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
202 * @retval None
203 */
SYSCFG_BreakConfig(uint32_t SYSCFG_Break)204 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
205 {
206 /* Check the parameter */
207 assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
208
209 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
210 }
211
212 /**
213 * @}
214 */
215
216 /**
217 * @}
218 */
219
220 /**
221 * @}
222 */
223
224 /**
225 * @}
226 */
227 /************************ (C) COPYRIGHT FMD *****END OF FILE****/
228