1 /**************************************************************************//**
2 * @file core_cm3.c
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
4 * @version V1.40
5 * @date 18. February 2010
6 *
7 * @note
8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23
24 #include <stdint.h>
25
26 /* define compiler specific symbols */
27 #if defined ( __CC_ARM )
28 #define __ASM __asm /*!< asm keyword for ARM Compiler */
29 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
30
31 #elif defined ( __ICCARM__ )
32 #define __ASM __asm /*!< asm keyword for IAR Compiler */
33 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
34
35 #elif defined ( __GNUC__ )
36 #define __ASM __asm /*!< asm keyword for GNU Compiler */
37 #define __INLINE inline /*!< inline keyword for GNU Compiler */
38
39 #elif defined ( __TASKING__ )
40 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
41 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
42
43 #endif
44
45
46 /* ########################## Core Instruction Access ######################### */
47
48 #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
49
50 /**
51 * @brief Reverse byte order (16 bit)
52 *
53 * @param value value to reverse
54 * @return reversed value
55 *
56 * Reverse byte order in unsigned short value
57 */
58 #if (__ARMCC_VERSION < 400677)
__REV16(uint16_t value)59 __ASM uint32_t __REV16(uint16_t value)
60 {
61 rev16 r0, r0
62 bx lr
63 }
64 #endif /* __ARMCC_VERSION */
65
66 /**
67 * @brief Reverse byte order in signed short value with sign extension to integer
68 *
69 * @param value value to reverse
70 * @return reversed value
71 *
72 * Reverse byte order in signed short value with sign extension to integer
73 */
74 #if (__ARMCC_VERSION < 400677)
__REVSH(int16_t value)75 __ASM int32_t __REVSH(int16_t value)
76 {
77 revsh r0, r0
78 bx lr
79 }
80 #endif /* __ARMCC_VERSION */
81
82 /**
83 * @brief Remove the exclusive lock created by ldrex
84 *
85 * Removes the exclusive lock which is created by ldrex.
86 */
87 #if (__ARMCC_VERSION < 400000)
__CLREX(void)88 __ASM void __CLREX(void)
89 {
90 clrex
91 }
92 #endif /* __ARMCC_VERSION */
93
94
95 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
96 /* obsolete */
97 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
98 /* obsolete */
99 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
100 /* obsolete */
101 #endif
102
103
104 /* ########################### Core Function Access ########################### */
105
106 #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
107
108 /**
109 * @brief Return the Control Register value
110 *
111 * @return Control value
112 *
113 * Return the content of the control register
114 */
115 #if (__ARMCC_VERSION < 400000)
__get_CONTROL(void)116 __ASM uint32_t __get_CONTROL(void)
117 {
118 mrs r0, control
119 bx lr
120 }
121 #endif /* __ARMCC_VERSION */
122
123 /**
124 * @brief Set the Control Register value
125 *
126 * @param control Control value
127 *
128 * Set the control register
129 */
130 #if (__ARMCC_VERSION < 400000)
__set_CONTROL(uint32_t control)131 __ASM void __set_CONTROL(uint32_t control)
132 {
133 msr control, r0
134 bx lr
135 }
136 #endif /* __ARMCC_VERSION */
137
138 /**
139 * @brief Get IPSR Register value
140 *
141 * @return uint32_t IPSR value
142 *
143 * return the content of the IPSR register
144 */
145 #if (__ARMCC_VERSION < 400000)
__get_IPSR(void)146 __ASM uint32_t __get_IPSR(void)
147 {
148 mrs r0, ipsr
149 bx lr
150 }
151 #endif /* __ARMCC_VERSION */
152
153 /**
154 * @brief Get APSR Register value
155 *
156 * @return uint32_t APSR value
157 *
158 * return the content of the APSR register
159 */
160 #if (__ARMCC_VERSION < 400000)
__get_APSR(void)161 __ASM uint32_t __get_APSR(void)
162 {
163 mrs r0, apsr
164 bx lr
165 }
166 #endif /* __ARMCC_VERSION */
167
168 /**
169 * @brief Get xPSR Register value
170 *
171 * @return uint32_t xPSR value
172 *
173 * return the content of the xPSR register
174 */
175 #if (__ARMCC_VERSION < 400000)
__get_xPSR(void)176 __ASM uint32_t __get_xPSR(void)
177 {
178 mrs r0, xpsr
179 bx lr
180 }
181 #endif /* __ARMCC_VERSION */
182
183 /**
184 * @brief Return the Process Stack Pointer
185 *
186 * @return ProcessStackPointer
187 *
188 * Return the actual process stack pointer
189 */
190 #if (__ARMCC_VERSION < 400000)
__get_PSP(void)191 __ASM uint32_t __get_PSP(void)
192 {
193 mrs r0, psp
194 bx lr
195 }
196 #endif /* __ARMCC_VERSION */
197
198 /**
199 * @brief Set the Process Stack Pointer
200 *
201 * @param topOfProcStack Process Stack Pointer
202 *
203 * Assign the value ProcessStackPointer to the MSP
204 * (process stack pointer) Cortex processor register
205 */
206 #if (__ARMCC_VERSION < 400000)
__set_PSP(uint32_t topOfProcStack)207 __ASM void __set_PSP(uint32_t topOfProcStack)
208 {
209 msr psp, r0
210 bx lr
211 }
212 #endif /* __ARMCC_VERSION */
213
214 /**
215 * @brief Return the Main Stack Pointer
216 *
217 * @return Main Stack Pointer
218 *
219 * Return the current value of the MSP (main stack pointer)
220 * Cortex processor register
221 */
222 #if (__ARMCC_VERSION < 400000)
__get_MSP(void)223 __ASM uint32_t __get_MSP(void)
224 {
225 mrs r0, msp
226 bx lr
227 }
228 #endif /* __ARMCC_VERSION */
229
230 /**
231 * @brief Set the Main Stack Pointer
232 *
233 * @param topOfMainStack Main Stack Pointer
234 *
235 * Assign the value mainStackPointer to the MSP
236 * (main stack pointer) Cortex processor register
237 */
238 #if (__ARMCC_VERSION < 400000)
__set_MSP(uint32_t mainStackPointer)239 __ASM void __set_MSP(uint32_t mainStackPointer)
240 {
241 msr msp, r0
242 bx lr
243 }
244 #endif /* __ARMCC_VERSION */
245
246 /**
247 * @brief Return the Base Priority value
248 *
249 * @return BasePriority
250 *
251 * Return the content of the base priority register
252 */
253 #if (__ARMCC_VERSION < 400000)
__get_BASEPRI(void)254 __ASM uint32_t __get_BASEPRI(void)
255 {
256 mrs r0, basepri
257 bx lr
258 }
259 #endif /* __ARMCC_VERSION */
260
261 /**
262 * @brief Set the Base Priority value
263 *
264 * @param basePri BasePriority
265 *
266 * Set the base priority register
267 */
268 #if (__ARMCC_VERSION < 400000)
__set_BASEPRI(uint32_t basePri)269 __ASM void __set_BASEPRI(uint32_t basePri)
270 {
271 msr basepri, r0
272 bx lr
273 }
274 #endif /* __ARMCC_VERSION */
275
276 /**
277 * @brief Return the Priority Mask value
278 *
279 * @return PriMask
280 *
281 * Return state of the priority mask bit from the priority mask register
282 */
283 #if (__ARMCC_VERSION < 400000)
__get_PRIMASK(void)284 __ASM uint32_t __get_PRIMASK(void)
285 {
286 mrs r0, primask
287 bx lr
288 }
289 #endif /* __ARMCC_VERSION */
290
291 /**
292 * @brief Set the Priority Mask value
293 *
294 * @param priMask PriMask
295 *
296 * Set the priority mask bit in the priority mask register
297 */
298 #if (__ARMCC_VERSION < 400000)
__set_PRIMASK(uint32_t priMask)299 __ASM void __set_PRIMASK(uint32_t priMask)
300 {
301 msr primask, r0
302 bx lr
303 }
304 #endif /* __ARMCC_VERSION */
305
306 /**
307 * @brief Return the Fault Mask value
308 *
309 * @return FaultMask
310 *
311 * Return the content of the fault mask register
312 */
313 #if (__ARMCC_VERSION < 400000)
__get_FAULTMASK(void)314 __ASM uint32_t __get_FAULTMASK(void)
315 {
316 mrs r0, faultmask
317 bx lr
318 }
319 #endif /* __ARMCC_VERSION */
320
321 /**
322 * @brief Set the Fault Mask value
323 *
324 * @param faultMask faultMask value
325 *
326 * Set the fault mask register
327 */
328 #if (__ARMCC_VERSION < 400000)
__set_FAULTMASK(uint32_t faultMask)329 __ASM void __set_FAULTMASK(uint32_t faultMask)
330 {
331 msr faultmask, r0
332 bx lr
333 }
334 #endif /* __ARMCC_VERSION */
335
336 /**
337 * @brief Return the FPSCR value
338 *
339 * @return FloatingPointStatusControlRegister
340 *
341 * Return the content of the FPSCR register
342 */
343
344 /**
345 * @brief Set the FPSCR value
346 *
347 * @param fpscr FloatingPointStatusControlRegister
348 *
349 * Set the FPSCR register
350 */
351
352
353 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
354 /* obsolete */
355 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
356 /* obsolete */
357 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
358 /* obsolete */
359 #endif
360