1 /**************************************************************************//**
2 * @file core_cmFunc.h
3 * @brief CMSIS Cortex-M Core Function Access Header File
4 * @version V1.40
5 * @date 16. February 2010
6 *
7 * @note
8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23
24 #ifndef __CORE_CMFUNC_H__
25 #define __CORE_CMFUNC_H__
26
27 /* ########################### Core Function Access ########################### */
28
29 #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
30 /* ARM armcc specific functions */
31
32 /**
33 * @brief Enable IRQ Interrupts
34 *
35 * Enables IRQ interrupts by clearing the I-bit in the CPSR.
36 * Can only be executed in Privileged modes.
37 */
38 /* intrinsic void __enable_irq(); */
39
40 /**
41 * @brief Disable IRQ Interrupts
42 *
43 * Disables IRQ interrupts by setting the I-bit in the CPSR.
44 * Can only be executed in Privileged modes.
45 */
46 /* intrinsic void __disable_irq(); */
47
48 /**
49 * @brief Return the Control Register value
50 *
51 * @return Control value
52 *
53 * Return the content of the control register
54 */
55 #if (__ARMCC_VERSION < 400000)
56 extern uint32_t __get_CONTROL(void);
57 #else /* (__ARMCC_VERSION >= 400000) */
__get_CONTROL(void)58 static __INLINE uint32_t __get_CONTROL(void)
59 {
60 register uint32_t __regControl __ASM("control");
61 return(__regControl);
62 }
63 #endif /* __ARMCC_VERSION */
64
65 /**
66 * @brief Set the Control Register value
67 *
68 * @param control Control value
69 *
70 * Set the control register
71 */
72 #if (__ARMCC_VERSION < 400000)
73 extern void __set_CONTROL(uint32_t control);
74 #else /* (__ARMCC_VERSION >= 400000) */
__set_CONTROL(uint32_t control)75 static __INLINE void __set_CONTROL(uint32_t control)
76 {
77 register uint32_t __regControl __ASM("control");
78 __regControl = control;
79 }
80 #endif /* __ARMCC_VERSION */
81
82 /**
83 * @brief Get IPSR Register value
84 *
85 * @return uint32_t IPSR value
86 *
87 * return the content of the IPSR register
88 */
89 #if (__ARMCC_VERSION < 400000)
90 extern uint32_t __get_IPSR(void);
91 #else /* (__ARMCC_VERSION >= 400000) */
__get_IPSR(void)92 static __INLINE uint32_t __get_IPSR(void)
93 {
94 register uint32_t __regIPSR __ASM("ipsr");
95 return(__regIPSR);
96 }
97 #endif /* __ARMCC_VERSION */
98
99 /**
100 * @brief Get APSR Register value
101 *
102 * @return uint32_t APSR value
103 *
104 * return the content of the APSR register
105 */
106 #if (__ARMCC_VERSION < 400000)
107 extern uint32_t __get_APSR(void);
108 #else /* (__ARMCC_VERSION >= 400000) */
__get_APSR(void)109 static __INLINE uint32_t __get_APSR(void)
110 {
111 register uint32_t __regAPSR __ASM("apsr");
112 return(__regAPSR);
113 }
114 #endif /* __ARMCC_VERSION */
115
116 /**
117 * @brief Get xPSR Register value
118 *
119 * @return uint32_t xPSR value
120 *
121 * return the content of the xPSR register
122 */
123 #if (__ARMCC_VERSION < 400000)
124 extern uint32_t __get_xPSR(void);
125 #else /* (__ARMCC_VERSION >= 400000) */
__get_xPSR(void)126 static __INLINE uint32_t __get_xPSR(void)
127 {
128 register uint32_t __regXPSR __ASM("xpsr");
129 return(__regXPSR);
130 }
131 #endif /* __ARMCC_VERSION */
132
133 /**
134 * @brief Return the Process Stack Pointer
135 *
136 * @return ProcessStackPointer
137 *
138 * Return the actual process stack pointer
139 */
140 #if (__ARMCC_VERSION < 400000)
141 extern uint32_t __get_PSP(void);
142 #else /* (__ARMCC_VERSION >= 400000) */
__get_PSP(void)143 static __INLINE uint32_t __get_PSP(void)
144 {
145 register uint32_t __regProcessStackPointer __ASM("psp");
146 return(__regProcessStackPointer);
147 }
148 #endif /* __ARMCC_VERSION */
149
150 /**
151 * @brief Set the Process Stack Pointer
152 *
153 * @param topOfProcStack Process Stack Pointer
154 *
155 * Assign the value ProcessStackPointer to the MSP
156 * (process stack pointer) Cortex processor register
157 */
158 #if (__ARMCC_VERSION < 400000)
159 extern void __set_PSP(uint32_t topOfProcStack);
160 #else /* (__ARMCC_VERSION >= 400000) */
__set_PSP(uint32_t topOfProcStack)161 static __INLINE void __set_PSP(uint32_t topOfProcStack)
162 {
163 register uint32_t __regProcessStackPointer __ASM("psp");
164 __regProcessStackPointer = topOfProcStack;
165 }
166 #endif /* __ARMCC_VERSION */
167
168 /**
169 * @brief Return the Main Stack Pointer
170 *
171 * @return Main Stack Pointer
172 *
173 * Return the current value of the MSP (main stack pointer)
174 * Cortex processor register
175 */
176 #if (__ARMCC_VERSION < 400000)
177 extern uint32_t __get_MSP(void);
178 #else /* (__ARMCC_VERSION >= 400000) */
__get_MSP(void)179 static __INLINE uint32_t __get_MSP(void)
180 {
181 register uint32_t __regMainStackPointer __ASM("msp");
182 return(__regMainStackPointer);
183 }
184 #endif /* __ARMCC_VERSION */
185
186 /**
187 * @brief Set the Main Stack Pointer
188 *
189 * @param topOfMainStack Main Stack Pointer
190 *
191 * Assign the value mainStackPointer to the MSP
192 * (main stack pointer) Cortex processor register
193 */
194 #if (__ARMCC_VERSION < 400000)
195 extern void __set_MSP(uint32_t topOfMainStack);
196 #else /* (__ARMCC_VERSION >= 400000) */
__set_MSP(uint32_t mainStackPointer)197 static __INLINE void __set_MSP(uint32_t mainStackPointer)
198 {
199 register uint32_t __regMainStackPointer __ASM("msp");
200 __regMainStackPointer = mainStackPointer;
201 }
202 #endif /* __ARMCC_VERSION */
203
204 /**
205 * @brief Return the Priority Mask value
206 *
207 * @return PriMask
208 *
209 * Return state of the priority mask bit from the priority mask register
210 */
211 #if (__ARMCC_VERSION < 400000)
212 extern uint32_t __get_PRIMASK(void);
213 #else /* (__ARMCC_VERSION >= 400000) */
__get_PRIMASK(void)214 static __INLINE uint32_t __get_PRIMASK(void)
215 {
216 register uint32_t __regPriMask __ASM("primask");
217 return(__regPriMask);
218 }
219 #endif /* __ARMCC_VERSION */
220
221 /**
222 * @brief Set the Priority Mask value
223 *
224 * @param priMask PriMask
225 *
226 * Set the priority mask bit in the priority mask register
227 */
228 #if (__ARMCC_VERSION < 400000)
229 extern void __set_PRIMASK(uint32_t priMask);
230 #else /* (__ARMCC_VERSION >= 400000) */
__set_PRIMASK(uint32_t priMask)231 static __INLINE void __set_PRIMASK(uint32_t priMask)
232 {
233 register uint32_t __regPriMask __ASM("primask");
234 __regPriMask = (priMask);
235 }
236 #endif /* __ARMCC_VERSION */
237
238
239 #if (__CORTEX_M >= 0x03)
240
241 /**
242 * @brief Enable FIQ Interrupts
243 *
244 * Enables FIQ interrupts by clearing the F-bit in the CPSR.
245 * Can only be executed in Privileged modes.
246 */
247 #define __enable_fault_irq __enable_fiq
248
249 /**
250 * @brief Disable FIQ Interrupts
251 *
252 * Disables FIQ interrupts by setting the F-bit in the CPSR.
253 * Can only be executed in Privileged modes.
254 */
255 #define __disable_fault_irq __disable_fiq
256
257 /**
258 * @brief Return the Base Priority value
259 *
260 * @return BasePriority
261 *
262 * Return the content of the base priority register
263 */
264 #if (__ARMCC_VERSION < 400000)
265 extern uint32_t __get_BASEPRI(void);
266 #else /* (__ARMCC_VERSION >= 400000) */
__get_BASEPRI(void)267 static __INLINE uint32_t __get_BASEPRI(void)
268 {
269 register uint32_t __regBasePri __ASM("basepri");
270 return(__regBasePri);
271 }
272 #endif /* __ARMCC_VERSION */
273
274 /**
275 * @brief Set the Base Priority value
276 *
277 * @param basePri BasePriority
278 *
279 * Set the base priority register
280 */
281 #if (__ARMCC_VERSION < 400000)
282 extern void __set_BASEPRI(uint32_t basePri);
283 #else /* (__ARMCC_VERSION >= 400000) */
__set_BASEPRI(uint32_t basePri)284 static __INLINE void __set_BASEPRI(uint32_t basePri)
285 {
286 register uint32_t __regBasePri __ASM("basepri");
287 __regBasePri = (basePri & 0xff);
288 }
289 #endif /* __ARMCC_VERSION */
290
291 /**
292 * @brief Return the Fault Mask value
293 *
294 * @return FaultMask
295 *
296 * Return the content of the fault mask register
297 */
298 #if (__ARMCC_VERSION < 400000)
299 extern uint32_t __get_FAULTMASK(void);
300 #else /* (__ARMCC_VERSION >= 400000) */
__get_FAULTMASK(void)301 static __INLINE uint32_t __get_FAULTMASK(void)
302 {
303 register uint32_t __regFaultMask __ASM("faultmask");
304 return(__regFaultMask);
305 }
306 #endif /* __ARMCC_VERSION */
307
308 /**
309 * @brief Set the Fault Mask value
310 *
311 * @param faultMask faultMask value
312 *
313 * Set the fault mask register
314 */
315 #if (__ARMCC_VERSION < 400000)
316 extern void __set_FAULTMASK(uint32_t faultMask);
317 #else /* (__ARMCC_VERSION >= 400000) */
__set_FAULTMASK(uint32_t faultMask)318 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
319 {
320 register uint32_t __regFaultMask __ASM("faultmask");
321 __regFaultMask = (faultMask & 1);
322 }
323 #endif /* __ARMCC_VERSION */
324
325 #endif /* (__CORTEX_M >= 0x03) */
326
327
328 #if (__CORTEX_M == 0x04)
329
330 /**
331 * @brief Return the FPSCR value
332 *
333 * @return FloatingPointStatusControlRegister
334 *
335 * Return the content of the FPSCR register
336 */
__get_FPSCR(void)337 static __INLINE uint32_t __get_FPSCR(void)
338 {
339 #if (__FPU_PRESENT == 1)
340 register uint32_t __regfpscr __ASM("fpscr");
341 return(__regfpscr);
342 #else
343 return(0);
344 #endif
345 }
346
347 /**
348 * @brief Set the FPSCR value
349 *
350 * @param fpscr FloatingPointStatusControlRegister
351 *
352 * Set the FPSCR register
353 */
__set_FPSCR(uint32_t fpscr)354 static __INLINE void __set_FPSCR(uint32_t fpscr)
355 {
356 #if (__FPU_PRESENT == 1)
357 register uint32_t __regfpscr __ASM("fpscr");
358 __regfpscr = (fpscr);
359 #endif
360 }
361
362 #endif /* (__CORTEX_M == 0x04) */
363
364
365 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
366 /* IAR iccarm specific functions */
367 #if defined (__ICCARM__)
368 #include <intrinsics.h> /* IAR Intrinsics */
369 #endif
370
371 #pragma diag_suppress=Pe940
372
373 /**
374 * @brief Enable IRQ Interrupts
375 *
376 * Enables IRQ interrupts by clearing the I-bit in the CPSR.
377 * Can only be executed in Privileged modes.
378 */
379 #define __enable_irq __enable_interrupt
380
381 /**
382 * @brief Disable IRQ Interrupts
383 *
384 * Disables IRQ interrupts by setting the I-bit in the CPSR.
385 * Can only be executed in Privileged modes.
386 */
387 #define __disable_irq __disable_interrupt
388
389 /**
390 * @brief Return the Control Register value
391 *
392 * @return Control value
393 *
394 * Return the content of the control register
395 */
396 /* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
397
398 /**
399 * @brief Set the Control Register value
400 *
401 * @param control Control value
402 *
403 * Set the control register
404 */
405 /* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
406
407 /**
408 * @brief Get IPSR Register value
409 *
410 * @return uint32_t IPSR value
411 *
412 * return the content of the IPSR register
413 */
__get_IPSR(void)414 static uint32_t __get_IPSR(void)
415 {
416 __ASM("mrs r0, ipsr");
417 }
418
419 /**
420 * @brief Get APSR Register value
421 *
422 * @return uint32_t APSR value
423 *
424 * return the content of the APSR register
425 */
426 /* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */
427
428 /**
429 * @brief Get xPSR Register value
430 *
431 * @return uint32_t xPSR value
432 *
433 * return the content of the xPSR register
434 */
__get_xPSR(void)435 static uint32_t __get_xPSR(void)
436 {
437 __ASM("mrs r0, psr"); // assembler does not know "xpsr"
438 }
439
440 /**
441 * @brief Return the Process Stack Pointer
442 *
443 * @return ProcessStackPointer
444 *
445 * Return the actual process stack pointer
446 */
__get_PSP(void)447 static uint32_t __get_PSP(void)
448 {
449 __ASM("mrs r0, psp");
450 }
451
452 /**
453 * @brief Set the Process Stack Pointer
454 *
455 * @param topOfProcStack Process Stack Pointer
456 *
457 * Assign the value ProcessStackPointer to the MSP
458 * (process stack pointer) Cortex processor register
459 */
__set_PSP(uint32_t topOfProcStack)460 static void __set_PSP(uint32_t topOfProcStack)
461 {
462 __ASM("msr psp, r0");
463 }
464
465 /**
466 * @brief Return the Main Stack Pointer
467 *
468 * @return Main Stack Pointer
469 *
470 * Return the current value of the MSP (main stack pointer)
471 * Cortex processor register
472 */
__get_MSP(void)473 static uint32_t __get_MSP(void)
474 {
475 __ASM("mrs r0, msp");
476 }
477
478 /**
479 * @brief Set the Main Stack Pointer
480 *
481 * @param topOfMainStack Main Stack Pointer
482 *
483 * Assign the value mainStackPointer to the MSP
484 * (main stack pointer) Cortex processor register
485 */
__set_MSP(uint32_t topOfMainStack)486 static void __set_MSP(uint32_t topOfMainStack)
487 {
488 __ASM("msr msp, r0");
489 }
490
491 /**
492 * @brief Return the Priority Mask value
493 *
494 * @return PriMask
495 *
496 * Return state of the priority mask bit from the priority mask register
497 */
498 /* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
499
500 /**
501 * @brief Set the Priority Mask value
502 *
503 * @param priMask PriMask
504 *
505 * Set the priority mask bit in the priority mask register
506 */
507 /* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
508
509
510 #if (__CORTEX_M >= 0x03)
511
512 /**
513 * @brief Enable FIQ Interrupts
514 *
515 * Enables FIQ interrupts by clearing the F-bit in the CPSR.
516 * Can only be executed in Privileged modes.
517 */
__enable_fault_irq()518 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
519
520 /**
521 * @brief Disable FIQ Interrupts
522 *
523 * Disables FIQ interrupts by setting the F-bit in the CPSR.
524 * Can only be executed in Privileged modes.
525 */
__disable_fault_irq()526 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
527
528 /**
529 * @brief Return the Base Priority value
530 *
531 * @return BasePriority
532 *
533 * Return the content of the base priority register
534 */
535 /* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
536
537 /**
538 * @brief Set the Base Priority value
539 *
540 * @param basePri BasePriority
541 *
542 * Set the base priority register
543 */
544 /* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
545
546 /**
547 * @brief Return the Fault Mask value
548 *
549 * @return FaultMask
550 *
551 * Return the content of the fault mask register
552 */
553 /* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
554
555 /**
556 * @brief Set the Fault Mask value
557 *
558 * @param faultMask faultMask value
559 *
560 * Set the fault mask register
561 */
562 /* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
563
564 #endif /* (__CORTEX_M >= 0x03) */
565
566
567 #if (__CORTEX_M == 0x04)
568
569 /**
570 * @brief Return the FPSCR value
571 *
572 * @return FloatingPointStatusControlRegister
573 *
574 * Return the content of the FPSCR register
575 */
__get_FPSCR(void)576 static __INLINE uint32_t __get_FPSCR(void)
577 {
578 #if (__FPU_PRESENT == 1)
579 /* not yet implemented */
580 return(0);
581 #else
582 return(0);
583 #endif
584 }
585
586 /**
587 * @brief Set the FPSCR value
588 *
589 * @param fpscr FloatingPointStatusControlRegister
590 *
591 * Set the FPSCR register
592 */
__set_FPSCR(uint32_t fpscr)593 static __INLINE void __set_FPSCR(uint32_t fpscr)
594 {
595 #if (__FPU_PRESENT == 1)
596 /* not yet implemented */
597 #endif
598 }
599
600 #endif /* (__CORTEX_M == 0x04) */
601
602 #pragma diag_default=Pe940
603
604
605 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
606 /* GNU gcc specific functions */
607 /**
608 * @brief Enable IRQ Interrupts
609 *
610 * Enables IRQ interrupts by clearing the I-bit in the CPSR.
611 * Can only be executed in Privileged modes.
612 */
__enable_irq()613 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
614
615 /**
616 * @brief Disable IRQ Interrupts
617 *
618 * Disables IRQ interrupts by setting the I-bit in the CPSR.
619 * Can only be executed in Privileged modes.
620 */
__disable_irq()621 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
622
623 /**
624 * @brief Return the Control Register value
625 *
626 * @return Control value
627 *
628 * Return the content of the control register
629 */
__get_CONTROL(void)630 static __INLINE uint32_t __get_CONTROL(void)
631 {
632 uint32_t result=0;
633
634 __ASM volatile ("MRS %0, control" : "=r" (result) );
635 return(result);
636 }
637
638 /**
639 * @brief Set the Control Register value
640 *
641 * @param control Control value
642 *
643 * Set the control register
644 */
__set_CONTROL(uint32_t control)645 static __INLINE void __set_CONTROL(uint32_t control)
646 {
647 __ASM volatile ("MSR control, %0" : : "r" (control) );
648 }
649
650 /**
651 * @brief Get IPSR Register value
652 *
653 * @return uint32_t IPSR value
654 *
655 * return the content of the IPSR register
656 */
__get_IPSR(void)657 static __INLINE uint32_t __get_IPSR(void)
658 {
659 uint32_t result=0;
660
661 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
662 return(result);
663 }
664
665 /**
666 * @brief Get APSR Register value
667 *
668 * @return uint32_t APSR value
669 *
670 * return the content of the APSR register
671 */
__get_APSR(void)672 static __INLINE uint32_t __get_APSR(void)
673 {
674 uint32_t result=0;
675
676 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
677 return(result);
678 }
679
680 /**
681 * @brief Get xPSR Register value
682 *
683 * @return uint32_t xPSR value
684 *
685 * return the content of the xPSR register
686 */
__get_xPSR(void)687 static __INLINE uint32_t __get_xPSR(void)
688 {
689 uint32_t result=0;
690
691 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
692 return(result);
693 }
694
695 /**
696 * @brief Return the Process Stack Pointer
697 *
698 * @return ProcessStackPointer
699 *
700 * Return the actual process stack pointer
701 */
702 static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) );
__get_PSP(void)703 static __INLINE uint32_t __get_PSP(void)
704 {
705 register uint32_t result __ASM ("r0") = 0;
706
707 __ASM volatile ("MRS %0, psp\n"
708 "BX lr \n" : "=r" (result) );
709 return(result);
710 }
711
712 /**
713 * @brief Set the Process Stack Pointer
714 *
715 * @param topOfProcStack Process Stack Pointer
716 *
717 * Assign the value ProcessStackPointer to the MSP
718 * (process stack pointer) Cortex processor register
719 */
720 static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
__set_PSP(uint32_t topOfProcStack)721 static __INLINE void __set_PSP(uint32_t topOfProcStack)
722 {
723 __ASM volatile ("MSR psp, %0\n"
724 "BX lr \n" : : "r" (topOfProcStack) );
725 }
726
727 /**
728 * @brief Return the Main Stack Pointer
729 *
730 * @return Main Stack Pointer
731 *
732 * Return the current value of the MSP (main stack pointer)
733 * Cortex processor register
734 */
735 static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) );
__get_MSP(void)736 static __INLINE uint32_t __get_MSP(void)
737 {
738 register uint32_t result __ASM ("r0") = 0;
739
740 __ASM volatile ("MRS %0, msp\n"
741 "BX lr \n" : "=r" (result) );
742 return(result);
743 }
744
745 /**
746 * @brief Set the Main Stack Pointer
747 *
748 * @param topOfMainStack Main Stack Pointer
749 *
750 * Assign the value mainStackPointer to the MSP
751 * (main stack pointer) Cortex processor register
752 */
753 static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
__set_MSP(uint32_t topOfMainStack)754 static __INLINE void __set_MSP(uint32_t topOfMainStack)
755 {
756 __ASM volatile ("MSR msp, %0\n"
757 "BX lr \n" : : "r" (topOfMainStack) );
758 }
759
760 /**
761 * @brief Return the Priority Mask value
762 *
763 * @return PriMask
764 *
765 * Return state of the priority mask bit from the priority mask register
766 */
__get_PRIMASK(void)767 static __INLINE uint32_t __get_PRIMASK(void)
768 {
769 uint32_t result=0;
770
771 __ASM volatile ("MRS %0, primask" : "=r" (result) );
772 return(result);
773 }
774
775 /**
776 * @brief Set the Priority Mask value
777 *
778 * @param priMask PriMask
779 *
780 * Set the priority mask bit in the priority mask register
781 */
__set_PRIMASK(uint32_t priMask)782 static __INLINE void __set_PRIMASK(uint32_t priMask)
783 {
784 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
785 }
786
787
788 #if (__CORTEX_M >= 0x03)
789
790 /**
791 * @brief Enable FIQ Interrupts
792 *
793 * Enables FIQ interrupts by clearing the F-bit in the CPSR.
794 * Can only be executed in Privileged modes.
795 */
__enable_fault_irq()796 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
797
798 /**
799 * @brief Disable FIQ Interrupts
800 *
801 * Disables FIQ interrupts by setting the F-bit in the CPSR.
802 * Can only be executed in Privileged modes.
803 */
__disable_fault_irq()804 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
805
806 /**
807 * @brief Return the Base Priority value
808 *
809 * @return BasePriority
810 *
811 * Return the content of the base priority register
812 */
__get_BASEPRI(void)813 static __INLINE uint32_t __get_BASEPRI(void)
814 {
815 uint32_t result=0;
816
817 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
818 return(result);
819 }
820
821 /**
822 * @brief Set the Base Priority value
823 *
824 * @param basePri BasePriority
825 *
826 * Set the base priority register
827 */
__set_BASEPRI(uint32_t value)828 static __INLINE void __set_BASEPRI(uint32_t value)
829 {
830 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
831 }
832
833 /**
834 * @brief Return the Fault Mask value
835 *
836 * @return FaultMask
837 *
838 * Return the content of the fault mask register
839 */
__get_FAULTMASK(void)840 static __INLINE uint32_t __get_FAULTMASK(void)
841 {
842 uint32_t result=0;
843
844 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
845 return(result);
846 }
847
848 #endif /* (__CORTEX_M >= 0x03) */
849
850 /**
851 * @brief Set the Fault Mask value
852 *
853 * @param faultMask faultMask value
854 *
855 * Set the fault mask register
856 */
__set_FAULTMASK(uint32_t faultMask)857 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
858 {
859 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
860 }
861
862
863 #if (__CORTEX_M == 0x04)
864
865 /**
866 * @brief Return the FPSCR value
867 *
868 * @return FloatingPointStatusControlRegister
869 *
870 * Return the content of the FPSCR register
871 */
__get_FPSCR(void)872 static __INLINE uint32_t __get_FPSCR(void)
873 {
874 #if (__FPU_PRESENT == 1)
875 uint32_t result=0;
876
877 __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
878 return(result);
879 #else
880 return(0);
881 #endif
882 }
883
884 /**
885 * @brief Set the FPSCR value
886 *
887 * @param fpscr FloatingPointStatusControlRegister
888 *
889 * Set the FPSCR register
890 */
__set_FPSCR(uint32_t fpscr)891 static __INLINE void __set_FPSCR(uint32_t fpscr)
892 {
893 #if (__FPU_PRESENT == 1)
894 __ASM volatile ("MSR control, %0" : : "r" (fpscr) );
895 #endif
896 }
897
898 #endif /* (__CORTEX_M == 0x04) */
899
900
901 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
902 /* TASKING carm specific functions */
903
904 /*
905 * The CMSIS functions have been implemented as intrinsics in the compiler.
906 * Please use "carm -?i" to get an up to date list of all instrinsics,
907 * Including the CMSIS ones.
908 */
909
910 #endif
911
912 #endif // __CORE_CMFUNC_H__
913