1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2006-03-13 Bernard first version 9 * 2011-05-15 lgnq modified according bernard's implementaion. 10 */ 11 12 #ifndef __FM3_UART_H__ 13 #define __FM3_UART_H__ 14 15 #include <rtthread.h> 16 #include "mb9bf506r.h" 17 18 #define SMR_SOE 0x01U 19 #define SMR_BDS 0x04U 20 #define SMR_SBL 0x08U 21 #define SMR_WUCR 0x10U 22 #define SMR_MD_UART 0x00U 23 #define SMR_MD_UART_MP 0x20U 24 #define SMR_MD_SIO 0x40U 25 #define SMR_MD_LIN 0x60U 26 #define SMR_MD_I2C 0x80U 27 28 #define SCR_TXE 0x01U 29 #define SCR_RXE 0x02U 30 #define SCR_TBIE 0x04U 31 #define SCR_TIE 0x08U 32 #define SCR_RIE 0x10U 33 #define SCR_UPGL 0x80U 34 35 #define SSR_TBI 0x01U 36 #define SSR_TDRE 0x02U 37 #define SSR_RDRF 0x04U 38 #define SSR_ORE 0x08U 39 #define SSR_FRE 0x10U 40 #define SSR_PE 0x20U 41 #define SSR_REC 0x80U 42 43 #define ESCR_P 0x08U 44 #define ESCR_PEN 0x10U 45 #define ESCR_INV 0x20U 46 #define ESCR_ESBL 0x40U 47 #define ESCR_FLWEN 0x80U 48 #define ESCR_DATABITS_8 0x00U 49 #define ESCR_DATABITS_5 0x01U 50 #define ESCR_DATABITS_6 0x02U 51 #define ESCR_DATABITS_7 0x03U 52 #define ESCR_DATABITS_9 0x04U 53 54 #define FIFO_SIZE 16 55 56 /* 57 * Enable/DISABLE Interrupt Controller 58 */ 59 /* deviation from MISRA-C:2004 Rule 19.7 */ 60 #define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) 61 #define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) 62 63 struct uart03_device 64 { 65 FM3_MFS03_UART_TypeDef *uart_regs; 66 /* irq number */ 67 IRQn_Type rx_irq; 68 IRQn_Type tx_irq; 69 }; 70 71 struct uart47_device 72 { 73 FM3_MFS47_UART_TypeDef *uart_regs; 74 /* irq number */ 75 IRQn_Type rx_irq; 76 IRQn_Type tx_irq; 77 rt_uint8_t fifo_size; 78 }; 79 80 void rt_hw_serial_init(void); 81 82 #endif 83