1 /******************************************************************************* 2 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 3 * 4 * This software is owned and published by: 5 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). 6 * 7 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 8 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. 9 * 10 * This software contains source code for use with Spansion 11 * components. This software is licensed by Spansion to be adapted only 12 * for use in systems utilizing Spansion components. Spansion shall not be 13 * responsible for misuse or illegal use of this software for devices not 14 * supported herein. Spansion is providing this software "AS IS" and will 15 * not be responsible for issues arising from incorrect user implementation 16 * of the software. 17 * 18 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, 19 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 20 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 21 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 22 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 23 * WARRANTY OF NONINFRINGEMENT. 24 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 25 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 26 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 27 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 28 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 30 * SAVINGS OR PROFITS, 31 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 32 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR 33 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 34 * FROM, THE SOFTWARE. 35 * 36 * This software may be replicated in part or whole for the licensed use, 37 * with the restriction that this Disclaimer and Copyright notice must be 38 * included with each copy of this software, whether used in part or whole, 39 * at all times. 40 */ 41 42 /******************************************************************************/ 43 /** \file system_mb9bf56xr.h 44 ** 45 ** Headerfile for FM4 system parameters 46 ** 47 ** History: 48 ** 2013-01-21 0.1 MWi AI: Unification to be done 49 ** 2013-02-06 0.2 MWi CMSIS coding restored; unifying still to be done 50 ** 2013-06-28 0.3 EH Added Trace Buffer enable definition 51 ** 2013-08-15 0.4 EH Changed APB1 Prescaler value 52 ******************************************************************************/ 53 54 #ifndef _SYSTEM_MB9ABXXX_H_ 55 #define _SYSTEM_MB9ABXXX_H_ 56 57 #ifdef __cplusplus 58 extern "C" { 59 #endif 60 61 /******************************************************************************/ 62 /* Include files */ 63 /******************************************************************************/ 64 #include <stdint.h> 65 66 /******************************************************************************/ 67 /* Global pre-processor symbols/macros ('define') */ 68 /******************************************************************************/ 69 70 /******************************************************************************/ 71 /* */ 72 /* START OF USER SETTINGS HERE */ 73 /* =========================== */ 74 /* */ 75 /* All lines with '<<<' can be set by user. */ 76 /* */ 77 /******************************************************************************/ 78 79 /** 80 ****************************************************************************** 81 ** \brief Clock Setup Enable 82 ** <i>(USER SETTING)</i> 83 ** 84 ** - 0 = No clock setup done by system_mb9xfxxx.c 85 ** - 1 = Clock setup done by system_mb9xfxxx.c 86 ******************************************************************************/ 87 #define CLOCK_SETUP 1 // <<< Define clock setup here 88 89 /** 90 ****************************************************************************** 91 ** \brief External Main Clock Frequency (in Hz, [value]ul) 92 ** <i>(USER SETTING)</i> 93 ******************************************************************************/ 94 #define __CLKMO ( 4000000ul) // <<< External 4MHz Crystal 95 96 /** 97 ****************************************************************************** 98 ** \brief External Sub Clock Frequency (in Hz, [value]ul) 99 ** <i>(USER SETTING)</i> 100 ******************************************************************************/ 101 #define __CLKSO ( 32768ul) // <<< External 32KHz Crystal 102 103 /** 104 ****************************************************************************** 105 ** \brief System Clock Mode Control Register value definition 106 ** <i>(USER SETTING)</i> 107 ** 108 ** SCM_CTL 109 ** 110 ** Bit#7-5 : RCS[2:0] 111 ** - 0 = Internal high-speed CR oscillation (default) 112 ** - 1 = Main oscillation clock 113 ** - 2 = PLL oscillation clock 114 ** - 3 = (not allowed) 115 ** - 4 = Internal low-speed CR oscillation 116 ** - 5 = Sub clock oscillation 117 ** - 6 = (not allowed) 118 ** - 7 = (not allowed) 119 ** 120 ** Bit#4 : PLLE 121 ** - 0 = Disable PLL (default) 122 ** - 1 = Enable PLL 123 ** 124 ** Bit#3 : SOSCE 125 ** - 0 = Disable sub oscillation (default) 126 ** - 1 = Enable sub oscillation 127 ** 128 ** Bit#2 : (reserved) 129 ** 130 ** Bit#1 : MOSCE 131 ** - 0 = Disable main oscillation (default) 132 ** - 1 = Enable main oscillation 133 ** 134 ** Bit#0 : (reserved) 135 ******************************************************************************/ 136 #define SCM_CTL_Val 0x00000052ul // <<< Define SCM_CTL here 137 138 /** 139 ****************************************************************************** 140 ** \brief Base Clock Prescaler Register value definition 141 ** <i>(USER SETTING)</i> 142 ** 143 ** BSC_PSR 144 ** 145 ** Bit#7-3 : (reserved) 146 ** 147 ** Bit#2-0 : BSR[2:0] 148 ** - 0 = HCLK = Master Clock 149 ** - 1 = HCLK = Master Clock / 2 150 ** - 2 = HCLK = Master Clock / 3 151 ** - 3 = HCLK = Master Clock / 4 152 ** - 4 = HCLK = Master Clock / 6 153 ** - 5 = HCLK = Master Clock / 8 154 ** - 6 = HCLK = Master Clock / 16 155 ** - 7 = (reserved) 156 ******************************************************************************/ 157 #define BSC_PSR_Val 0x00000000ul // <<< Define BSC_PSR here 158 159 /** 160 ****************************************************************************** 161 ** \brief APB0 Prescaler Register value definition 162 ** <i>(USER SETTING)</i> 163 ** 164 ** APBC0_PSR 165 ** 166 ** Bit#7-2 : (reserved) 167 ** 168 ** Bit#1-0 : BSR[2:0] 169 ** - 0 = PCLK0 = HCLK 170 ** - 1 = PCLK0 = HCLK / 2 171 ** - 2 = PCLK0 = HCLK / 4 172 ** - 3 = PCLK0 = HCLK / 8 173 ******************************************************************************/ 174 #define APBC0_PSR_Val 0x00000001UL // <<< Define APBC0_PSR here 175 176 /** 177 ****************************************************************************** 178 ** \brief APB1 Prescaler Register value definition 179 ** <i>(USER SETTING)</i> 180 ** 181 ** APBC1_PSR 182 ** 183 ** Bit#7 : APBC1EN 184 ** - 0 = Disable PCLK1 output 185 ** - 1 = Enables PCLK1 (default) 186 ** 187 ** Bit#6-5 : (reserved) 188 ** 189 ** Bit#4 : APBC1RST 190 ** - 0 = APB1 bus reset, inactive (default) 191 ** - 1 = APB1 bus reset, active 192 ** 193 ** Bit#3-2 : (reserved) 194 ** 195 ** Bit#1-0 : APBC1[2:0] 196 ** - 0 = PCLK1 = HCLK 197 ** - 1 = PCLK1 = HCLK / 2 198 ** - 2 = PCLK1 = HCLK / 4 199 ** - 3 = PCLK1 = HCLK / 8 200 ******************************************************************************/ 201 #define APBC1_PSR_Val 0x00000080ul // <<< Define APBC1_PSR here 202 203 /** 204 ****************************************************************************** 205 ** \brief APB2 Prescaler Register value definition 206 ** <i>(USER SETTING)</i> 207 ** 208 ** APBC2_PSR 209 ** 210 ** Bit#7 : APBC2EN 211 ** - 0 = Disable PCLK2 output 212 ** - 1 = Enables PCLK2 (default) 213 ** 214 ** Bit#6-5 : (reserved) 215 ** 216 ** Bit#4 : APBC2RST 217 ** - 0 = APB2 bus reset, inactive (default) 218 ** - 1 = APB2 bus reset, active 219 ** 220 ** Bit#3-2 : (reserved) 221 ** 222 ** Bit#1-0 : APBC2[1:0] 223 ** - 0 = PCLK2 = HCLK 224 ** - 1 = PCLK2 = HCLK / 2 225 ** - 2 = PCLK2 = HCLK / 4 226 ** - 3 = PCLK2 = HCLK / 8 227 ******************************************************************************/ 228 #define APBC2_PSR_Val 0x00000081ul // <<< Define APBC2_PSR here 229 230 /** 231 ****************************************************************************** 232 ** \brief Software Watchdog Clock Prescaler Register value definition 233 ** <i>(USER SETTING)</i> 234 ** 235 ** SWC_PSR 236 ** 237 ** Bit#7 : TESTB 238 ** - 0 = (not allowed) 239 ** - 1 = (always write "1" to this bit) 240 ** 241 ** Bit#6-2 : (reserved) 242 ** 243 ** Bit#1-0 : SWDS[2:0] 244 ** - 0 = SWDGOGCLK = PCLK0 245 ** - 1 = SWDGOGCLK = PCLK0 / 2 246 ** - 2 = SWDGOGCLK = PCLK0 / 4 247 ** - 3 = SWDGOGCLK = PCLK0 / 8 248 ******************************************************************************/ 249 #define SWC_PSR_Val 0x00000003ul // <<< Define SWC_PSR here 250 251 /** 252 ****************************************************************************** 253 ** \brief Trace Clock Prescaler Register value definition 254 ** <i>(USER SETTING)</i> 255 ** 256 ** TTC_PSR 257 ** 258 ** Bit#7-1 : (reserved) 259 ** 260 ** Bit#0 : TTC 261 ** - 0 = TPIUCLK = HCLK 262 ** - 1 = TPIUCLK = HCLK / 2 263 ******************************************************************************/ 264 #define TTC_PSR_Val 0x00000000ul // <<< Define TTC_PSR here 265 266 /** 267 ****************************************************************************** 268 ** \brief Clock Stabilization Wait Time Register value definition 269 ** <i>(USER SETTING)</i> 270 ** 271 ** CSW_TMR 272 ** 273 ** Bit#7 : (reserved) 274 ** 275 ** Bit#6-4 : SOWT[2:0] 276 ** - 0 = ~10.3 ms (default) 277 ** - 1 = ~20.5 ms 278 ** - 2 = ~41 ms 279 ** - 3 = ~82 ms 280 ** - 4 = ~164 ms 281 ** - 5 = ~327 ms 282 ** - 6 = ~655 ms 283 ** - 7 = ~1.31 s 284 ** 285 ** Bit#3-0 : MOWT[3:0] 286 ** - 0 = ~500 ns (default) 287 ** - 1 = ~8 us 288 ** - 2 = ~16 us 289 ** - 3 = ~32 us 290 ** - 4 = ~64 us 291 ** - 5 = ~128 us 292 ** - 6 = ~256 us 293 ** - 7 = ~512 us 294 ** - 8 = ~1.0 ms 295 ** - 9 = ~2.0 ms 296 ** - 10 = ~4.0 ms 297 ** - 11 = ~8.0 ms 298 ** - 12 = ~33.0 ms 299 ** - 13 = ~131 ms 300 ** - 14 = ~524 ms 301 ** - 15 = ~2.0 s 302 ******************************************************************************/ 303 #define CSW_TMR_Val 0x0000005Cul // <<< Define CSW_TMR here 304 305 /** 306 ****************************************************************************** 307 ** \brief PLL Clock Stabilization Wait Time Setup Register value definition 308 ** <i>(USER SETTING)</i> 309 ** 310 ** PSW_TMR 311 ** 312 ** Bit#7-5 : (reserved) 313 ** 314 ** Bit#4 : PINC 315 ** - 0 = Selects CLKMO (main oscillation) (default) 316 ** - 1 = (setting diabled) 317 ** 318 ** Bit#3 : (reserved) 319 ** 320 ** Bit#2-0 : POWT[2:0] 321 ** - 0 = ~128 us (default) 322 ** - 1 = ~256 us 323 ** - 2 = ~512 us 324 ** - 3 = ~1.02 ms 325 ** - 4 = ~2.05 ms 326 ** - 5 = ~4.10 ms 327 ** - 6 = ~8.20 ms 328 ** - 7 = ~16.40 ms 329 ******************************************************************************/ 330 #define PSW_TMR_Val 0x00000000ul // <<< Define PSW_TMR here 331 332 /** 333 ****************************************************************************** 334 ** \brief PLL Control Register 1 value definition 335 ** <i>(USER SETTING)</i> 336 ** 337 ** PLL_CTL1 338 ** 339 ** Bit#7-4 : PLLK[3:0] 340 ** - 0 = Division(PLLK) = 1/1 (default) 341 ** - 1 = Division(PLLK) = 1/2 342 ** - 2 = Division(PLLK) = 1/3 343 ** - . . . 344 ** - 15 = Division(PLLK) = 1/16 345 ** 346 ** Bit#3-0 : PLLM[3:0] 347 ** - 0 = Division(PLLM) = 1/1 (default) 348 ** - 1 = Division(PLLM) = 1/2 349 ** - 2 = Division(PLLM) = 1/3 350 ** - . . . 351 ** - 15 = Division(PLLM) = 1/16 352 ******************************************************************************/ 353 #define PLL_CTL1_Val 0x00000001ul // <<< Define PLL_CTL1 here 354 355 /** 356 ****************************************************************************** 357 ** \brief PLL Control Register 2 value definition 358 ** <i>(USER SETTING)</i> 359 ** 360 ** PLL_CTL2 361 ** 362 ** Bit#7-6 : (reserved) 363 ** 364 ** Bit#5-0 : PLLN[5:0] 365 ** - 0 = Division(PLLN) = 1/1 (default) 366 ** - 1 = Division(PLLN) = 1/2 367 ** - 2 = Division(PLLN) = 1/3 368 ** - . . . 369 ** - 63 = Division(PLLN) = 1/64 370 ******************************************************************************/ 371 #define PLL_CTL2_Val 0x00000027ul // <<< Define PLL_CTL2 here 372 373 /** 374 ****************************************************************************** 375 ** \brief Hardware Watchdog disable definition 376 ** <i>(USER SETTING)</i> 377 ** 378 ** - 0 = Hardware Watchdog enable 379 ** - 1 = Hardware Watchdog disable 380 ******************************************************************************/ 381 #define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here 382 383 /** 384 ****************************************************************************** 385 ** \brief Trimming CR 386 ** <i>(USER SETTING)</i> 387 ** 388 ** - 0 = CR is not trimmed at startup 389 ** - 1 = CR is trimmed at startup 390 ******************************************************************************/ 391 #define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here 392 393 /** 394 ****************************************************************************** 395 ** brief Trace Buffer enable definition 396 ** <i>(USER SETTING)</i> 397 ** 398 ** - 0 = Trace Buffer disable 399 ** - 1 = Trace Buffer enable 400 ******************************************************************************/ 401 #define TRACE_BUFFER_ENABLE 1 // <<< Define Trace Buffer enable here 402 403 404 /******************************************************************************/ 405 /* */ 406 /* END OF USER SETTINGS HERE */ 407 /* ========================= */ 408 /* */ 409 /******************************************************************************/ 410 411 /******************************************************************************/ 412 /* Device dependent System Clock absolute maximum ranges */ 413 /******************************************************************************/ 414 415 /** 416 ****************************************************************************** 417 ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]ul) 418 ** <i>(USER SETTING)</i> 419 ******************************************************************************/ 420 #define __CLKHC ( 4000000ul) /* Internal 4MHz CR Oscillator */ 421 422 /** 423 ****************************************************************************** 424 ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]ul) 425 ** <i>(USER SETTING)</i> 426 ******************************************************************************/ 427 #define __CLKLC ( 100000ul) /* Internal 100KHz CR Oscillator */ 428 429 /** 430 ****************************************************************************** 431 ** \brief Any case minimum Main Clock frequency (in Hz, [value]ul) 432 ** <i>(DEVICE DEPENDENT SETTING)</i> 433 ******************************************************************************/ 434 #define __CLKMOMIN ( 4000000ul) 435 436 /** 437 ****************************************************************************** 438 ** \brief Maximum Main Clock frequency using external clock (in Hz, [value]ul) 439 ** <i>(DEVICE DEPENDENT SETTING)</i> 440 ******************************************************************************/ 441 #define __CLKMOMAX ( 48000000ul) 442 443 /** 444 ****************************************************************************** 445 ** \brief Any case minimum Sub Clock frequency (in Hz, [value]ul) 446 ** <i>(DEVICE DEPENDENT SETTING)</i> 447 ******************************************************************************/ 448 #define __CLKSOMIN ( 32000ul) 449 450 /** 451 ****************************************************************************** 452 ** \brief Maximum Sub Clock frequency using external clock (in Hz, [value]ul) 453 ** <i>(DEVICE DEPENDENT SETTING)</i> 454 ******************************************************************************/ 455 #define __CLKSOMAX ( 100000ul) 456 457 /** 458 ****************************************************************************** 459 ** \brief Absolute minimum PLL input frequency (in Hz, [value]ul) 460 ** <i>(DEVICE DEPENDENT SETTING)</i> 461 ******************************************************************************/ 462 #define __PLLCLKINMIN ( 4000000ul) 463 464 /** 465 ****************************************************************************** 466 ** \brief Absolute maximum PLL input frequency (in Hz, [value]ul) 467 ** <i>(DEVICE DEPENDENT SETTING)</i> 468 ******************************************************************************/ 469 #define __PLLCLKINMAX ( 16000000ul) 470 471 /** 472 ****************************************************************************** 473 ** \brief Absolute minimum PLL oscillation frequency (in Hz, [value]ul) 474 ** <i>(DEVICE DEPENDENT SETTING)</i> 475 ******************************************************************************/ 476 #define __PLLCLKMIN (200000000ul) 477 478 /** 479 ****************************************************************************** 480 ** \brief Absolute maximum PLL oscillation frequency (in Hz, [value]ul) 481 ** <i>(DEVICE DEPENDENT SETTING)</i> 482 ******************************************************************************/ 483 #define __PLLCLKMAX (320000000ul) 484 485 /** 486 ****************************************************************************** 487 ** \brief Absolute maximum System Clock frequency (HCLK) (in Hz, [value]ul) 488 ** <i>(DEVICE DEPENDENT SETTING)</i> 489 ******************************************************************************/ 490 #define __HCLKMAX (160000000ul) 491 492 /** 493 ****************************************************************************** 494 ** \brief Preprocessor macro for checking range (clock settings). 495 ** 496 ** \return 0 Within range 497 ** \return 1 Out of range 498 ******************************************************************************/ 499 #define CHECK_RANGE(val, min, max) (((val) < (min)) || ((val) > (max))) 500 501 /** 502 ****************************************************************************** 503 ** \brief Preprocessor macro for checking bits with mask (clock settings). 504 ** Prevents from setting reserved bits by mistake. 505 ** 506 ** \return 0 All bits within mask 507 ** \return 1 One or more bits out of mask 508 ******************************************************************************/ 509 #define CHECK_RSVD(val, mask) ((val) & (mask)) 510 511 512 /******************************************************************************/ 513 /* Check register settings */ 514 /******************************************************************************/ 515 #if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FAul)) 516 #error "SCM_CTL: Invalid values of reserved bits!" 517 #endif 518 519 #if ((SCM_CTL_Val & 0xE0ul) == 0x40ul) && ((SCM_CTL_Val & 0x10ul) != 0x10ul) 520 #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" 521 #endif 522 523 #if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007Ful)) 524 #error "CSW_TMR: Invalid values of reserved bits!" 525 #endif 526 527 #if ((SCM_CTL_Val & 0x10ul)) /* if PLL is used */ 528 #if (CHECK_RSVD((PSW_TMR_Val), ~0x00000017ul)) 529 #error "PSW_TMR: Invalid values of reserved bits!" 530 #endif 531 532 #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FFul)) 533 #error "PLL_CTL1: Invalid values of reserved bits!" 534 #endif 535 536 #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003Ful)) 537 #error "PLL_CTL2: Invalid values of reserved bits!" 538 #endif 539 #endif 540 541 #if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007ul)) 542 #error "BSC_PSR: Invalid values of reserved bits!" 543 #endif 544 545 #if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003ul)) 546 #error "APBC0_PSR: Invalid values of reserved bits!" 547 #endif 548 549 #if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000093ul)) 550 #error "APBC1_PSR: Invalid values of reserved bits!" 551 #endif 552 553 #if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000093ul)) 554 #error "APBC2_PSR: Invalid values of reserved bits!" 555 #endif 556 557 #if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003ul)) 558 #error "SWC_PSR: Invalid values of reserved bits!" 559 #endif 560 561 #if (CHECK_RSVD((TTC_PSR_Val), ~0x00000003ul)) 562 #error "TTC_PSR: Invalid values of reserved bits!" 563 #endif 564 565 /******************************************************************************/ 566 /* Define clocks with checking settings */ 567 /******************************************************************************/ 568 569 /** 570 ****************************************************************************** 571 ** \brief Calculate PLL K factor from settings 572 ******************************************************************************/ 573 #define __PLLK (((PLL_CTL1_Val >> 4ul) & 0x0Ful) + 1ul) 574 575 /** 576 ****************************************************************************** 577 ** \brief Calculate PLL N factor from settings 578 ******************************************************************************/ 579 #define __PLLN (((PLL_CTL2_Val ) & 0x3Ful) + 1ul) 580 581 /** 582 ****************************************************************************** 583 ** \brief Calculate PLL M factor from settings 584 ******************************************************************************/ 585 #define __PLLM (((PLL_CTL1_Val ) & 0x0Ful) + 1ul) 586 587 /** 588 ****************************************************************************** 589 ** \brief Calculate PLL output frequency from settings 590 ******************************************************************************/ 591 #define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) 592 593 /******************************************************************************/ 594 /* Determine core clock frequency according to settings */ 595 /******************************************************************************/ 596 597 /** 598 ****************************************************************************** 599 ** \brief Define Master Clock from settings 600 ******************************************************************************/ 601 #if (((SCM_CTL_Val >> 5ul) & 0x07UL) == 0ul) 602 #define __MASTERCLK (__CLKHC) 603 #elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 1ul) 604 #define __MASTERCLK (__CLKMO) 605 #elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 2ul) 606 #define __MASTERCLK (__PLLCLK) 607 #elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 4ul) 608 #define __MASTERCLK (__CLKLC) 609 #elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 5ul) 610 #define __MASTERCLK (__CLKSO) 611 #else 612 #define __MASTERCLK (0UL) 613 #endif 614 615 /** 616 ****************************************************************************** 617 ** \brief Define System Clock Frequency (Core Clock) from settings 618 ******************************************************************************/ 619 #if ((BSC_PSR_Val & 0x07UL) == 0ul) 620 #define __HCLK (__MASTERCLK / 1ul) 621 #elif ((BSC_PSR_Val & 0x07UL) == 1ul) 622 #define __HCLK (__MASTERCLK / 2ul) 623 #elif ((BSC_PSR_Val & 0x07UL) == 2ul) 624 #define __HCLK (__MASTERCLK / 3ul) 625 #elif ((BSC_PSR_Val & 0x07UL) == 3ul) 626 #define __HCLK (__MASTERCLK / 4ul) 627 #elif ((BSC_PSR_Val & 0x07UL) == 4ul) 628 #define __HCLK (__MASTERCLK / 6ul) 629 #elif ((BSC_PSR_Val & 0x07UL) == 5ul) 630 #define __HCLK (__MASTERCLK / 8ul) 631 #elif ((BSC_PSR_Val & 0x07UL) == 6ul) 632 #define __HCLK (__MASTERCLK /16ul) 633 #else 634 #define __HCLK (0ul) 635 #endif 636 637 /******************************************************************************/ 638 /* HCLK range check */ 639 /******************************************************************************/ 640 #if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX)) 641 #error "Main Oscillator Clock (CLKMO) out of range!" 642 #endif 643 644 #if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX)) 645 #error "Sub Oscillator Clock (CLKMO) out of range!" 646 #endif 647 648 #if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX)) 649 #error "PLL input frequency out of range!" 650 #endif 651 652 #if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX)) 653 #error "PLL oscillation frequency out of range!" 654 #endif 655 656 #if (CHECK_RANGE(__HCLK, 0UL, __HCLKMAX)) 657 #error "System Clock (HCLK) out of range!" 658 #endif 659 660 /******************************************************************************/ 661 /* Global function prototypes ('extern', definition in C source) */ 662 /******************************************************************************/ 663 664 extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) 665 666 extern void SystemInit (void); // Initialize the system 667 668 extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable 669 670 #ifdef __cplusplus 671 } 672 #endif 673 674 #endif /* _SYSTEM_MB9ABXXX_H_ */ 675