1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-12-04 zylx The first version for STM32F4xx 9 * 2023-08-20 yuanzihao adapter gd32f4xx 10 */ 11 12 #ifndef __SDRAM_PORT_H__ 13 #define __SDRAM_PORT_H__ 14 15 /* parameters for sdram peripheral */ 16 #define SDRAM_DEVICE EXMC_SDRAM_DEVICE0 17 /* Bank1 or Bank2 */ 18 #define SDRAM_TARGET_BANK 1 19 /* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */ 20 #define SDRAM_BANK_ADDR ((uint32_t)0XC0000000) 21 /* data width: 8, 16, 32 */ 22 #define SDRAM_DATA_WIDTH_IN_NUMBER 16 23 #define SDRAM_DATA_WIDTH EXMC_SDRAM_DATABUS_WIDTH_16B 24 /* column bit numbers: 8, 9, 10, 11 */ 25 #define SDRAM_COLUMN_BITS EXMC_SDRAM_COW_ADDRESS_9 26 /* row bit numbers: 11, 12, 13 */ 27 #define SDRAM_ROW_BITS EXMC_SDRAM_ROW_ADDRESS_13 28 /* cas latency clock number: 1, 2, 3 */ 29 #define SDRAM_CAS_LATENCY EXMC_CAS_LATENCY_3_SDCLK 30 /* read pipe delay: 0, 1, 2 */ 31 #define SDRAM_RPIPE_DELAY EXMC_PIPELINE_DELAY_2_HCLK 32 /* clock divid: 2, 3 */ 33 #define SDCLOCK_PERIOD EXMC_SDCLK_PERIODS_3_HCLK 34 /* refresh rate counter */ 35 #define SDRAM_REFRESH_COUNT ((uint32_t)0x02A5) 36 #define SDRAM_SIZE ((uint32_t)0x2000000) 37 #define SDRAM_TIMEOUT ((uint32_t)0x0000FFFF) 38 39 /* Timing configuration for W9825G6KH-6 */ 40 /* 100 MHz of HCKL3 clock frequency (200MHz/2) */ 41 /* TMRD: 2 Clock cycles */ 42 #define LOADTOACTIVEDELAY 2 43 /* TXSR: 8x10ns */ 44 #define EXITSELFREFRESHDELAY 8 45 /* TRAS: 5x10ns */ 46 #define SELFREFRESHTIME 7 47 /* TRC: 7x10ns */ 48 #define ROWCYCLEDELAY 5 49 /* TWR: 2 Clock cycles */ 50 #define WRITERECOVERYTIME 2 51 /* TRP: 2x10ns */ 52 #define RPDELAY 3 53 /* TRCD: 2x10ns */ 54 #define RCDDELAY 3 55 56 /* memory mode register */ 57 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) 58 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) 59 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) 60 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) 61 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) 62 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) 63 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) 64 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) 65 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) 66 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 67 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) 68 69 #endif 70