1 /* 2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-02-20 CDT first version 9 */ 10 11 #ifndef __IRQ_CONFIG_H__ 12 #define __IRQ_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn 21 #define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 22 #define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn 23 #define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 24 #define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn 25 #define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 26 #define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn 27 #define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 28 #define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn 29 #define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 30 #define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn 31 #define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 32 #define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn 33 #define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 34 #define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn 35 #define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 36 #define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn 37 #define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 38 #define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn 39 #define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 40 #define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn 41 #define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 42 #define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn 43 #define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 44 #define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn 45 #define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 46 #define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn 47 #define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 48 #define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn 49 #define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 50 #define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn 51 #define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 52 53 /* DMA1 ch0 */ 54 #define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn 55 #define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 56 /* DMA1 ch1 */ 57 #define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn 58 #define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 59 /* DMA1 ch2 */ 60 #define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn 61 #define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 62 /* DMA1 ch3 */ 63 #define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn 64 #define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 65 /* DMA1 ch4 */ 66 #define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn 67 #define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 68 /* DMA1 ch5 */ 69 #define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn 70 #define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 71 /* DMA1 ch6 */ 72 #define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn 73 #define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 74 /* DMA1 ch7 */ 75 #define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn 76 #define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 77 78 #if defined(BSP_USING_UART1) 79 #define BSP_UART1_IRQ_NUM USART1_IRQn 80 #define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 81 82 #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ 83 defined(RT_USING_SERIAL_V2) 84 #define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn 85 #define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 86 #endif 87 #endif /* BSP_USING_UART1 */ 88 89 #if defined(BSP_USING_UART2) 90 #define BSP_UART2_IRQ_NUM USART2_IRQn 91 #define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 92 93 #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ 94 defined(RT_USING_SERIAL_V2) 95 #define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn 96 #define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 97 #endif 98 #endif /* BSP_USING_UART2 */ 99 100 #if defined(BSP_USING_UART3) 101 #define BSP_UART3_IRQ_NUM USART3_IRQn 102 #define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 103 104 #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)) || \ 105 defined(RT_USING_SERIAL_V2) 106 #define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn 107 #define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 108 #endif 109 #endif /* BSP_USING_UART3 */ 110 111 #if defined(BSP_USING_UART4) 112 #define BSP_UART4_IRQ_NUM USART4_IRQn 113 #define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 114 115 #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ 116 defined(RT_USING_SERIAL_V2) 117 #define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn 118 #define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 119 #endif 120 #endif /* BSP_USING_UART4 */ 121 122 #if defined(BSP_USING_SPI1) 123 #define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn 124 #define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 125 #endif 126 127 #if defined(BSP_USING_SPI2) 128 #define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn 129 #define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 130 #endif 131 132 #if defined(BSP_USING_SPI3) 133 #define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn 134 #define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 135 #endif 136 137 #if defined (BSP_USING_QSPI) 138 #define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn 139 #define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 140 #endif /* BSP_USING_QSPI */ 141 142 #if defined(BSP_USING_TMRA_1) 143 #define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn 144 #define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 145 #endif/* BSP_USING_TMRA_1 */ 146 147 #if defined(BSP_USING_TMRA_2) 148 #define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn 149 #define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 150 #endif/* BSP_USING_TMRA_2 */ 151 152 #if defined(BSP_USING_TMRA_3) 153 #define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn 154 #define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 155 #endif/* BSP_USING_TMRA_3 */ 156 157 #if defined(BSP_USING_TMRA_4) 158 #define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn 159 #define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 160 #endif/* BSP_USING_TMRA_4 */ 161 162 #if defined(BSP_USING_TMRA_5) 163 #define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn 164 #define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 165 #endif/* BSP_USING_TMRA_5 */ 166 167 #if defined(BSP_USING_MCAN1) 168 #define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn 169 #define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 170 171 #define BSP_MCAN1_INT1_IRQ_NUM MCAN1_INT1_IRQn 172 #define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 173 #endif/* BSP_USING_MCAN1 */ 174 175 #if defined(BSP_USING_MCAN2) 176 #define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn 177 #define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 178 179 #define BSP_MCAN2_INT1_IRQ_NUM MCAN2_INT1_IRQn 180 #define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 181 #endif/* BSP_USING_MCAN2 */ 182 183 #if defined(RT_USING_ALARM) 184 #define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn 185 #define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 186 #endif/* RT_USING_ALARM */ 187 188 #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) 189 #define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn 190 #define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 191 #define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn 192 #define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 193 #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ 194 #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) 195 #define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn 196 #define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 197 #define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn 198 #define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 199 #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ 200 #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) 201 #define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn 202 #define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 203 #define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn 204 #define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 205 #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ 206 #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) 207 #define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn 208 #define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 209 #define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn 210 #define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 211 #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ 212 #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) 213 #define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn 214 #define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 215 #define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn 216 #define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 217 #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ 218 219 #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) 220 #define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn 221 #define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 222 #define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn 223 #define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 224 #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ 225 #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) 226 #define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn 227 #define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 228 #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn 229 #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT 230 #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ 231 232 #ifdef __cplusplus 233 } 234 #endif 235 236 #endif /* __IRQ_CONFIG_H__ */ 237