1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 * 7 * Change Logs: 8 * Date Author Notes 9 * 2024-02-20 CDT first version 10 */ 11 12 #ifndef __DMA_CONFIG_H__ 13 #define __DMA_CONFIG_H__ 14 15 #include <rtthread.h> 16 #include "irq_config.h" 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /* DMA1 ch0 */ 23 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 24 #define SPI1_RX_DMA_INSTANCE CM_DMA1 25 #define SPI1_RX_DMA_CHANNEL DMA_CH0 26 #define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 27 #define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 28 #define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 29 #define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 30 #define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 31 #define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 32 33 #elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 34 #define SPI3_RX_DMA_INSTANCE CM_DMA1 35 #define SPI3_RX_DMA_CHANNEL DMA_CH0 36 #define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 37 #define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 38 #define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 39 #define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 40 #define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 41 #define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 42 43 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) 44 #define I2C1_TX_DMA_INSTANCE CM_DMA1 45 #define I2C1_TX_DMA_CHANNEL DMA_CH0 46 #define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 47 #define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 48 #define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 49 #define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 50 #define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 51 #define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 52 #endif 53 54 /* DMA1 ch1 */ 55 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 56 #define SPI1_TX_DMA_INSTANCE CM_DMA1 57 #define SPI1_TX_DMA_CHANNEL DMA_CH1 58 #define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 59 #define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 60 #define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 61 #define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 62 #define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 63 #define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 64 65 #elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 66 #define SPI3_TX_DMA_INSTANCE CM_DMA1 67 #define SPI3_TX_DMA_CHANNEL DMA_CH1 68 #define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 69 #define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 70 #define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 71 #define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 72 #define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 73 #define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 74 75 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) 76 #define I2C1_RX_DMA_INSTANCE CM_DMA1 77 #define I2C1_RX_DMA_CHANNEL DMA_CH1 78 #define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 79 #define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 80 #define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 81 #define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 82 #define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 83 #define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 84 #endif 85 86 /* DMA1 ch2 */ 87 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 88 #define SPI2_RX_DMA_INSTANCE CM_DMA1 89 #define SPI2_RX_DMA_CHANNEL DMA_CH2 90 #define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 91 #define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 92 #define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 93 #define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM 94 #define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO 95 #define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 96 97 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) 98 #define I2C2_TX_DMA_INSTANCE CM_DMA1 99 #define I2C2_TX_DMA_CHANNEL DMA_CH2 100 #define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 101 #define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 102 #define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 103 #define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM 104 #define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO 105 #define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 106 #endif 107 108 /* DMA1 ch3 */ 109 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 110 #define SPI2_TX_DMA_INSTANCE CM_DMA1 111 #define SPI2_TX_DMA_CHANNEL DMA_CH3 112 #define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 113 #define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 114 #define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 115 #define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 116 #define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 117 #define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 118 119 120 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) 121 #define I2C2_RX_DMA_INSTANCE CM_DMA1 122 #define I2C2_RX_DMA_CHANNEL DMA_CH3 123 #define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 124 #define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 125 #define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 126 #define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 127 #define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 128 #define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 129 130 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) 131 #define ADC1_EOCA_DMA_INSTANCE CM_DMA1 132 #define ADC1_EOCA_DMA_CHANNEL DMA_CH3 133 #define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 134 #define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 135 #define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 136 #define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 137 #define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 138 #define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 139 140 #endif 141 142 /* DMA1 ch4 */ 143 #if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) 144 #define UART5_RX_DMA_INSTANCE CM_DMA1 145 #define UART5_RX_DMA_CHANNEL DMA_CH4 146 #define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 147 #define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4 148 #define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 149 #define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM 150 #define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO 151 #define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 152 153 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) 154 #define ADC2_EOCA_DMA_INSTANCE CM_DMA1 155 #define ADC2_EOCA_DMA_CHANNEL DMA_CH4 156 #define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 157 #define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 158 #define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 159 #define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM 160 #define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO 161 #define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 162 #endif 163 164 /* DMA1 ch5 */ 165 #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) 166 #define UART5_TX_DMA_INSTANCE CM_DMA1 167 #define UART5_TX_DMA_CHANNEL DMA_CH5 168 #define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 169 #define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5 170 #define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 171 #define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM 172 #define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO 173 #define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 174 175 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) 176 #define ADC3_EOCA_DMA_INSTANCE CM_DMA1 177 #define ADC3_EOCA_DMA_CHANNEL DMA_CH5 178 #define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 179 #define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 180 #define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 181 #define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM 182 #define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO 183 #define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 184 #endif 185 186 /* DMA2 ch0 */ 187 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 188 #define UART1_RX_DMA_INSTANCE CM_DMA2 189 #define UART1_RX_DMA_CHANNEL DMA_CH0 190 #define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 191 #define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 192 #define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 193 #define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM 194 #define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO 195 #define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 196 197 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) 198 #define QSPI_DMA_INSTANCE CM_DMA2 199 #define QSPI_DMA_CHANNEL DMA_CH0 200 #define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 201 #define QSPI_DMA_TRIG_SELECT AOS_DMA2_0 202 #define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 203 #define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM 204 #define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO 205 #define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0 206 #endif 207 208 /* DMA2 ch1 */ 209 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 210 #define UART1_TX_DMA_INSTANCE CM_DMA2 211 #define UART1_TX_DMA_CHANNEL DMA_CH1 212 #define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 213 #define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 214 #define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 215 #define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM 216 #define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO 217 #define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 218 #endif 219 220 /* DMA2 ch2 */ 221 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 222 #define UART2_RX_DMA_INSTANCE CM_DMA2 223 #define UART2_RX_DMA_CHANNEL DMA_CH2 224 #define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 225 #define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 226 #define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 227 #define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM 228 #define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO 229 #define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 230 #endif 231 232 /* DMA2 ch3 */ 233 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 234 #define UART2_TX_DMA_INSTANCE CM_DMA2 235 #define UART2_TX_DMA_CHANNEL DMA_CH3 236 #define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 237 #define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 238 #define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 239 #define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM 240 #define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO 241 #define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 242 #endif 243 244 /* DMA2 ch4 */ 245 #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) 246 #define UART4_RX_DMA_INSTANCE CM_DMA2 247 #define UART4_RX_DMA_CHANNEL DMA_CH4 248 #define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 249 #define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4 250 #define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 251 #define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM 252 #define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO 253 #define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 254 #endif 255 256 /* DMA2 ch5 */ 257 #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) 258 #define UART4_TX_DMA_INSTANCE CM_DMA2 259 #define UART4_TX_DMA_CHANNEL DMA_CH5 260 #define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 261 #define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5 262 #define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 263 #define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM 264 #define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO 265 #define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 266 #endif 267 268 #ifdef __cplusplus 269 } 270 #endif 271 272 273 #endif /* __DMA_CONFIG_H__ */ 274