1 /* 2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-02-20 CDT first version 9 */ 10 11 #ifndef __ADC_CONFIG_H__ 12 #define __ADC_CONFIG_H__ 13 14 #include <rtthread.h> 15 #include "irq_config.h" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #ifdef BSP_USING_ADC1 22 #ifndef ADC1_INIT_PARAMS 23 #define ADC1_INIT_PARAMS \ 24 { \ 25 .name = "adc1", \ 26 .vref = 3300, \ 27 .resolution = ADC_RESOLUTION_12BIT, \ 28 .data_align = ADC_DATAALIGN_RIGHT, \ 29 .eoc_poll_time_max = 100, \ 30 .hard_trig_enable = RT_FALSE, \ 31 .hard_trig_src = ADC_HARDTRIG_EVT0, \ 32 .internal_trig0_comtrg0_enable = RT_FALSE, \ 33 .internal_trig0_comtrg1_enable = RT_FALSE, \ 34 .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ 35 .internal_trig1_comtrg0_enable = RT_FALSE, \ 36 .internal_trig1_comtrg1_enable = RT_FALSE, \ 37 .internal_trig1_sel = EVT_SRC_MAX, \ 38 .continue_conv_mode_enable = RT_FALSE, \ 39 .data_reg_auto_clear = RT_TRUE, \ 40 } 41 #endif /* ADC1_INIT_PARAMS */ 42 43 #if defined (BSP_ADC1_USING_DMA) 44 #ifndef ADC1_EOCA_DMA_CONFIG 45 #define ADC1_EOCA_DMA_CONFIG \ 46 { \ 47 .Instance = ADC1_EOCA_DMA_INSTANCE, \ 48 .channel = ADC1_EOCA_DMA_CHANNEL, \ 49 .clock = ADC1_EOCA_DMA_CLOCK, \ 50 .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ 51 .trigger_event = EVT_SRC_ADC1_EOCA, \ 52 .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ 53 .irq_config = \ 54 { \ 55 .irq_num = ADC1_EOCA_DMA_IRQn, \ 56 .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ 57 .int_src = ADC1_EOCA_DMA_INT_SRC, \ 58 }, \ 59 } 60 #endif /* ADC1_EOCA_DMA_CONFIG */ 61 #endif /* BSP_ADC1_USING_DMA */ 62 #endif /* BSP_USING_ADC1 */ 63 64 #ifdef BSP_USING_ADC2 65 #ifndef ADC2_INIT_PARAMS 66 #define ADC2_INIT_PARAMS \ 67 { \ 68 .name = "adc2", \ 69 .vref = 3300, \ 70 .resolution = ADC_RESOLUTION_12BIT, \ 71 .data_align = ADC_DATAALIGN_RIGHT, \ 72 .eoc_poll_time_max = 100, \ 73 .hard_trig_enable = RT_FALSE, \ 74 .hard_trig_src = ADC_HARDTRIG_EVT0, \ 75 .internal_trig0_comtrg0_enable = RT_FALSE, \ 76 .internal_trig0_comtrg1_enable = RT_FALSE, \ 77 .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ 78 .internal_trig1_comtrg0_enable = RT_FALSE, \ 79 .internal_trig1_comtrg1_enable = RT_FALSE, \ 80 .internal_trig1_sel = EVT_SRC_MAX, \ 81 .continue_conv_mode_enable = RT_FALSE, \ 82 .data_reg_auto_clear = RT_TRUE, \ 83 } 84 #endif /* ADC2_INIT_PARAMS */ 85 86 #if defined (BSP_ADC2_USING_DMA) 87 #ifndef ADC2_EOCA_DMA_CONFIG 88 #define ADC2_EOCA_DMA_CONFIG \ 89 { \ 90 .Instance = ADC2_EOCA_DMA_INSTANCE, \ 91 .channel = ADC2_EOCA_DMA_CHANNEL, \ 92 .clock = ADC2_EOCA_DMA_CLOCK, \ 93 .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ 94 .trigger_event = EVT_SRC_ADC2_EOCA, \ 95 .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ 96 .irq_config = \ 97 { \ 98 .irq_num = ADC2_EOCA_DMA_IRQn, \ 99 .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ 100 .int_src = ADC2_EOCA_DMA_INT_SRC, \ 101 }, \ 102 } 103 #endif /* ADC2_EOCA_DMA_CONFIG */ 104 #endif /* BSP_ADC2_USING_DMA */ 105 #endif /* BSP_USING_ADC2 */ 106 107 #ifdef BSP_USING_ADC3 108 #ifndef ADC3_INIT_PARAMS 109 #define ADC3_INIT_PARAMS \ 110 { \ 111 .name = "adc3", \ 112 .vref = 3300, \ 113 .resolution = ADC_RESOLUTION_12BIT, \ 114 .data_align = ADC_DATAALIGN_RIGHT, \ 115 .eoc_poll_time_max = 100, \ 116 .hard_trig_enable = RT_FALSE, \ 117 .hard_trig_src = ADC_HARDTRIG_EVT0, \ 118 .internal_trig0_comtrg0_enable = RT_FALSE, \ 119 .internal_trig0_comtrg1_enable = RT_FALSE, \ 120 .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ 121 .internal_trig1_comtrg0_enable = RT_FALSE, \ 122 .internal_trig1_comtrg1_enable = RT_FALSE, \ 123 .internal_trig1_sel = EVT_SRC_MAX, \ 124 .continue_conv_mode_enable = RT_FALSE, \ 125 .data_reg_auto_clear = RT_TRUE, \ 126 } 127 #endif /* ADC3_INIT_PARAMS */ 128 129 #if defined (BSP_ADC3_USING_DMA) 130 #ifndef ADC3_EOCA_DMA_CONFIG 131 #define ADC3_EOCA_DMA_CONFIG \ 132 { \ 133 .Instance = ADC3_EOCA_DMA_INSTANCE, \ 134 .channel = ADC3_EOCA_DMA_CHANNEL, \ 135 .clock = ADC3_EOCA_DMA_CLOCK, \ 136 .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ 137 .trigger_event = EVT_SRC_ADC3_EOCA, \ 138 .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ 139 .irq_config = \ 140 { \ 141 .irq_num = ADC3_EOCA_DMA_IRQn, \ 142 .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ 143 .int_src = ADC3_EOCA_DMA_INT_SRC, \ 144 }, \ 145 } 146 #endif /* ADC3_EOCA_DMA_CONFIG */ 147 #endif /* BSP_ADC3_USING_DMA */ 148 #endif /* BSP_USING_ADC3 */ 149 150 #ifdef __cplusplus 151 } 152 #endif 153 154 #endif /* __ADC_CONFIG_H__ */ 155