1 /* 2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-04-28 CDT first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 #include "irq_config.h" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 ch0 */ 22 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 23 #define SPI1_RX_DMA_INSTANCE CM_DMA1 24 #define SPI1_RX_DMA_CHANNEL DMA_CH0 25 #define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 26 #define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 27 #define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 28 #define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 29 #define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 30 #define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 31 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) 32 #define SDIO1_RX_DMA_INSTANCE CM_DMA1 33 #define SDIO1_RX_DMA_CHANNEL DMA_CH0 34 #define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 35 #define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 36 #define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 37 #define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 38 #define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 39 #define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 40 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) 41 #define I2C1_TX_DMA_INSTANCE CM_DMA1 42 #define I2C1_TX_DMA_CHANNEL DMA_CH0 43 #define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 44 #define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 45 #define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 46 #define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 47 #define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 48 #define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 49 #endif 50 51 /* DMA1 ch1 */ 52 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 53 #define SPI1_TX_DMA_INSTANCE CM_DMA1 54 #define SPI1_TX_DMA_CHANNEL DMA_CH1 55 #define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 56 #define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 57 #define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 58 #define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 59 #define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 60 #define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 61 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) 62 #define SDIO1_TX_DMA_INSTANCE CM_DMA1 63 #define SDIO1_TX_DMA_CHANNEL DMA_CH1 64 #define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 65 #define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 66 #define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 67 #define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 68 #define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 69 #define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 70 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) 71 #define I2C1_RX_DMA_INSTANCE CM_DMA1 72 #define I2C1_RX_DMA_CHANNEL DMA_CH1 73 #define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 74 #define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 75 #define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 76 #define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 77 #define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 78 #define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 79 #endif 80 81 /* DMA1 ch2 */ 82 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) 83 #define SPI2_RX_DMA_INSTANCE CM_DMA1 84 #define SPI2_RX_DMA_CHANNEL DMA_CH2 85 #define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 86 #define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 87 #define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 88 #define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM 89 #define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO 90 #define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 91 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) 92 #define SDIO2_RX_DMA_INSTANCE CM_DMA1 93 #define SDIO2_RX_DMA_CHANNEL DMA_CH2 94 #define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 95 #define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 96 #define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 97 #define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM 98 #define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO 99 #define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 100 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) 101 #define I2C2_TX_DMA_INSTANCE CM_DMA1 102 #define I2C2_TX_DMA_CHANNEL DMA_CH2 103 #define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 104 #define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 105 #define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 106 #define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM 107 #define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO 108 #define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 109 #endif 110 111 /* DMA1 ch3 */ 112 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) 113 #define SPI2_TX_DMA_INSTANCE CM_DMA1 114 #define SPI2_TX_DMA_CHANNEL DMA_CH3 115 #define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 116 #define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 117 #define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 118 #define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 119 #define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 120 #define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 121 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) 122 #define SDIO2_TX_DMA_INSTANCE CM_DMA1 123 #define SDIO2_TX_DMA_CHANNEL DMA_CH3 124 #define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 125 #define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 126 #define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 127 #define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 128 #define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 129 #define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 130 #elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) 131 #define QSPI_DMA_INSTANCE CM_DMA1 132 #define QSPI_DMA_CHANNEL DMA_CH3 133 #define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 134 #define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 135 #define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 136 #define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 137 #define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 138 #define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 139 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) 140 #define I2C2_RX_DMA_INSTANCE CM_DMA1 141 #define I2C2_RX_DMA_CHANNEL DMA_CH3 142 #define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 143 #define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 144 #define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 145 #define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 146 #define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 147 #define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 148 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) 149 #define ADC1_EOCA_DMA_INSTANCE CM_DMA1 150 #define ADC1_EOCA_DMA_CHANNEL DMA_CH3 151 #define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 152 #define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 153 #define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 154 #define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 155 #define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 156 #define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 157 #endif 158 159 /* DMA1 ch4 */ 160 #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) 161 #define SPI3_RX_DMA_INSTANCE CM_DMA1 162 #define SPI3_RX_DMA_CHANNEL DMA_CH4 163 #define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 164 #define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 165 #define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 166 #define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM 167 #define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO 168 #define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 169 #elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) 170 #define I2C3_TX_DMA_INSTANCE CM_DMA1 171 #define I2C3_TX_DMA_CHANNEL DMA_CH4 172 #define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 173 #define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 174 #define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 175 #define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM 176 #define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO 177 #define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 178 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) 179 #define ADC2_EOCA_DMA_INSTANCE CM_DMA1 180 #define ADC2_EOCA_DMA_CHANNEL DMA_CH4 181 #define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 182 #define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 183 #define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 184 #define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM 185 #define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO 186 #define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 187 #endif 188 189 /* DMA1 ch5 */ 190 #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) 191 #define SPI3_TX_DMA_INSTANCE CM_DMA1 192 #define SPI3_TX_DMA_CHANNEL DMA_CH5 193 #define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 194 #define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 195 #define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 196 #define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM 197 #define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO 198 #define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 199 #elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) 200 #define I2C3_RX_DMA_INSTANCE CM_DMA1 201 #define I2C3_RX_DMA_CHANNEL DMA_CH5 202 #define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 203 #define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 204 #define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 205 #define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM 206 #define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO 207 #define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 208 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) 209 #define ADC3_EOCA_DMA_INSTANCE CM_DMA1 210 #define ADC3_EOCA_DMA_CHANNEL DMA_CH5 211 #define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 212 #define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 213 #define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 214 #define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM 215 #define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO 216 #define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 217 #endif 218 219 /* DMA1 ch6 */ 220 #if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) 221 #define SPI4_RX_DMA_INSTANCE CM_DMA1 222 #define SPI4_RX_DMA_CHANNEL DMA_CH6 223 #define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 224 #define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 225 #define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 226 #define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM 227 #define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO 228 #define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 229 #elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) 230 #define I2C4_TX_DMA_INSTANCE CM_DMA1 231 #define I2C4_TX_DMA_CHANNEL DMA_CH6 232 #define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 233 #define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 234 #define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 235 #define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM 236 #define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO 237 #define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 238 #endif 239 240 /* DMA1 ch7 */ 241 #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) 242 #define SPI4_TX_DMA_INSTANCE CM_DMA1 243 #define SPI4_TX_DMA_CHANNEL DMA_CH7 244 #define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 245 #define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 246 #define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 247 #define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM 248 #define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO 249 #define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 250 #elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) 251 #define I2C4_RX_DMA_INSTANCE CM_DMA1 252 #define I2C4_RX_DMA_CHANNEL DMA_CH7 253 #define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 254 #define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 255 #define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 256 #define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM 257 #define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO 258 #define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 259 #endif 260 261 /* DMA1 ch8 */ 262 #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) 263 #define SPI5_TX_DMA_INSTANCE CM_DMA1 264 #define SPI5_TX_DMA_CHANNEL DMA_CH8 265 #define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 266 #define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 267 #define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 268 #define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM 269 #define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO 270 #define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 271 #endif 272 273 /* DMA1 ch9 */ 274 #if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) 275 #define SPI6_TX_DMA_INSTANCE CM_DMA1 276 #define SPI6_TX_DMA_CHANNEL DMA_CH9 277 #define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) 278 #define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 279 #define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 280 #define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM 281 #define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO 282 #define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 283 #endif 284 285 /* DMA2 ch0 */ 286 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 287 #define UART1_RX_DMA_INSTANCE CM_DMA2 288 #define UART1_RX_DMA_CHANNEL DMA_CH0 289 #define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 290 #define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 291 #define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 292 #define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM 293 #define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO 294 #define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 295 #elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) 296 #define I2C5_TX_DMA_INSTANCE CM_DMA2 297 #define I2C5_TX_DMA_CHANNEL DMA_CH0 298 #define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 299 #define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 300 #define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 301 #define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM 302 #define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO 303 #define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 304 #endif 305 306 /* DMA2 ch1 */ 307 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 308 #define UART1_TX_DMA_INSTANCE CM_DMA2 309 #define UART1_TX_DMA_CHANNEL DMA_CH1 310 #define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 311 #define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 312 #define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 313 #define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM 314 #define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO 315 #define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 316 #elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) 317 #define I2C5_RX_DMA_INSTANCE CM_DMA2 318 #define I2C5_RX_DMA_CHANNEL DMA_CH1 319 #define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 320 #define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 321 #define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 322 #define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM 323 #define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO 324 #define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 325 #endif 326 327 /* DMA2 ch2 */ 328 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 329 #define UART2_RX_DMA_INSTANCE CM_DMA2 330 #define UART2_RX_DMA_CHANNEL DMA_CH2 331 #define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 332 #define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 333 #define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 334 #define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM 335 #define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO 336 #define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 337 #elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) 338 #define I2C6_TX_DMA_INSTANCE CM_DMA2 339 #define I2C6_TX_DMA_CHANNEL DMA_CH2 340 #define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 341 #define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 342 #define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 343 #define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM 344 #define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO 345 #define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 346 #endif 347 348 /* DMA2 ch3 */ 349 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 350 #define UART2_TX_DMA_INSTANCE CM_DMA2 351 #define UART2_TX_DMA_CHANNEL DMA_CH3 352 #define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 353 #define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 354 #define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 355 #define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM 356 #define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO 357 #define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 358 #elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) 359 #define I2C6_RX_DMA_INSTANCE CM_DMA2 360 #define I2C6_RX_DMA_CHANNEL DMA_CH3 361 #define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 362 #define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 363 #define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 364 #define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM 365 #define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO 366 #define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 367 #endif 368 369 /* DMA2 ch4 */ 370 #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) 371 #define UART6_RX_DMA_INSTANCE CM_DMA2 372 #define UART6_RX_DMA_CHANNEL DMA_CH4 373 #define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 374 #define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 375 #define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 376 #define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM 377 #define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO 378 #define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 379 #endif 380 381 /* DMA2 ch5 */ 382 #if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) 383 #define UART6_TX_DMA_INSTANCE CM_DMA2 384 #define UART6_TX_DMA_CHANNEL DMA_CH5 385 #define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 386 #define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 387 #define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 388 #define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM 389 #define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO 390 #define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 391 #endif 392 393 /* DMA2 ch6 */ 394 #if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) 395 #define UART7_RX_DMA_INSTANCE CM_DMA2 396 #define UART7_RX_DMA_CHANNEL DMA_CH6 397 #define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 398 #define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 399 #define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 400 #define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM 401 #define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO 402 #define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 403 #endif 404 405 /* DMA2 ch7 */ 406 #if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) 407 #define UART7_TX_DMA_INSTANCE CM_DMA2 408 #define UART7_TX_DMA_CHANNEL DMA_CH7 409 #define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) 410 #define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 411 #define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 412 #define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM 413 #define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO 414 #define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 415 #endif 416 417 418 #ifdef __cplusplus 419 } 420 #endif 421 422 423 #endif /* __DMA_CONFIG_H__ */ 424