1 /* 2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2023-06-21 CDT first version 9 */ 10 11 #ifndef __TMR_CONFIG_H__ 12 #define __TMR_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #ifdef BSP_USING_TMRA_1 21 #ifndef TMRA_1_CONFIG 22 #define TMRA_1_CONFIG \ 23 { \ 24 .tmr_handle = CM_TMRA_1, \ 25 .clock_source = CLK_BUS_PCLK0, \ 26 .clock = FCG2_PERIPH_TMRA_1, \ 27 .flag = TMRA_FLAG_OVF, \ 28 .isr = \ 29 { \ 30 .enIntSrc = INT_SRC_TMRA_1_OVF, \ 31 .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ 32 .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ 33 }, \ 34 .name = "tmra_1" \ 35 } 36 #endif /* TMRA_1_CONFIG */ 37 #endif /* BSP_USING_TMRA_1 */ 38 39 #ifdef BSP_USING_TMRA_2 40 #ifndef TMRA_2_CONFIG 41 #define TMRA_2_CONFIG \ 42 { \ 43 .tmr_handle = CM_TMRA_2, \ 44 .clock_source = CLK_BUS_PCLK0, \ 45 .clock = FCG2_PERIPH_TMRA_2, \ 46 .flag = TMRA_FLAG_OVF, \ 47 .isr = \ 48 { \ 49 .enIntSrc = INT_SRC_TMRA_2_OVF, \ 50 .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ 51 .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ 52 }, \ 53 .name = "tmra_2" \ 54 } 55 #endif /* TMRA_2_CONFIG */ 56 #endif /* BSP_USING_TMRA_2 */ 57 58 #ifdef BSP_USING_TMRA_3 59 #ifndef TMRA_3_CONFIG 60 #define TMRA_3_CONFIG \ 61 { \ 62 .tmr_handle = CM_TMRA_3, \ 63 .clock_source = CLK_BUS_PCLK0, \ 64 .clock = FCG2_PERIPH_TMRA_3, \ 65 .flag = TMRA_FLAG_OVF, \ 66 .isr = \ 67 { \ 68 .enIntSrc = INT_SRC_TMRA_3_OVF, \ 69 .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ 70 .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ 71 }, \ 72 .name = "tmra_3" \ 73 } 74 #endif /* TMRA_3_CONFIG */ 75 #endif /* BSP_USING_TMRA_3 */ 76 77 #ifdef BSP_USING_TMRA_4 78 #ifndef TMRA_4_CONFIG 79 #define TMRA_4_CONFIG \ 80 { \ 81 .tmr_handle = CM_TMRA_4, \ 82 .clock_source = CLK_BUS_PCLK0, \ 83 .clock = FCG2_PERIPH_TMRA_4, \ 84 .flag = TMRA_FLAG_OVF, \ 85 .isr = \ 86 { \ 87 .enIntSrc = INT_SRC_TMRA_4_OVF, \ 88 .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ 89 .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ 90 }, \ 91 .name = "tmra_4" \ 92 } 93 #endif /* TMRA_4_CONFIG */ 94 #endif /* BSP_USING_TMRA_4 */ 95 96 #ifdef BSP_USING_TMRA_5 97 #ifndef TMRA_5_CONFIG 98 #define TMRA_5_CONFIG \ 99 { \ 100 .tmr_handle = CM_TMRA_5, \ 101 .clock_source = CLK_BUS_PCLK1, \ 102 .clock = FCG2_PERIPH_TMRA_5, \ 103 .flag = TMRA_FLAG_OVF, \ 104 .isr = \ 105 { \ 106 .enIntSrc = INT_SRC_TMRA_5_OVF, \ 107 .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ 108 .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ 109 }, \ 110 .name = "tmra_5" \ 111 } 112 #endif /* TMRA_5_CONFIG */ 113 #endif /* BSP_USING_TMRA_5 */ 114 115 #ifdef BSP_USING_TMRA_6 116 #ifndef TMRA_6_CONFIG 117 #define TMRA_6_CONFIG \ 118 { \ 119 .tmr_handle = CM_TMRA_6, \ 120 .clock_source = CLK_BUS_PCLK1, \ 121 .clock = FCG2_PERIPH_TMRA_6, \ 122 .flag = TMRA_FLAG_OVF, \ 123 .isr = \ 124 { \ 125 .enIntSrc = INT_SRC_TMRA_6_OVF, \ 126 .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ 127 .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ 128 }, \ 129 .name = "tmra_6" \ 130 } 131 #endif /* TMRA_6_CONFIG */ 132 #endif /* BSP_USING_TMRA_6 */ 133 134 #ifdef BSP_USING_TMRA_7 135 #ifndef TMRA_7_CONFIG 136 #define TMRA_7_CONFIG \ 137 { \ 138 .tmr_handle = CM_TMRA_7, \ 139 .clock_source = CLK_BUS_PCLK1, \ 140 .clock = FCG2_PERIPH_TMRA_7, \ 141 .flag = TMRA_FLAG_OVF, \ 142 .isr = \ 143 { \ 144 .enIntSrc = INT_SRC_TMRA_7_OVF, \ 145 .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ 146 .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ 147 }, \ 148 .name = "tmra_7" \ 149 } 150 #endif /* TMRA_7_CONFIG */ 151 #endif /* BSP_USING_TMRA_7 */ 152 153 #ifdef BSP_USING_TMRA_8 154 #ifndef TMRA_8_CONFIG 155 #define TMRA_8_CONFIG \ 156 { \ 157 .tmr_handle = CM_TMRA_8, \ 158 .clock_source = CLK_BUS_PCLK1, \ 159 .clock = FCG2_PERIPH_TMRA_8, \ 160 .flag = TMRA_FLAG_OVF, \ 161 .isr = \ 162 { \ 163 .enIntSrc = INT_SRC_TMRA_8_OVF, \ 164 .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ 165 .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ 166 }, \ 167 .name = "tmra_8" \ 168 } 169 #endif /* TMRA_8_CONFIG */ 170 #endif /* BSP_USING_TMRA_8 */ 171 172 #ifdef BSP_USING_TMRA_9 173 #ifndef TMRA_9_CONFIG 174 #define TMRA_9_CONFIG \ 175 { \ 176 .tmr_handle = CM_TMRA_9, \ 177 .clock_source = CLK_BUS_PCLK1, \ 178 .clock = FCG2_PERIPH_TMRA_9, \ 179 .flag = TMRA_FLAG_OVF, \ 180 .isr = \ 181 { \ 182 .enIntSrc = INT_SRC_TMRA_9_OVF, \ 183 .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ 184 .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ 185 }, \ 186 .name = "tmra_9" \ 187 } 188 #endif /* TMRA_9_CONFIG */ 189 #endif /* BSP_USING_TMRA_9 */ 190 191 #ifdef BSP_USING_TMRA_10 192 #ifndef TMRA_10_CONFIG 193 #define TMRA_10_CONFIG \ 194 { \ 195 .tmr_handle = CM_TMRA_10, \ 196 .clock_source = CLK_BUS_PCLK1, \ 197 .clock = FCG2_PERIPH_TMRA_10, \ 198 .flag = TMRA_FLAG_OVF, \ 199 .isr = \ 200 { \ 201 .enIntSrc = INT_SRC_TMRA_10_OVF, \ 202 .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ 203 .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ 204 }, \ 205 .name = "tmra_10" \ 206 } 207 #endif /* TMRA_10_CONFIG */ 208 #endif /* BSP_USING_TMRA_10 */ 209 210 #ifdef BSP_USING_TMRA_11 211 #ifndef TMRA_11_CONFIG 212 #define TMRA_11_CONFIG \ 213 { \ 214 .tmr_handle = CM_TMRA_11, \ 215 .clock_source = CLK_BUS_PCLK1, \ 216 .clock = FCG2_PERIPH_TMRA_11, \ 217 .flag = TMRA_FLAG_OVF, \ 218 .isr = \ 219 { \ 220 .enIntSrc = INT_SRC_TMRA_11_OVF, \ 221 .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ 222 .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ 223 }, \ 224 .name = "tmra_11" \ 225 } 226 #endif /* TMRA_11_CONFIG */ 227 #endif /* BSP_USING_TMRA_11 */ 228 229 #ifdef BSP_USING_TMRA_12 230 #ifndef TMRA_12_CONFIG 231 #define TMRA_12_CONFIG \ 232 { \ 233 .tmr_handle = CM_TMRA_12, \ 234 .clock_source = CLK_BUS_PCLK1, \ 235 .clock = FCG2_PERIPH_TMRA_12, \ 236 .flag = TMRA_FLAG_OVF, \ 237 .isr = \ 238 { \ 239 .enIntSrc = INT_SRC_TMRA_12_OVF, \ 240 .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ 241 .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ 242 }, \ 243 .name = "tmra_12" \ 244 } 245 #endif /* TMRA_12_CONFIG */ 246 #endif /* BSP_USING_TMRA_12 */ 247 #endif /* __TMR_CONFIG_H__ */ 248