1/***************************************************************************//**
2 * \file HC32F4A0.icf
3 * \version 1.0
4 *
5 * \brief Linker file for the IAR compiler.
6 *
7********************************************************************************
8* \copyright
9 * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
10 *
11 * This software component is licensed by XHSC under BSD 3-Clause license
12 * (the "License"); You may not use this file except in compliance with the
13 * License. You may obtain a copy of the License at:
14 *                    opensource.org/licenses/BSD-3-Clause
15*******************************************************************************/
16/*###ICF### Section handled by ICF editor, don't touch! *****/
17/*-Editor annotation file-*/
18/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
19// Check that necessary symbols have been passed to linker via command line interface
20if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
21  error "Link location not defined or not supported!";
22}
23if((!isdefinedsymbol(_HC32F4A0_2M_)) && (!isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) && (!isdefinedsymbol(_HC32F4A0_1M_DUAL_))) {
24  error "Mcu type or size not defined or not supported!";
25}
26
27/*******************************************************************************
28 * Memory address and size definitions
29 ******************************************************************************/
30define symbol ram1_base_address = 0x1FFE0000;
31define symbol ram1_end_address  = 0x2005FFFF;
32
33if(isdefinedsymbol(_LINK_RAM_)) {
34  define symbol ram_start_reserve = 0x20000;
35  define symbol rom1_base_address = ram1_base_address;
36  define symbol rom1_end_address  = rom1_base_address + ram_start_reserve - 0x01;
37  define symbol rom2_base_address = 0x0;
38  define symbol rom2_end_address  = 0x0;
39  define symbol rom3_base_address = 0x0;
40  define symbol rom3_end_address = 0x0;
41} else {
42  define symbol ram_start_reserve = 0x0;
43  define symbol rom1_base_address = 0x0;
44  define symbol rom3_base_address = 0x03000000;
45  define symbol rom3_end_address = 0x030017FF;
46  if (isdefinedsymbol(_HC32F4A0_2M_)) {
47    define symbol rom1_end_address  = 0x001FFFFF;
48    define symbol rom2_base_address = 0x0;
49    define symbol rom2_end_address  = 0x0;
50  } else if (isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) {
51    define symbol rom1_end_address  = 0x000FFFFF;
52    define symbol rom2_base_address = 0x0;
53    define symbol rom2_end_address  = 0x0;
54  } else if (isdefinedsymbol(_HC32F4A0_1M_DUAL_)) {
55    define symbol rom1_end_address  = 0x0007FFFF;
56    define symbol rom2_base_address = 0x00100000;
57    define symbol rom2_end_address  = 0x0017FFFF;
58  }
59}
60
61/*-Specials-*/
62define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
63/*-Memory Regions-*/
64define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
65define symbol __ICFEDIT_region_IROM1_end__   = rom1_end_address;
66define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
67define symbol __ICFEDIT_region_IROM2_end__   = rom2_end_address;
68define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
69define symbol __ICFEDIT_region_IROM3_end__   = rom3_end_address;
70define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
71define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
72define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
73define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
74define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
75define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
76define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
77define symbol __ICFEDIT_region_IRAM1_end__   = ram1_end_address;
78define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
79define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
80define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
81define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
82define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
83define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
84define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
85define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
86
87
88/*-Sizes-*/
89define symbol __ICFEDIT_size_cstack__     = 0x2000;
90define symbol __ICFEDIT_size_proc_stack__ = 0x0;
91define symbol __ICFEDIT_size_heap__       = 0x2000;
92/**** End of ICF editor section. ###ICF###*/
93
94/*******************************************************************************
95 * Memory definitions
96 ******************************************************************************/
97define memory mem with size = 4G;
98define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
99                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
100define region OTP_region       =   mem:[from __ICFEDIT_region_IROM3_start__   to __ICFEDIT_region_IROM3_end__];
101define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
102                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
103
104define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
105define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
106
107initialize by copy { readwrite };
108do not initialize  { section .noinit };
109
110place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
111
112place in ROM_region   { readonly };
113place in OTP_region   { readonly section .otp_data };
114place in RAM_region   { readwrite,
115                        block CSTACK, block HEAP };
116