1 /* 2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2023-02-24 CDT first version 9 * 2024-02-20 CDT modify timing configuration for using exclk clock frequency 30MHz 10 * add t_rcd/t_rfc/t_rp configuration macros-definition 11 */ 12 13 #ifndef __SDRAM_PORT_H__ 14 #define __SDRAM_PORT_H__ 15 16 /* parameters for sdram peripheral */ 17 18 /* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ 19 #define SDRAM_CHIP EXMC_DMC_CHIP1 20 /* bank address */ 21 #define SDRAM_BANK_ADDR (0x80000000UL) 22 /* size(kbyte):8MB = 8*1024*1KBytes */ 23 #define SDRAM_SIZE (8UL * 1024UL * 1024UL) 24 /* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ 25 #define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 26 /* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ 27 #define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT 28 /* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ 29 #define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 30 /* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ 31 #define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 32 /* cas latency clock number: 2, 3 */ 33 #define SDRAM_CAS_LATENCY 2UL 34 /* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ 35 #define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT 36 37 /* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ 38 #define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD 39 /* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ 40 #define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL 41 /* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ 42 #define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED 43 44 /* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */ 45 /* refresh rate counter (EXCLK clock) */ 46 #define SDRAM_REFRESH_COUNT (450U) 47 /* TMDR: mode register command time (EXCLK clock) */ 48 #define SDRAM_TMDR 2U 49 /* TRAS: RAS to precharge delay time (EXCLK clock) */ 50 #define SDRAM_TRAS 2U 51 /* TRC: active bank x to active bank x delay time (EXCLK clock) */ 52 #define SDRAM_TRC 2U 53 /* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ 54 #define SDRAM_TRCD_B 3U 55 #define SDRAM_TRCD_P 0U 56 /* TRFC: autorefresh command time (EXCLK clock) */ 57 #define SDRAM_TRFC_B 3U 58 #define SDRAM_TRFC_P 0U 59 /* TRP: precharge to RAS delay time (EXCLK clock) */ 60 #define SDRAM_TRP_B 3U 61 #define SDRAM_TRP_P 0U 62 /* TRRD: active bank x to active bank y delay time (EXCLK clock) */ 63 #define SDRAM_TRRD 1U 64 /* TWR: write to precharge delay time (EXCLK clock). */ 65 #define SDRAM_TWR 2U 66 /* TWTR: write to read delay time (EXCLK clock). */ 67 #define SDRAM_TWTR 1U 68 /* TXP: exit power-down command time (EXCLK clock). */ 69 #define SDRAM_TXP 1U 70 /* TXSR: exit self-refresh command time (EXCLK clock). */ 71 #define SDRAM_TXSR 5U 72 /* TESR: self-refresh command time (EXCLK clock). */ 73 #define SDRAM_TESR 5U 74 75 /* memory mode register */ 76 #define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) 77 #define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) 78 #define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) 79 #define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) 80 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) 81 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) 82 #define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) 83 #define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) 84 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) 85 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) 86 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) 87 88 #endif 89