1 /* 2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-04-28 CDT first version 9 */ 10 11 12 #ifndef __DRV_ETH_H__ 13 #define __DRV_ETH_H__ 14 15 /******************************************************************************* 16 * Include files 17 ******************************************************************************/ 18 #include <rtthread.h> 19 #include <rthw.h> 20 #include <rtdevice.h> 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 27 /* The PHY basic control register */ 28 #define PHY_BASIC_CONTROL_REG 0x00U 29 #define PHY_RESET_MASK (1<<15) 30 #define PHY_AUTO_NEGOTIATION_MASK (1<<12) 31 32 /* The PHY basic status register */ 33 #define PHY_BASIC_STATUS_REG 0x01U 34 #define PHY_LINKED_STATUS_MASK (1<<2) 35 #define PHY_AUTONEGO_COMPLETE_MASK (1<<5) 36 37 /* The PHY ID one register */ 38 #define PHY_ID1_REG 0x02U 39 40 41 #if defined (ETH_PHY_USING_RTL8201F) 42 /* Extended PHY Registers */ 43 #define PHY_PSMR (0x18U) /*!< Power Saving Mode Register */ 44 #define PHY_IISDR (0x1EU) /*!< Interrupt Indicators and SNR Display Register */ 45 #define PHY_PSR (0x1FU) /*!< Page Select Register */ 46 #define PHY_P7_RMSR (0x10U) /*!< RMII Mode Setting Register */ 47 #define PHY_P7_IWLFR (0x13U) /*!< Interrupt, WOL Enable, and LED Function Registers */ 48 49 /* The following parameters will return to default values after a software reset */ 50 #define PHY_EN_PWR_SAVE (0x8000U) /*!< Enable Power Saving Mode */ 51 52 #define PHY_FLAG_AUTO_NEGO_ERROR (0x8000U) /*!< Auto-Negotiation Error Interrupt Flag */ 53 #define PHY_FLAG_SPEED_MODE_CHANGE (0x4000U) /*!< Speed Mode Change Interrupt Flag */ 54 #define PHY_FLAG_DUPLEX_MODE_CHANGE (0x2000U) /*!< Duplex Mode Change Interrupt Flag */ 55 #define PHY_FLAG_LINK_STATUS_CHANGE (0x0800U) /*!< Link Status Change Interrupt Flag */ 56 57 #define PHY_PAGE_ADDR_0 (0x0000U) /*!< Page Address 0 (default) */ 58 #define PHY_PAGE_ADDR_7 (0x0007U) /*!< Page Address 7 */ 59 60 #define PHY_RMII_CLK_DIR (0x1000U) /*!< TXC direction in RMII Mode */ 61 #define PHY_RMII_MODE (0x0008U) /*!< RMII Mode or MII Mode */ 62 #define PHY_RMII_RXDV_CRSDV (0x0004U) /*!< CRS_DV or RXDV select */ 63 64 #define PHY_INT_LINK_CHANGE (0x2000U) /*!< Link Change Interrupt Mask */ 65 #define PHY_INT_DUPLEX_CHANGE (0x1000U) /*!< Duplex Change Interrupt Mask */ 66 #define PHY_INT_AUTO_NEGO_ERROR (0x0800U) /*!< Auto-Negotiation Error Interrupt Mask */ 67 #define PHY_LED_WOL_SELECT (0x0400U) /*!< LED and Wake-On-LAN Function Selection */ 68 #define PHY_LED_SELECT (0x0030U) /*!< Traditional LED Function Selection. */ 69 #define PHY_LED_SELECT_00 (0x0000U) /*!< LED0: ACT(all) LED1: LINK(100) */ 70 #define PHY_LED_SELECT_01 (0x0010U) /*!< LED0: LINK(ALL)/ACT(all) LED1: LINK(100) */ 71 #define PHY_LED_SELECT_10 (0x0020U) /*!< LED0: LINK(10)/ACT(all) LED1: LINK(100) */ 72 #define PHY_LED_SELECT_11 (0x0030U) /*!< LED0: LINK(10)/ACT(10) LED1: LINK(100)/ACT(100) */ 73 #define PHY_EN_10M_LED_FUNC (0x0001U) /*!< Enable 10M LPI LED Function */ 74 75 #endif 76 77 78 #ifdef __cplusplus 79 } 80 #endif 81 82 #endif /* __DRV_ETH_H__ */ 83