1 /*
2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2023-06-09 CDT first version
9 */
10
11 #include "board.h"
12 #include "drv_config.h"
13
14 #ifdef BSP_USING_PULSE_ENCODER
15
16 #include "drv_irq.h"
17
18 // #define DRV_DEBUG
19 #define LOG_TAG "drv_pulse_encoder"
20 #include <drv_log.h>
21
22 #if defined(BSP_USING_TMRA_PULSE_ENCODER)
23
24 #if !defined(BSP_USING_PULSE_ENCODER_TMRA_1) && !defined(BSP_USING_PULSE_ENCODER_TMRA_2) && !defined(BSP_USING_PULSE_ENCODER_TMRA_3) && \
25 !defined(BSP_USING_PULSE_ENCODER_TMRA_4) && !defined(BSP_USING_PULSE_ENCODER_TMRA_5) && !defined(BSP_USING_PULSE_ENCODER_TMRA_6) && \
26 !defined(BSP_USING_PULSE_ENCODER_TMRA_7) && !defined(BSP_USING_PULSE_ENCODER_TMRA_8) && !defined(BSP_USING_PULSE_ENCODER_TMRA_9) && \
27 !defined(BSP_USING_PULSE_ENCODER_TMRA_10) && !defined(BSP_USING_PULSE_ENCODER_TMRA_11) && !defined(BSP_USING_PULSE_ENCODER_TMRA_12)
28 #error "Please define at least one BSP_USING_PULSE_ENCODERx"
29 /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
30 #endif
31
32 enum
33 {
34 #ifdef BSP_USING_PULSE_ENCODER_TMRA_1
35 PULSE_ENCODER_TMRA_1_INDEX,
36 #endif
37 #ifdef BSP_USING_PULSE_ENCODER_TMRA_2
38 PULSE_ENCODER_TMRA_2_INDEX,
39 #endif
40 #ifdef BSP_USING_PULSE_ENCODER_TMRA_3
41 PULSE_ENCODER_TMRA_3_INDEX,
42 #endif
43 #ifdef BSP_USING_PULSE_ENCODER_TMRA_4
44 PULSE_ENCODER_TMRA_4_INDEX,
45 #endif
46 #ifdef BSP_USING_PULSE_ENCODER_TMRA_5
47 PULSE_ENCODER_TMRA_5_INDEX,
48 #endif
49 #ifdef BSP_USING_PULSE_ENCODER_TMRA_6
50 PULSE_ENCODER_TMRA_6_INDEX,
51 #endif
52 #ifdef BSP_USING_PULSE_ENCODER_TMRA_7
53 PULSE_ENCODER_TMRA_7_INDEX,
54 #endif
55 #ifdef BSP_USING_PULSE_ENCODER_TMRA_8
56 PULSE_ENCODER_TMRA_8_INDEX,
57 #endif
58 #ifdef BSP_USING_PULSE_ENCODER_TMRA_9
59 PULSE_ENCODER_TMRA_9_INDEX,
60 #endif
61 #ifdef BSP_USING_PULSE_ENCODER_TMRA_10
62 PULSE_ENCODER_TMRA_10_INDEX,
63 #endif
64 #ifdef BSP_USING_PULSE_ENCODER_TMRA_11
65 PULSE_ENCODER_TMRA_11_INDEX,
66 #endif
67 #ifdef BSP_USING_PULSE_ENCODER_TMRA_12
68 PULSE_ENCODER_TMRA_12_INDEX,
69 #endif
70 };
71
72 struct hc32_pulse_encoder_tmra_device
73 {
74 struct rt_pulse_encoder_device pulse_encoder;
75 CM_TMRA_TypeDef *tmr_handler;
76 uint32_t u32PeriphClock;
77 struct
78 {
79 uint16_t u16CountUpCond;
80 uint16_t u16CountDownCond;
81 } hw_count;
82 struct
83 {
84 en_int_src_t enIntSrc_Ovf;
85 IRQn_Type enIRQn_Ovf;
86 uint8_t u8Int_Prio_Ovf;
87 func_ptr_t Irq_Ovf_Callback;
88 en_int_src_t enIntSrc_Udf;
89 IRQn_Type enIRQn_Udf;
90 uint8_t u8Int_Prio_Udf;
91 func_ptr_t Irq_Udf_Callback;
92 } isr;
93 rt_uint32_t u32PeriodValue;
94 rt_int32_t Over_Under_Flowcount;
95 char *name;
96 };
97
98 static struct hc32_pulse_encoder_tmra_device hc32_pulse_encoder_tmra_obj[] =
99 {
100 #ifdef BSP_USING_PULSE_ENCODER_TMRA_1
101 PULSE_ENCODER_TMRA_1_CONFIG,
102 #endif
103 #ifdef BSP_USING_PULSE_ENCODER_TMRA_2
104 PULSE_ENCODER_TMRA_2_CONFIG,
105 #endif
106 #ifdef BSP_USING_PULSE_ENCODER_TMRA_3
107 PULSE_ENCODER_TMRA_3_CONFIG,
108 #endif
109 #ifdef BSP_USING_PULSE_ENCODER_TMRA_4
110 PULSE_ENCODER_TMRA_4_CONFIG,
111 #endif
112 #ifdef BSP_USING_PULSE_ENCODER_TMRA_5
113 PULSE_ENCODER_TMRA_5_CONFIG,
114 #endif
115 #ifdef BSP_USING_PULSE_ENCODER_TMRA_6
116 PULSE_ENCODER_TMRA_6_CONFIG,
117 #endif
118 #ifdef BSP_USING_PULSE_ENCODER_TMRA_7
119 PULSE_ENCODER_TMRA_7_CONFIG,
120 #endif
121 #ifdef BSP_USING_PULSE_ENCODER_TMRA_8
122 PULSE_ENCODER_TMRA_8_CONFIG,
123 #endif
124 #ifdef BSP_USING_PULSE_ENCODER_TMRA_9
125 PULSE_ENCODER_TMRA_9_CONFIG,
126 #endif
127 #ifdef BSP_USING_PULSE_ENCODER_TMRA_10
128 PULSE_ENCODER_TMRA_10_CONFIG,
129 #endif
130 #ifdef BSP_USING_PULSE_ENCODER_TMRA_11
131 PULSE_ENCODER_TMRA_11_CONFIG,
132 #endif
133 #ifdef BSP_USING_PULSE_ENCODER_TMRA_12
134 PULSE_ENCODER_TMRA_12_CONFIG,
135 #endif
136 };
137
138 #ifdef BSP_USING_PULSE_ENCODER_TMRA_1
TMRA_1_Ovf_callback(void)139 static void TMRA_1_Ovf_callback(void)
140 {
141 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler, TMRA_FLAG_OVF);
142 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].Over_Under_Flowcount++;
143 }
TMRA_1_Udf_callback(void)144 static void TMRA_1_Udf_callback(void)
145 {
146 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler, TMRA_FLAG_UDF);
147 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].Over_Under_Flowcount--;
148 }
149 #if defined (HC32F448) || defined (HC32F472)
TMRA_1_Ovf_Udf_Handler(void)150 void TMRA_1_Ovf_Udf_Handler(void)
151 {
152 CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler;
153 if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_OVF) == SET)
154 {
155 TMRA_1_Ovf_callback();
156 }
157 else if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_UDF) == SET)
158 {
159 TMRA_1_Udf_callback();
160 }
161 }
162 #endif
163 #endif
164
165 #ifdef BSP_USING_PULSE_ENCODER_TMRA_2
TMRA_2_Ovf_callback(void)166 static void TMRA_2_Ovf_callback(void)
167 {
168 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler, TMRA_FLAG_OVF);
169 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].Over_Under_Flowcount++;
170 }
TMRA_2_Udf_callback(void)171 static void TMRA_2_Udf_callback(void)
172 {
173 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler, TMRA_FLAG_UDF);
174 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].Over_Under_Flowcount--;
175 }
176 #if defined (HC32F448) || defined (HC32F472)
TMRA_2_Ovf_Udf_Handler(void)177 void TMRA_2_Ovf_Udf_Handler(void)
178 {
179 CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler;
180 if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_OVF) == SET)
181 {
182 TMRA_2_Ovf_callback();
183 }
184 else if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_UDF) == SET)
185 {
186 TMRA_2_Udf_callback();
187 }
188 }
189 #endif
190 #endif
191
192 #ifdef BSP_USING_PULSE_ENCODER_TMRA_3
TMRA_3_Ovf_callback(void)193 static void TMRA_3_Ovf_callback(void)
194 {
195 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler, TMRA_FLAG_OVF);
196 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].Over_Under_Flowcount++;
197 }
TMRA_3_Udf_callback(void)198 static void TMRA_3_Udf_callback(void)
199 {
200 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler, TMRA_FLAG_UDF);
201 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].Over_Under_Flowcount--;
202 }
203 #if defined (HC32F448) || defined (HC32F472)
TMRA_3_Ovf_Udf_Handler(void)204 void TMRA_3_Ovf_Udf_Handler(void)
205 {
206 CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler;
207 if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_OVF) == SET)
208 {
209 TMRA_3_Ovf_callback();
210 }
211 else if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_UDF) == SET)
212 {
213 TMRA_3_Udf_callback();
214 }
215 }
216 #endif
217 #endif
218
219 #ifdef BSP_USING_PULSE_ENCODER_TMRA_4
TMRA_4_Ovf_callback(void)220 static void TMRA_4_Ovf_callback(void)
221 {
222 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler, TMRA_FLAG_OVF);
223 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].Over_Under_Flowcount++;
224 }
TMRA_4_Udf_callback(void)225 static void TMRA_4_Udf_callback(void)
226 {
227 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler, TMRA_FLAG_UDF);
228 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].Over_Under_Flowcount--;
229 }
230 #if defined (HC32F448) || defined (HC32F472)
TMRA_4_Ovf_Udf_Handler(void)231 void TMRA_4_Ovf_Udf_Handler(void)
232 {
233 CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler;
234 if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_OVF) == SET)
235 {
236 TMRA_4_Ovf_callback();
237 }
238 else if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_UDF) == SET)
239 {
240 TMRA_4_Udf_callback();
241 }
242 }
243 #endif
244 #endif
245
246 #ifdef BSP_USING_PULSE_ENCODER_TMRA_5
TMRA_5_Ovf_callback(void)247 static void TMRA_5_Ovf_callback(void)
248 {
249 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler, TMRA_FLAG_OVF);
250 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].Over_Under_Flowcount++;
251 }
TMRA_5_Udf_callback(void)252 static void TMRA_5_Udf_callback(void)
253 {
254 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler, TMRA_FLAG_UDF);
255 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].Over_Under_Flowcount--;
256 }
257 #if defined (HC32F448) || defined (HC32F472)
TMRA_5_Ovf_Udf_Handler(void)258 void TMRA_5_Ovf_Udf_Handler(void)
259 {
260 CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler;
261 if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_OVF) == SET)
262 {
263 TMRA_5_Ovf_callback();
264 }
265 else if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_UDF) == SET)
266 {
267 TMRA_5_Udf_callback();
268 }
269 }
270 #endif
271 #endif
272
273 #ifdef BSP_USING_PULSE_ENCODER_TMRA_6
TMRA_6_Ovf_callback(void)274 static void TMRA_6_Ovf_callback(void)
275 {
276 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].tmr_handler, TMRA_FLAG_OVF);
277 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].Over_Under_Flowcount++;
278 }
TMRA_6_Udf_callback(void)279 static void TMRA_6_Udf_callback(void)
280 {
281 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].tmr_handler, TMRA_FLAG_UDF);
282 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].Over_Under_Flowcount--;
283 }
284 #if defined (HC32F472)
TMRA_6_Ovf_Udf_Handler(void)285 void TMRA_6_Ovf_Udf_Handler(void)
286 {
287 CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].tmr_handler;
288 if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_OVF) == SET)
289 {
290 TMRA_6_Ovf_callback();
291 }
292 else if (TMRA_GetStatus(tmr_handler, TMRA_FLAG_UDF) == SET)
293 {
294 TMRA_6_Udf_callback();
295 }
296 }
297 #endif
298 #endif
299
300 #ifdef BSP_USING_PULSE_ENCODER_TMRA_7
TMRA_7_Ovf_callback(void)301 static void TMRA_7_Ovf_callback(void)
302 {
303 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].tmr_handler, TMRA_FLAG_OVF);
304 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].Over_Under_Flowcount++;
305 }
TMRA_7_Udf_callback(void)306 static void TMRA_7_Udf_callback(void)
307 {
308 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].tmr_handler, TMRA_FLAG_UDF);
309 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].Over_Under_Flowcount--;
310 }
311 #endif
312
313 #ifdef BSP_USING_PULSE_ENCODER_TMRA_8
TMRA_8_Ovf_callback(void)314 static void TMRA_8_Ovf_callback(void)
315 {
316 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].tmr_handler, TMRA_FLAG_OVF);
317 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].Over_Under_Flowcount++;
318 }
TMRA_8_Udf_callback(void)319 static void TMRA_8_Udf_callback(void)
320 {
321 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].tmr_handler, TMRA_FLAG_UDF);
322 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].Over_Under_Flowcount--;
323 }
324 #endif
325
326 #ifdef BSP_USING_PULSE_ENCODER_TMRA_9
TMRA_9_Ovf_callback(void)327 static void TMRA_9_Ovf_callback(void)
328 {
329 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].tmr_handler, TMRA_FLAG_OVF);
330 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].Over_Under_Flowcount++;
331 }
TMRA_9_Udf_callback(void)332 static void TMRA_9_Udf_callback(void)
333 {
334 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].tmr_handler, TMRA_FLAG_UDF);
335 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].Over_Under_Flowcount--;
336 }
337 #endif
338
339 #ifdef BSP_USING_PULSE_ENCODER_TMRA_10
TMRA_10_Ovf_callback(void)340 static void TMRA_10_Ovf_callback(void)
341 {
342 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].tmr_handler, TMRA_FLAG_OVF);
343 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].Over_Under_Flowcount++;
344 }
TMRA_10_Udf_callback(void)345 static void TMRA_10_Udf_callback(void)
346 {
347 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].tmr_handler, TMRA_FLAG_UDF);
348 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].Over_Under_Flowcount--;
349 }
350 #endif
351
352 #ifdef BSP_USING_PULSE_ENCODER_TMRA_11
TMRA_11_Ovf_callback(void)353 static void TMRA_11_Ovf_callback(void)
354 {
355 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].tmr_handler, TMRA_FLAG_OVF);
356 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].Over_Under_Flowcount++;
357 }
TMRA_11_Udf_callback(void)358 static void TMRA_11_Udf_callback(void)
359 {
360 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].tmr_handler, TMRA_FLAG_UDF);
361 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].Over_Under_Flowcount--;
362 }
363 #endif
364
365 #ifdef BSP_USING_PULSE_ENCODER_TMRA_12
TMRA_12_Ovf_callback(void)366 static void TMRA_12_Ovf_callback(void)
367 {
368 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].tmr_handler, TMRA_FLAG_OVF);
369 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].Over_Under_Flowcount++;
370 }
TMRA_12_Udf_callback(void)371 static void TMRA_12_Udf_callback(void)
372 {
373 TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].tmr_handler, TMRA_FLAG_UDF);
374 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].Over_Under_Flowcount--;
375 }
376 #endif
377
378 /**
379 * @brief This function gets pulse_encoder_tima irq handle.
380 * @param None
381 * @retval None
382 */
hc32_get_pulse_encoder_tmra_callback(void)383 static void hc32_get_pulse_encoder_tmra_callback(void)
384 {
385 #ifdef BSP_USING_PULSE_ENCODER_TMRA_1
386 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].isr.Irq_Ovf_Callback = TMRA_1_Ovf_callback;
387 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].isr.Irq_Udf_Callback = TMRA_1_Udf_callback;
388 #endif
389 #ifdef BSP_USING_PULSE_ENCODER_TMRA_2
390 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].isr.Irq_Ovf_Callback = TMRA_2_Ovf_callback;
391 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].isr.Irq_Udf_Callback = TMRA_2_Udf_callback;
392 #endif
393 #ifdef BSP_USING_PULSE_ENCODER_TMRA_3
394 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].isr.Irq_Ovf_Callback = TMRA_3_Ovf_callback;
395 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].isr.Irq_Udf_Callback = TMRA_3_Udf_callback;
396 #endif
397 #ifdef BSP_USING_PULSE_ENCODER_TMRA_4
398 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].isr.Irq_Ovf_Callback = TMRA_4_Ovf_callback;
399 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].isr.Irq_Udf_Callback = TMRA_4_Udf_callback;
400 #endif
401 #ifdef BSP_USING_PULSE_ENCODER_TMRA_5
402 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].isr.Irq_Ovf_Callback = TMRA_5_Ovf_callback;
403 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].isr.Irq_Udf_Callback = TMRA_5_Udf_callback;
404 #endif
405 #ifdef BSP_USING_PULSE_ENCODER_TMRA_6
406 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].isr.Irq_Ovf_Callback = TMRA_6_Ovf_callback;
407 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].isr.Irq_Udf_Callback = TMRA_6_Udf_callback;
408 #endif
409 #ifdef BSP_USING_PULSE_ENCODER_TMRA_7
410 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].isr.Irq_Ovf_Callback = TMRA_7_Ovf_callback;
411 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_7_INDEX].isr.Irq_Udf_Callback = TMRA_7_Udf_callback;
412 #endif
413 #ifdef BSP_USING_PULSE_ENCODER_TMRA_8
414 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].isr.Irq_Ovf_Callback = TMRA_8_Ovf_callback;
415 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_8_INDEX].isr.Irq_Udf_Callback = TMRA_8_Udf_callback;
416 #endif
417 #ifdef BSP_USING_PULSE_ENCODER_TMRA_9
418 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].isr.Irq_Ovf_Callback = TMRA_9_Ovf_callback;
419 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_9_INDEX].isr.Irq_Udf_Callback = TMRA_9_Udf_callback;
420 #endif
421 #ifdef BSP_USING_PULSE_ENCODER_TMRA_10
422 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].isr.Irq_Ovf_Callback = TMRA_10_Ovf_callback;
423 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_10_INDEX].isr.Irq_Udf_Callback = TMRA_10_Udf_callback;
424 #endif
425 #ifdef BSP_USING_PULSE_ENCODER_TMRA_11
426 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].isr.Irq_Ovf_Callback = TMRA_11_Ovf_callback;
427 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_11_INDEX].isr.Irq_Udf_Callback = TMRA_11_Udf_callback;
428 #endif
429 #ifdef BSP_USING_PULSE_ENCODER_TMRA_12
430 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].isr.Irq_Ovf_Callback = TMRA_12_Ovf_callback;
431 hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_12_INDEX].isr.Irq_Udf_Callback = TMRA_12_Udf_callback;
432 #endif
433 }
434
_tmra_pulse_encoder_init(struct rt_pulse_encoder_device * pulse_encoder)435 rt_err_t _tmra_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
436 {
437 stc_tmra_init_t stcTmraInit;
438 struct hc32_irq_config irq_config;
439 struct hc32_pulse_encoder_tmra_device *hc32_device;
440 hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
441
442 /* Enable TimerA peripheral clock. */
443 FCG_Fcg2PeriphClockCmd(hc32_device->u32PeriphClock, ENABLE);
444
445 (void)TMRA_StructInit(&stcTmraInit);
446 /* Initializes position-count unit. */
447 stcTmraInit.u8CountSrc = TMRA_CNT_SRC_HW;
448 stcTmraInit.hw_count.u16CountUpCond = hc32_device->hw_count.u16CountUpCond;
449 stcTmraInit.hw_count.u16CountDownCond = hc32_device->hw_count.u16CountDownCond;
450 stcTmraInit.u32PeriodValue = hc32_device->u32PeriodValue;
451 (void)TMRA_Init(hc32_device->tmr_handler, &stcTmraInit);
452
453 /* OVF interrupt configuration */
454 irq_config.irq_num = hc32_device->isr.enIRQn_Ovf;
455 irq_config.int_src = hc32_device->isr.enIntSrc_Ovf;
456 irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Ovf;
457 /* register interrupt */
458 hc32_install_irq_handler(&irq_config, hc32_device->isr.Irq_Ovf_Callback, RT_TRUE);
459 /* UDF interrupt configuration */
460 irq_config.irq_num = hc32_device->isr.enIRQn_Udf;
461 irq_config.int_src = hc32_device->isr.enIntSrc_Udf;
462 irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Udf;
463 /* register interrupt */
464 hc32_install_irq_handler(&irq_config, hc32_device->isr.Irq_Udf_Callback, RT_TRUE);
465 /* Enable the specified interrupts of TimerA. */
466 TMRA_IntCmd(hc32_device->tmr_handler, TMRA_INT_OVF | TMRA_INT_UDF, ENABLE);
467
468 LOG_D("_tmra_pulse_encoder_init");
469
470 return RT_EOK;
471 }
472
_tmra_pulse_encoder_clear_count(struct rt_pulse_encoder_device * pulse_encoder)473 rt_err_t _tmra_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
474 {
475 rt_uint8_t startFlag = RT_FALSE;
476 struct hc32_pulse_encoder_tmra_device *hc32_device;
477 hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
478 hc32_device->Over_Under_Flowcount = 0;
479 if (READ_REG8_BIT(hc32_device->tmr_handler->BCSTRL, TMRA_BCSTRL_START) == TMRA_BCSTRL_START)
480 {
481 startFlag = RT_TRUE;
482 }
483 TMRA_Stop(hc32_device->tmr_handler);
484 TMRA_SetCountValue(hc32_device->tmr_handler, 0);
485 if (RT_TRUE == startFlag)
486 {
487 TMRA_Start(hc32_device->tmr_handler);
488 }
489 return RT_EOK;
490 }
491
_tmra_pulse_encoder_get_count(struct rt_pulse_encoder_device * pulse_encoder)492 rt_int32_t _tmra_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
493 {
494 struct hc32_pulse_encoder_tmra_device *hc32_device;
495 hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
496 return (rt_int32_t)((rt_int16_t)TMRA_GetCountValue(hc32_device->tmr_handler) + (hc32_device->Over_Under_Flowcount * (hc32_device->u32PeriodValue + 1)));
497 }
498
_tmra_pulse_encoder_control(struct rt_pulse_encoder_device * pulse_encoder,rt_uint32_t cmd,void * args)499 rt_err_t _tmra_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
500 {
501 rt_err_t result;
502 struct hc32_pulse_encoder_tmra_device *hc32_device;
503 hc32_device = (struct hc32_pulse_encoder_tmra_device *)pulse_encoder;
504
505 result = RT_EOK;
506
507 switch (cmd)
508 {
509 case PULSE_ENCODER_CMD_ENABLE:
510 TMRA_Start(hc32_device->tmr_handler);
511 LOG_D("TMRA_Start");
512 break;
513 case PULSE_ENCODER_CMD_DISABLE:
514 TMRA_Stop(hc32_device->tmr_handler);
515 LOG_D("TMRA_Stop");
516 break;
517 default:
518 result = -RT_ENOSYS;
519 break;
520 }
521
522 return result;
523 }
524
525 static const struct rt_pulse_encoder_ops _tmra_ops =
526 {
527 .init = _tmra_pulse_encoder_init,
528 .get_count = _tmra_pulse_encoder_get_count,
529 .clear_count = _tmra_pulse_encoder_clear_count,
530 .control = _tmra_pulse_encoder_control,
531 };
532
533 #endif /* BSP_USING_TMRA_PULSE_ENCODER */
534
535 #if defined(BSP_USING_TMR6_PULSE_ENCODER)
536
537 #if !defined(BSP_USING_PULSE_ENCODER_TMR6_1) && !defined(BSP_USING_PULSE_ENCODER_TMR6_2) && !defined(BSP_USING_PULSE_ENCODER_TMR6_3) && \
538 !defined(BSP_USING_PULSE_ENCODER_TMR6_4) && !defined(BSP_USING_PULSE_ENCODER_TMR6_5) && !defined(BSP_USING_PULSE_ENCODER_TMR6_6) && \
539 !defined(BSP_USING_PULSE_ENCODER_TMR6_7) && !defined(BSP_USING_PULSE_ENCODER_TMR6_8) && !defined(BSP_USING_PULSE_ENCODER_TMR6_9) && \
540 !defined(BSP_USING_PULSE_ENCODER_TMR6_10)
541 #error "Please define at least one BSP_USING_PULSE_ENCODERx"
542 /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
543 #endif
544
545 enum
546 {
547 #ifdef BSP_USING_PULSE_ENCODER_TMR6_1
548 PULSE_ENCODER_TMR6_1_INDEX,
549 #endif
550 #ifdef BSP_USING_PULSE_ENCODER_TMR6_2
551 PULSE_ENCODER_TMR6_2_INDEX,
552 #endif
553 #ifdef BSP_USING_PULSE_ENCODER_TMR6_3
554 PULSE_ENCODER_TMR6_3_INDEX,
555 #endif
556 #ifdef BSP_USING_PULSE_ENCODER_TMR6_4
557 PULSE_ENCODER_TMR6_4_INDEX,
558 #endif
559 #ifdef BSP_USING_PULSE_ENCODER_TMR6_5
560 PULSE_ENCODER_TMR6_5_INDEX,
561 #endif
562 #ifdef BSP_USING_PULSE_ENCODER_TMR6_6
563 PULSE_ENCODER_TMR6_6_INDEX,
564 #endif
565 #ifdef BSP_USING_PULSE_ENCODER_TMR6_7
566 PULSE_ENCODER_TMR6_7_INDEX,
567 #endif
568 #ifdef BSP_USING_PULSE_ENCODER_TMR6_8
569 PULSE_ENCODER_TMR6_8_INDEX,
570 #endif
571 #ifdef BSP_USING_PULSE_ENCODER_TMR6_9
572 PULSE_ENCODER_TMR6_9_INDEX,
573 #endif
574 #ifdef BSP_USING_PULSE_ENCODER_TMR6_10
575 PULSE_ENCODER_TMR6_10_INDEX,
576 #endif
577 };
578
579 struct hc32_pulse_encoder_tmr6_device
580 {
581 struct rt_pulse_encoder_device pulse_encoder;
582 CM_TMR6_TypeDef *tmr_handler;
583 uint32_t u32PeriphClock;
584 struct
585 {
586 uint32_t u32CountUpCond;
587 uint32_t u32CountDownCond;
588 } hw_count;
589 struct
590 {
591 en_int_src_t enIntSrc_Ovf;
592 IRQn_Type enIRQn_Ovf;
593 uint8_t u8Int_Prio_Ovf;
594 func_ptr_t Irq_Ovf_Callback;
595 en_int_src_t enIntSrc_Udf;
596 IRQn_Type enIRQn_Udf;
597 uint8_t u8Int_Prio_Udf;
598 func_ptr_t Irq_Udf_Callback;
599 } isr;
600 rt_uint32_t u32PeriodValue;
601 rt_int32_t Over_Under_Flowcount;
602 char *name;
603 };
604
605 static struct hc32_pulse_encoder_tmr6_device hc32_pulse_encoder_tmr6_obj[] =
606 {
607 #ifdef BSP_USING_PULSE_ENCODER_TMR6_1
608 PULSE_ENCODER_TMR6_1_CONFIG,
609 #endif
610 #ifdef BSP_USING_PULSE_ENCODER_TMR6_2
611 PULSE_ENCODER_TMR6_2_CONFIG,
612 #endif
613 #ifdef BSP_USING_PULSE_ENCODER_TMR6_3
614 PULSE_ENCODER_TMR6_3_CONFIG,
615 #endif
616 #ifdef BSP_USING_PULSE_ENCODER_TMR6_4
617 PULSE_ENCODER_TMR6_4_CONFIG,
618 #endif
619 #ifdef BSP_USING_PULSE_ENCODER_TMR6_5
620 PULSE_ENCODER_TMR6_5_CONFIG,
621 #endif
622 #ifdef BSP_USING_PULSE_ENCODER_TMR6_6
623 PULSE_ENCODER_TMR6_6_CONFIG,
624 #endif
625 #ifdef BSP_USING_PULSE_ENCODER_TMR6_7
626 PULSE_ENCODER_TMR6_7_CONFIG,
627 #endif
628 #ifdef BSP_USING_PULSE_ENCODER_TMR6_8
629 PULSE_ENCODER_TMR6_8_CONFIG,
630 #endif
631 #ifdef BSP_USING_PULSE_ENCODER_TMR6_9
632 PULSE_ENCODER_TMR6_9_CONFIG,
633 #endif
634 #ifdef BSP_USING_PULSE_ENCODER_TMR6_10
635 PULSE_ENCODER_TMR6_10_CONFIG,
636 #endif
637 };
638
639 #ifdef BSP_USING_PULSE_ENCODER_TMR6_1
TMR6_1_Ovf_callback(void)640 void TMR6_1_Ovf_callback(void)
641 {
642 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler, TMR6_FLAG_OVF);
643 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].Over_Under_Flowcount++;
644 }
TMR6_1_Udf_callback(void)645 void TMR6_1_Udf_callback(void)
646 {
647 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler, TMR6_FLAG_UDF);
648 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].Over_Under_Flowcount--;
649 }
650 #if defined (HC32F448) || defined (HC32F472)
TMR6_1_Ovf_Udf_Handler(void)651 void TMR6_1_Ovf_Udf_Handler(void)
652 {
653 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler;
654 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
655 {
656 TMR6_1_Ovf_callback();
657 }
658 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
659 {
660 TMR6_1_Udf_callback();
661 }
662 }
663 #endif
664 #endif
665
666 #ifdef BSP_USING_PULSE_ENCODER_TMR6_2
TMR6_2_Ovf_callback(void)667 void TMR6_2_Ovf_callback(void)
668 {
669 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler, TMR6_FLAG_OVF);
670 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].Over_Under_Flowcount++;
671 }
TMR6_2_Udf_callback(void)672 void TMR6_2_Udf_callback(void)
673 {
674 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler, TMR6_FLAG_UDF);
675 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].Over_Under_Flowcount--;
676 }
677 #if defined (HC32F448) || defined (HC32F472)
TMR6_2_Ovf_Udf_Handler(void)678 void TMR6_2_Ovf_Udf_Handler(void)
679 {
680 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler;
681 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
682 {
683 TMR6_2_Ovf_callback();
684 }
685 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
686 {
687 TMR6_2_Udf_callback();
688 }
689 }
690 #endif
691 #endif
692
693 #ifdef BSP_USING_PULSE_ENCODER_TMR6_3
TMR6_3_Ovf_callback(void)694 void TMR6_3_Ovf_callback(void)
695 {
696 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler, TMR6_FLAG_OVF);
697 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].Over_Under_Flowcount++;
698 }
TMR6_3_Udf_callback(void)699 void TMR6_3_Udf_callback(void)
700 {
701 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler, TMR6_FLAG_UDF);
702 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].Over_Under_Flowcount--;
703 }
704 #if defined (HC32F472)
TMR6_3_Ovf_Udf_Handler(void)705 void TMR6_3_Ovf_Udf_Handler(void)
706 {
707 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler;
708 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
709 {
710 TMR6_3_Ovf_callback();
711 }
712 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
713 {
714 TMR6_3_Udf_callback();
715 }
716 }
717 #endif
718 #endif
719
720 #ifdef BSP_USING_PULSE_ENCODER_TMR6_4
TMR6_4_Ovf_callback(void)721 void TMR6_4_Ovf_callback(void)
722 {
723 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler, TMR6_FLAG_OVF);
724 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].Over_Under_Flowcount++;
725 }
TMR6_4_Udf_callback(void)726 void TMR6_4_Udf_callback(void)
727 {
728 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler, TMR6_FLAG_UDF);
729 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].Over_Under_Flowcount--;
730 }
731 #if defined (HC32F472)
TMR6_4_Ovf_Udf_Handler(void)732 void TMR6_4_Ovf_Udf_Handler(void)
733 {
734 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler;
735 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
736 {
737 TMR6_4_Ovf_callback();
738 }
739 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
740 {
741 TMR6_4_Udf_callback();
742 }
743 }
744 #endif
745 #endif
746
747 #ifdef BSP_USING_PULSE_ENCODER_TMR6_5
TMR6_5_Ovf_callback(void)748 void TMR6_5_Ovf_callback(void)
749 {
750 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler, TMR6_FLAG_OVF);
751 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].Over_Under_Flowcount++;
752 }
TMR6_5_Udf_callback(void)753 void TMR6_5_Udf_callback(void)
754 {
755 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler, TMR6_FLAG_UDF);
756 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].Over_Under_Flowcount--;
757 }
758 #if defined (HC32F472)
TMR6_5_Ovf_Udf_Handler(void)759 void TMR6_5_Ovf_Udf_Handler(void)
760 {
761 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler;
762 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
763 {
764 TMR6_5_Ovf_callback();
765 }
766 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
767 {
768 TMR6_5_Udf_callback();
769 }
770 }
771 #endif
772 #endif
773
774 #ifdef BSP_USING_PULSE_ENCODER_TMR6_6
TMR6_6_Ovf_callback(void)775 void TMR6_6_Ovf_callback(void)
776 {
777 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler, TMR6_FLAG_OVF);
778 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].Over_Under_Flowcount++;
779 }
TMR6_6_Udf_callback(void)780 void TMR6_6_Udf_callback(void)
781 {
782 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler, TMR6_FLAG_UDF);
783 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].Over_Under_Flowcount--;
784 }
785 #if defined (HC32F472)
TMR6_6_Ovf_Udf_Handler(void)786 void TMR6_6_Ovf_Udf_Handler(void)
787 {
788 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler;
789 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
790 {
791 TMR6_6_Ovf_callback();
792 }
793 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
794 {
795 TMR6_6_Udf_callback();
796 }
797 }
798 #endif
799 #endif
800
801 #ifdef BSP_USING_PULSE_ENCODER_TMR6_7
TMR6_7_Ovf_callback(void)802 void TMR6_7_Ovf_callback(void)
803 {
804 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].tmr_handler, TMR6_FLAG_OVF);
805 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].Over_Under_Flowcount++;
806 }
TMR6_7_Udf_callback(void)807 void TMR6_7_Udf_callback(void)
808 {
809 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].tmr_handler, TMR6_FLAG_UDF);
810 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].Over_Under_Flowcount--;
811 }
812 #if defined (HC32F472)
TMR6_7_Ovf_Udf_Handler(void)813 void TMR6_7_Ovf_Udf_Handler(void)
814 {
815 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].tmr_handler;
816 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
817 {
818 TMR6_7_Ovf_callback();
819 }
820 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
821 {
822 TMR6_7_Udf_callback();
823 }
824 }
825 #endif
826 #endif
827
828 #ifdef BSP_USING_PULSE_ENCODER_TMR6_8
TMR6_8_Ovf_callback(void)829 void TMR6_8_Ovf_callback(void)
830 {
831 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].tmr_handler, TMR6_FLAG_OVF);
832 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].Over_Under_Flowcount++;
833 }
TMR6_8_Udf_callback(void)834 void TMR6_8_Udf_callback(void)
835 {
836 TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].tmr_handler, TMR6_FLAG_UDF);
837 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].Over_Under_Flowcount--;
838 }
839 #if defined (HC32F472)
TMR6_8_Ovf_Udf_Handler(void)840 void TMR6_8_Ovf_Udf_Handler(void)
841 {
842 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].tmr_handler;
843 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
844 {
845 TMR6_8_Ovf_callback();
846 }
847 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
848 {
849 TMR6_8_Udf_callback();
850 }
851 }
852 #endif
853 #endif
854
855 #ifdef BSP_USING_PULSE_ENCODER_TMR6_9
856 #if defined (HC32F472)
TMR6_9_Ovf_Udf_Handler(void)857 void TMR6_9_Ovf_Udf_Handler(void)
858 {
859 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_9_INDEX].tmr_handler;
860 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
861 {
862 TMR6_ClearStatus(tmr_handler, TMR6_FLAG_OVF);
863 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_9_INDEX].Over_Under_Flowcount++;
864 }
865 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
866 {
867 TMR6_ClearStatus(tmr_handler, TMR6_FLAG_UDF);
868 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_9_INDEX].Over_Under_Flowcount--;
869 }
870 }
871 #endif
872 #endif
873
874 #ifdef BSP_USING_PULSE_ENCODER_TMR6_10
875 #if defined (HC32F472)
TMR6_10_Ovf_Udf_Handler(void)876 void TMR6_10_Ovf_Udf_Handler(void)
877 {
878 CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_10_INDEX].tmr_handler;
879 if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_OVF) == SET)
880 {
881 TMR6_ClearStatus(tmr_handler, TMR6_FLAG_OVF);
882 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_10_INDEX].Over_Under_Flowcount++;
883 }
884 else if (TMR6_GetStatus(tmr_handler, TMR6_FLAG_UDF) == SET)
885 {
886 TMR6_ClearStatus(tmr_handler, TMR6_FLAG_UDF);
887 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_10_INDEX].Over_Under_Flowcount--;
888 }
889 }
890 #endif
891 #endif
892
893 /**
894 * @brief This function gets pulse_encoder_tim6 irq handle.
895 * @param None
896 * @retval None
897 */
hc32_get_pulse_encoder_tmr6_callback(void)898 static void hc32_get_pulse_encoder_tmr6_callback(void)
899 {
900 #ifdef BSP_USING_PULSE_ENCODER_TMR6_1
901 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].isr.Irq_Ovf_Callback = TMR6_1_Ovf_callback;
902 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].isr.Irq_Udf_Callback = TMR6_1_Udf_callback;
903 #endif
904 #ifdef BSP_USING_PULSE_ENCODER_TMR6_2
905 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].isr.Irq_Ovf_Callback = TMR6_2_Ovf_callback;
906 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].isr.Irq_Udf_Callback = TMR6_2_Udf_callback;
907 #endif
908 #ifdef BSP_USING_PULSE_ENCODER_TMR6_3
909 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].isr.Irq_Ovf_Callback = TMR6_3_Ovf_callback;
910 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].isr.Irq_Udf_Callback = TMR6_3_Udf_callback;
911 #endif
912 #ifdef BSP_USING_PULSE_ENCODER_TMR6_4
913 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].isr.Irq_Ovf_Callback = TMR6_4_Ovf_callback;
914 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].isr.Irq_Udf_Callback = TMR6_4_Udf_callback;
915 #endif
916 #ifdef BSP_USING_PULSE_ENCODER_TMR6_5
917 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].isr.Irq_Ovf_Callback = TMR6_5_Ovf_callback;
918 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].isr.Irq_Udf_Callback = TMR6_5_Udf_callback;
919 #endif
920 #ifdef BSP_USING_PULSE_ENCODER_TMR6_6
921 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].isr.Irq_Ovf_Callback = TMR6_6_Ovf_callback;
922 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].isr.Irq_Udf_Callback = TMR6_6_Udf_callback;
923 #endif
924 #ifdef BSP_USING_PULSE_ENCODER_TMR6_7
925 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].isr.Irq_Ovf_Callback = TMR6_7_Ovf_callback;
926 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].isr.Irq_Udf_Callback = TMR6_7_Udf_callback;
927 #endif
928 #ifdef BSP_USING_PULSE_ENCODER_TMR6_8
929 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].isr.Irq_Ovf_Callback = TMR6_8_Ovf_callback;
930 hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].isr.Irq_Udf_Callback = TMR6_8_Udf_callback;
931 #endif
932 }
933
_tmr6_pulse_encoder_init(struct rt_pulse_encoder_device * pulse_encoder)934 rt_err_t _tmr6_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
935 {
936 stc_tmr6_init_t stcTmr6Init;
937 struct hc32_irq_config irq_config;
938 struct hc32_pulse_encoder_tmr6_device *hc32_device;
939 hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
940
941 /* Enable Timer6 peripheral clock. */
942 FCG_Fcg2PeriphClockCmd(hc32_device->u32PeriphClock, ENABLE);
943
944 (void)TMR6_StructInit(&stcTmr6Init);
945 /* Initializes position-count unit. */
946 stcTmr6Init.u8CountSrc = TMR6_CNT_SRC_HW;
947 stcTmr6Init.hw_count.u32CountUpCond = hc32_device->hw_count.u32CountUpCond;
948 stcTmr6Init.hw_count.u32CountDownCond = hc32_device->hw_count.u32CountDownCond;
949 stcTmr6Init.u32PeriodValue = hc32_device->u32PeriodValue;
950 (void)TMR6_Init(hc32_device->tmr_handler, &stcTmr6Init);
951
952 /* OVF interrupt configuration */
953 irq_config.irq_num = hc32_device->isr.enIRQn_Ovf;
954 irq_config.int_src = hc32_device->isr.enIntSrc_Ovf;
955 irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Ovf;
956 /* register interrupt */
957 hc32_install_irq_handler(&irq_config, hc32_device->isr.Irq_Ovf_Callback, RT_TRUE);
958 /* UDF interrupt configuration */
959 irq_config.irq_num = hc32_device->isr.enIRQn_Udf;
960 irq_config.int_src = hc32_device->isr.enIntSrc_Udf;
961 irq_config.irq_prio = hc32_device->isr.u8Int_Prio_Udf;
962 /* register interrupt */
963 hc32_install_irq_handler(&irq_config, hc32_device->isr.Irq_Udf_Callback, RT_TRUE);
964 /* Enable the specified interrupts of Timer6. */
965 TMR6_IntCmd(hc32_device->tmr_handler, TMR6_INT_OVF | TMR6_INT_UDF, ENABLE);
966
967 LOG_D("_tmr6_pulse_encoder_init");
968
969 return RT_EOK;
970 }
971
_tmr6_pulse_encoder_clear_count(struct rt_pulse_encoder_device * pulse_encoder)972 rt_err_t _tmr6_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
973 {
974 rt_uint8_t startFlag = RT_FALSE;
975 struct hc32_pulse_encoder_tmr6_device *hc32_device;
976 hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
977 hc32_device->Over_Under_Flowcount = 0;
978 if (READ_REG32_BIT(hc32_device->tmr_handler->GCONR, TMR6_GCONR_START) == TMR6_GCONR_START)
979 {
980 startFlag = RT_TRUE;
981 }
982 TMR6_Stop(hc32_device->tmr_handler);
983 TMR6_SetCountValue(hc32_device->tmr_handler, 0);
984 if (RT_TRUE == startFlag)
985 {
986 TMR6_Start(hc32_device->tmr_handler);
987 }
988 return RT_EOK;
989 }
990
_tmr6_pulse_encoder_get_count(struct rt_pulse_encoder_device * pulse_encoder)991 rt_int32_t _tmr6_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
992 {
993 struct hc32_pulse_encoder_tmr6_device *hc32_device;
994 hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
995 return (rt_int32_t)((rt_int16_t)TMR6_GetCountValue(hc32_device->tmr_handler) + (hc32_device->Over_Under_Flowcount * (hc32_device->u32PeriodValue + 1)));
996 }
997
_tmr6_pulse_encoder_control(struct rt_pulse_encoder_device * pulse_encoder,rt_uint32_t cmd,void * args)998 rt_err_t _tmr6_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
999 {
1000 rt_err_t result;
1001 struct hc32_pulse_encoder_tmr6_device *hc32_device;
1002 hc32_device = (struct hc32_pulse_encoder_tmr6_device *)pulse_encoder;
1003
1004 result = RT_EOK;
1005
1006 switch (cmd)
1007 {
1008 case PULSE_ENCODER_CMD_ENABLE:
1009 TMR6_Start(hc32_device->tmr_handler);
1010 LOG_D("TMR6_Start");
1011 break;
1012 case PULSE_ENCODER_CMD_DISABLE:
1013 TMR6_Stop(hc32_device->tmr_handler);
1014 LOG_D("TMR6_Stop");
1015 break;
1016 default:
1017 result = -RT_ENOSYS;
1018 break;
1019 }
1020
1021 return result;
1022 }
1023
1024 static const struct rt_pulse_encoder_ops _tmr6_ops =
1025 {
1026 .init = _tmr6_pulse_encoder_init,
1027 .get_count = _tmr6_pulse_encoder_get_count,
1028 .clear_count = _tmr6_pulse_encoder_clear_count,
1029 .control = _tmr6_pulse_encoder_control,
1030 };
1031
1032 #endif /* BSP_USING_TMR6_PULSE_ENCODER */
1033
rt_hw_pulse_encoder_init(void)1034 static int rt_hw_pulse_encoder_init(void)
1035 {
1036 int result;
1037
1038 result = RT_EOK;
1039
1040 #if defined(BSP_USING_TMRA_PULSE_ENCODER)
1041 extern rt_err_t rt_hw_board_pulse_encoder_tmra_init(void);
1042 result = rt_hw_board_pulse_encoder_tmra_init();
1043 hc32_get_pulse_encoder_tmra_callback();
1044 for (int i = 0; i < sizeof(hc32_pulse_encoder_tmra_obj) / sizeof(hc32_pulse_encoder_tmra_obj[0]); i++)
1045 {
1046 hc32_pulse_encoder_tmra_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
1047 hc32_pulse_encoder_tmra_obj[i].pulse_encoder.ops = &_tmra_ops;
1048
1049 if (rt_device_pulse_encoder_register(&hc32_pulse_encoder_tmra_obj[i].pulse_encoder, hc32_pulse_encoder_tmra_obj[i].name, RT_NULL) != RT_EOK)
1050 {
1051 LOG_E("%s register failed", hc32_pulse_encoder_tmra_obj[i].name);
1052 result = -RT_ERROR;
1053 }
1054 }
1055 #endif /* BSP_USING_TMRA_PULSE_ENCODER */
1056
1057 #if defined(BSP_USING_TMR6_PULSE_ENCODER)
1058 extern rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void);
1059 result = rt_hw_board_pulse_encoder_tmr6_init();
1060 hc32_get_pulse_encoder_tmr6_callback();
1061 for (int i = 0; i < sizeof(hc32_pulse_encoder_tmr6_obj) / sizeof(hc32_pulse_encoder_tmr6_obj[0]); i++)
1062 {
1063 hc32_pulse_encoder_tmr6_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
1064 hc32_pulse_encoder_tmr6_obj[i].pulse_encoder.ops = &_tmr6_ops;
1065
1066 if (rt_device_pulse_encoder_register(&hc32_pulse_encoder_tmr6_obj[i].pulse_encoder, hc32_pulse_encoder_tmr6_obj[i].name, RT_NULL) != RT_EOK)
1067 {
1068 LOG_E("%s register failed", hc32_pulse_encoder_tmr6_obj[i].name);
1069 result = -RT_ERROR;
1070 }
1071 }
1072 #endif /* BSP_USING_TMR6_PULSE_ENCODER */
1073
1074 return result;
1075 }
1076 INIT_BOARD_EXPORT(rt_hw_pulse_encoder_init);
1077
1078 #endif /* RT_USING_PULSE_ENCODER */
1079