1 /*
2  * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2023-06-15     CDT          first version
9  */
10 
11 #ifndef __DRV_QSPI_H__
12 #define __DRV_QSPI_H__
13 
14 #include <rtthread.h>
15 #include <rtdevice.h>
16 #include "drv_dma.h"
17 
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21 
22 
23 struct hc32_hw_qspi_cs
24 {
25     rt_uint16_t pin;
26 };
27 
28 struct hc32_qspi_irq_config
29 {
30     struct hc32_irq_config irq_config;
31     func_ptr_t             irq_callback;
32 };
33 
34 struct hc32_qspi_config
35 {
36     CM_QSPI_TypeDef             *Instance;
37     rt_uint32_t                 clock;
38     rt_uint32_t                 timeout;
39     struct hc32_qspi_irq_config err_irq;
40 #ifdef BSP_QSPI_USING_DMA
41     struct dma_config           *dma_qspi;
42 #if defined (HC32F448) || defined (HC32F4A8)
43     rt_uint16_t                 *dma_tx_buf;
44     rt_uint16_t                 dma_tx_buf_size;    /* unit: half-word, DMA data width of QSPI transmitting is 16bit */
45 #endif
46 #endif
47 };
48 
49 struct hc32_qspi_bus
50 {
51     struct hc32_qspi_config     *config;
52     char                        *bus_name;
53 };
54 
55 rt_err_t rt_hw_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)());
56 
57 #ifdef __cplusplus
58 }
59 #endif
60 
61 #endif /* __DRV_QSPI_H__ */
62