1 /*****************************************************************************
2 * Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
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10 * This software contains source code for use with HDSC
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42 /******************************************************************************/
43 /** \file dma.h
44 **
45 ** A detailed description is available at
46 ** @link DmacGroup Dmac description @endlink
47 **
48 **   - 2018-03-09  1.0  Hongjh First version for Device Driver Library of Dmac.
49 **
50 ******************************************************************************/
51 #ifndef __DMAC_H__
52 #define __DMAC_H__
53 
54 /*******************************************************************************
55 * Include files
56 ******************************************************************************/
57 #include "ddl.h"
58 
59 /* C binding of definitions if building with C++ compiler */
60 #ifdef __cplusplus
61 extern "C"
62 {
63 #endif
64 
65   /**
66   *******************************************************************************
67   ** \defgroup DmacGroup Direct Memory Access Control(DMAC)
68   **
69   ******************************************************************************/
70   //@{
71 
72   /*******************************************************************************
73   * Global type definitions ('typedef')
74   ******************************************************************************/
75   /**
76   *******************************************************************************
77   ** \brief DMA Channel
78   **
79   ******************************************************************************/
80   typedef enum en_dma_channel
81   {
82     DmaCh0                          = 0U,    ///< DMA channel 0
83     DmaCh1                          = 1U,    ///< DMA channel 1
84     DmaChMax                        = 2U     ///< DMA channel max
85   } en_dma_channel_t;
86   /**
87   *******************************************************************************
88   ** \brief DMA priority
89   **
90   ******************************************************************************/
91   typedef enum en_dma_priority
92   {
93     DmaPriorityFix                          = 0U,    ///< DMA channel priority fix (CH0>CH1)
94     DmaPriorityLoop                         = 1U,    ///< DMA channel priority loop
95   } en_dma_priority_t;
96 
97   /**
98   *******************************************************************************
99   ** \brief DMA transfer data width
100   **
101   ******************************************************************************/
102   typedef enum en_dma_transfer_width
103   {
104     Dma8Bit                         = 0U,    ///< 8 bit transfer via DMA
105     Dma16Bit                        = 1U,    ///< 16 bit transfer via DMA
106     Dma32Bit                        = 2U     ///< 32 bit transfer via DMA
107   } en_dma_transfer_width_t;
108 
109   /**
110   *******************************************************************************
111   ** \brief DMA transfer mode
112   **
113   ******************************************************************************/
114   typedef enum en_dma_transfer_mode
115   {
116     DmaBlock                        = 0U,    ///< block transfer via DMA
117     DmaBurst                        = 1U,    ///< burst transfer via DMA
118   } en_dma_transfer_mode_t;
119 
120   /**
121   *******************************************************************************
122   ** \brief DMA flag
123   **
124   ******************************************************************************/
125   typedef enum en_dma_stat
126   {
127     DEFAULT							            = 0U,    ///< Reserve
128     DmaAddOverflow									= 1U,   ///< DMA address overflow
129     DmaHALT                         = 2U,    ///< DMA HALT
130     DmaAccSCRErr                    = 3U,    ///< DMA access source address error
131     DmaAccDestErr                   = 4U,    ///< DMA access dest address error
132     DmaTransferComplete             = 5U,    ///< DMA transfer complete
133     DmaTransferPause                = 7U,    ///< DMA transfer pause
134   } en_dma_stat_t;
135 
136   /**
137   *******************************************************************************
138   ** \brief DMA address mode
139   **
140   ******************************************************************************/
141   typedef enum en_address_mode
142   {
143     AddressIncrease                 = 0U,    ///< Address increased
144     AddressFix                      = 1U,    ///< Address fixed
145   } en_address_mode_t;
146 
147   /**
148   *******************************************************************************
149   ** \brief DMA repeat tranfer
150   **
151   ******************************************************************************/
152   typedef enum en_dma_msk
153   {
154     OneTranfer                      = 0U,    ///< One Tranfer
155     ContinuousTranfer               = 1U,    ///< Continuous Tranfer
156   } en_dma_msk_t;
157   /**
158   *******************************************************************************
159   ** \brief DMA trigger selection
160   **
161   ******************************************************************************/
162   typedef enum stc_dma_trig_sel
163   {
164     SWTrig                         = 0U,     ///< Select DMA software trig
165     SPI0RXTrig                     = 32U,    ///< Select DMA hardware trig 0
166     SPI0TXTrig                     = 33U,    ///< Select DMA hardware trig 1
167     SPI1RXTrig                     = 34U,    ///< Select DMA hardware trig 2
168     SPI1TXTrig                     = 35U,    ///< Select DMA hardware trig 3
169     ADCJQRTrig                     = 36U,    ///< Select DMA hardware trig 4
170     ADCSQRTrig                     = 37U,    ///< Select DMA hardware trig 5
171     LCDTxTrig                      = 38U,    ///< Select DMA hardware trig 6
172     Uart0RxTrig                    = 40U,    ///< Select DMA hardware trig 8
173     Uart0TxTrig                    = 41U,    ///< Select DMA hardware trig 9
174     Uart1RxTrig                    = 42U,    ///< Select DMA hardware trig 10
175     Uart1TxTrig                    = 43U,    ///< Select DMA hardware trig 11
176     LpUart0RxTrig                  = 44U,    ///< Select DMA hardware trig 12
177     LpUart0TxTrig                  = 45U,    ///< Select DMA hardware trig 13
178     LpUart1RxTrig                  = 46U,    ///< Select DMA hardware trig 14
179     LpUart1TxTrig                  = 47U,    ///< Select DMA hardware trig 15
180     TIM0ATrig                      = 50U,    ///< Select DMA hardware trig 18
181     TIM0BTrig                      = 51U,    ///< Select DMA hardware trig 19
182     TIM1ATrig                      = 52U,    ///< Select DMA hardware trig 20
183     TIM1BTrig                      = 53U,    ///< Select DMA hardware trig 21
184     TIM2ATrig                      = 54U,    ///< Select DMA hardware trig 22
185     TIM2BTrig                      = 55U,    ///< Select DMA hardware trig 23
186     TIM3ATrig                      = 56U,    ///< Select DMA hardware trig 24
187     TIM3BTrig                      = 57U,    ///< Select DMA hardware trig 25
188     TIM4ATrig                      = 58U,    ///< Select DMA hardware trig 26
189     TIM4BTrig                      = 59U,    ///< Select DMA hardware trig 27
190     TIM5ATrig                      = 60U,    ///< Select DMA hardware trig 28
191     TIM5BTrig                      = 61U,    ///< Select DMA hardware trig 29
192     TIM6ATrig                      = 62U,    ///< Select DMA hardware trig 30
193     TIM6BTrig                      = 63U,    ///< Select DMA hardware trig 31
194   }en_dma_trig_sel_t;
195   /**
196   *******************************************************************************
197   ** \brief DMA interrupt selection
198   **
199   ******************************************************************************/
200 typedef struct stc_dma_irq
201   {
202     boolean_t TrnErrIrq;                        ///< Select DMA transfer error interrupt
203     boolean_t TrnCpltIrq;                      ///< Select DMA transfer completion interrupt
204   }stc_dma_irq_sel_t;
205 
206 
207 
208   /**
209   *******************************************************************************
210   ** \brief DMA configuration
211   **
212   ******************************************************************************/
213   typedef struct stc_dma_config
214   {
215     en_dma_transfer_mode_t enMode;
216 
217     uint16_t u16BlockSize;                      ///< Transfer Block counter
218     uint16_t u16TransferCnt;                    ///< Transfer counter
219     en_dma_transfer_width_t enTransferWidth;    ///< DMA transfer width (see #en_dma_transfer_width_t for details)
220 
221     en_address_mode_t enSrcAddrMode;            ///< Source address mode(see #en_source_address_mode_t for details)
222     en_address_mode_t enDstAddrMode;            ///< Destination address mode(see #en_dest_address_mode_t for details)
223 
224     boolean_t bSrcAddrReloadCtl;  ///< Source address reload(TRUE: reload;FALSE: reload forbidden)
225     boolean_t bDestAddrReloadCtl;  ///< Dest address reload(TRUE: reload;FALSE: reload forbidden)
226     boolean_t bSrcBcTcReloadCtl;  ///< Bc/Tc address reload(TRUE: reload;FALSE: reload forbidden)
227     uint32_t u32SrcAddress;           ///< Source address>
228     uint32_t u32DstAddress;           ///< Dest address>
229     boolean_t bMsk;                   ///0: clear the bit (CONFA:ENS) after tarnfer;1: remain the bit (CONFA:ENS) after tarnfer
230 
231     en_dma_trig_sel_t enRequestNum;     ///< DMA trigger request number
232   } stc_dma_config_t;
233   /**
234  ******************************************************************************
235  ** \brief  DMA中断回调函数
236  *****************************************************************************/
237 typedef struct stc_dma_irq_calbakfn_pt
238 {
239     /*! Dma传输完成中断回调函数指针*/
240     func_ptr_t  pfnDma0TranferCompleteIrq;
241      /*! Dma传输完成中断回调函数指针*/
242     func_ptr_t  pfnDma1TranferCompleteIrq;
243     /*! Dma传输错误中断回调函数指针*/
244     func_ptr_t  pfnDma0TranferErrIrq;
245     /*! Dma传输错误中断回调函数指针*/
246     func_ptr_t  pfnDma1TranferErrIrq;
247 }stc_dma_irq_calbakfn_pt_t;
248   /*******************************************************************************
249   * Global pre-processor symbols/macros ('#define')
250   ******************************************************************************/
251 
252   /*******************************************************************************
253   * Global variable definitions ('extern')
254   ******************************************************************************/
255 
256   /*******************************************************************************
257   * Global function prototypes (definition in C source)
258   ******************************************************************************/
259   en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig);
260 
261   void Dma_SwTrigger(en_dma_channel_t enCh);
262 
263   void Dma_Enable(void);
264   void Dma_Disable(void);
265 
266   void Dma_Start(en_dma_channel_t enCh);
267   void Dma_Stop(en_dma_channel_t enCh);
268 
269   en_result_t Dma_EnableChannel(en_dma_channel_t enCh);
270   en_result_t Dma_DisableChannel(en_dma_channel_t enCh);
271 
272   en_result_t Dma_SetTriggerSel(en_dma_channel_t enCh, en_dma_trig_sel_t enTrgSel);
273 
274   en_result_t Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address);
275   en_result_t Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address);
276 
277   en_result_t Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize);
278   en_result_t Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt);
279 
280 
281   en_result_t Dma_SetSourceIncMode(en_dma_channel_t enCh, en_address_mode_t enMode);
282   en_result_t Dma_SetDestinationIncMode(en_dma_channel_t enCh, en_address_mode_t enMode);
283 
284   en_result_t Dma_EnableSourceRload(en_dma_channel_t enCh);
285   en_result_t Dma_DisableSourceRload(en_dma_channel_t enCh);
286 
287   en_result_t Dma_EnableDestinationRload(en_dma_channel_t enCh);
288   en_result_t Dma_DisableDestinationRload(en_dma_channel_t enCh);
289 
290   en_result_t Dma_EnableContinusTranfer(en_dma_channel_t enCh);
291   en_result_t Dma_DisableContinusTranfer(en_dma_channel_t enCh);
292 
293   en_result_t Dma_EnableBcTcReload(en_dma_channel_t enCh);
294   en_result_t Dma_DisableBcTcReload(en_dma_channel_t enCh);
295 
296   void Dma_HaltTranfer(void);
297   void Dma_RecoverTranfer(void);
298   en_result_t Dma_PauseChannelTranfer(en_dma_channel_t enCh);
299   en_result_t Dma_RecoverChannelTranfer(en_dma_channel_t enCh);
300 
301   en_result_t Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth);
302 
303   en_result_t Dma_SetChPriority(en_dma_priority_t enPrio);
304 
305   en_result_t Dma_EnableChannelIrq(en_dma_channel_t enCh);
306   en_result_t Dma_DisableChannelIrq(en_dma_channel_t enCh);
307 
308   en_result_t Dma_EnableChannelErrIrq(en_dma_channel_t enCh);
309   en_result_t Dma_DisableChannelErrIrq(en_dma_channel_t enCh);
310 
311   en_result_t Dma_ConfigIrq(en_dma_channel_t enCh,stc_dma_irq_sel_t* stcDmaIrqCfg,stc_dma_irq_calbakfn_pt_t* pstcDmaIrqCalbaks);
312 
313 
314   en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh);
315 
316   void Dma_ClrStat(en_dma_channel_t enCh);
317   //@} // DmacGroup
318 
319 #ifdef __cplusplus
320 }
321 #endif
322 
323 #endif /* __DMAC_H__ */
324 
325 /*******************************************************************************
326 * EOF (not truncated)
327 ******************************************************************************/
328