1 /******************************************************************************* 2 * Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. 3 * 4 * This software is owned and published by: 5 * Huada Semiconductor Co.,Ltd ("HDSC"). 6 * 7 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 8 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. 9 * 10 * This software contains source code for use with HDSC 11 * components. This software is licensed by HDSC to be adapted only 12 * for use in systems utilizing HDSC components. HDSC shall not be 13 * responsible for misuse or illegal use of this software for devices not 14 * supported herein. HDSC is providing this software "AS IS" and will 15 * not be responsible for issues arising from incorrect user implementation 16 * of the software. 17 * 18 * Disclaimer: 19 * HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, 20 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 21 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 22 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 23 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 24 * WARRANTY OF NONINFRINGEMENT. 25 * HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 26 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 27 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 28 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 29 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 31 * SAVINGS OR PROFITS, 32 * EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 33 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR 34 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 35 * FROM, THE SOFTWARE. 36 * 37 * This software may be replicated in part or whole for the licensed use, 38 * with the restriction that this Disclaimer and Copyright notice must be 39 * included with each copy of this software, whether used in part or whole, 40 * at all times. 41 */ 42 /******************************************************************************/ 43 /** \file sysctrl.h 44 ** 45 ** Headerfile for SYSCTRL functions 46 ** @link SYSCTRL Group Some description @endlink 47 ** 48 ** History: 49 ** - 2018-04-15 Lux First Version 50 ** 51 ******************************************************************************/ 52 53 #ifndef __SYSCTRL_H__ 54 #define __SYSCTRL_H__ 55 56 /******************************************************************************* 57 * Include files 58 ******************************************************************************/ 59 #include "ddl.h" 60 #include "interrupts_hc32l136.h" 61 62 #ifdef __cplusplus 63 extern "C" 64 { 65 #endif 66 67 /** 68 ****************************************************************************** 69 ** \defgroup SysCtrlGroup (SYSCTRL) 70 ** 71 ******************************************************************************/ 72 //@{ 73 74 /** 75 ******************************************************************************* 76 ** function prototypes. 77 ******************************************************************************/ 78 79 /****************************************************************************** 80 * Global type definitions 81 ******************************************************************************/ 82 #define SYSTEM_XTH 32*1000*1000u //默认32MHz,具体值应根据实际系统修改 83 #define SYSTEM_XTL 32768u //默认32768Hz,具体值应根据实际系统修改 84 85 /** 86 ******************************************************************************* 87 ** \brief 系统时钟输入源类型定义 88 ** \note 89 ******************************************************************************/ 90 typedef enum en_sysctrl_clk_source 91 { 92 SysctrlClkRCH = 0u, ///< 内部高速时钟 93 SysctrlClkXTH = 1u, ///< 外部高速时钟 94 SysctrlClkRCL = 2u, ///< 内部低速时钟 95 SysctrlClkXTL = 3u, ///< 外部低速时钟 96 SysctrlClkPLL = 4u, ///< PLL时钟 97 }en_sysctrl_clk_source_t; 98 99 /** 100 ******************************************************************************* 101 ** \brief RCH频率值枚举类型定义 102 ******************************************************************************/ 103 typedef enum en_sysctrl_rch_freq 104 { 105 SysctrlRchFreq4MHz = 0u, ///< 4MHz 106 SysctrlRchFreq8MHz = 1u, ///< 8MHz 107 SysctrlRchFreq16MHz = 2u, ///< 16MHz 108 SysctrlRchFreq22_12MHz = 3u, ///< 22.12MHz 109 SysctrlRchFreq24MHz = 4u, ///< 24MHz 110 }en_sysctrl_rch_freq_t; 111 112 /** 113 ******************************************************************************* 114 ** \brief XTAL驱动能力类型定义 115 ******************************************************************************/ 116 typedef enum en_sysctrl_xtal_driver 117 { 118 SysctrlXtalDriver0 = 0u, ///< 最弱驱动能力 119 SysctrlXtalDriver1 = 1u, ///< 弱驱动能力 120 SysctrlXtalDriver2 = 3u, ///< 一般驱动能力 121 SysctrlXtalDriver3 = 3u, ///< 最强驱动能力 122 }en_sysctrl_xtal_driver_t; 123 124 /** 125 ******************************************************************************* 126 ** \brief XTH频率值范围选择类型定义 127 ******************************************************************************/ 128 typedef enum en_sysctrl_xth_freq 129 { 130 SysctrlXthFreq4_6MHz = 0u, ///< 4~6MHz 131 SysctrlXthFreq6_12MHz = 1u, ///< 6~12MHz 132 SysctrlXthFreq12_20MHz = 2u, ///< 12~20MHz 133 SysctrlXthFreq20_32MHz = 3u, ///< 20~32MHz 134 }en_sysctrl_xth_freq_t; 135 136 /** 137 ******************************************************************************* 138 ** \brief XTH时钟稳定周期数类型定义 139 ******************************************************************************/ 140 typedef enum en_sysctrl_xth_cycle 141 { 142 SysctrlXthStableCycle256 = 0u, ///< 256 个周期数 143 SysctrlXthStableCycle1024 = 1u, ///< 1024 个周期数 144 SysctrlXthStableCycle4096 = 2u, ///< 4096 个周期数 145 SysctrlXthStableCycle16384 = 3u, ///< 16384 个周期数 146 }en_sysctrl_xth_cycle_t; 147 148 /** 149 ******************************************************************************* 150 ** \brief RCL频率值枚举类型定义 151 ******************************************************************************/ 152 typedef enum en_sysctrl_rcl_freq 153 { 154 SysctrlRclFreq32768 = 0u, ///< 32.768KHz 155 SysctrlRclFreq38400 = 1u, ///< 38.4KHz 156 }en_sysctrl_rcl_freq_t; 157 158 /** 159 ******************************************************************************* 160 ** \brief RCL时钟稳定周期数类型定义 161 ******************************************************************************/ 162 typedef enum en_sysctrl_rcl_cycle 163 { 164 SysctrlRclStableCycle4 = 0u, ///< 4 个周期数 165 SysctrlRclStableCycle16 = 1u, ///< 16 个周期数 166 SysctrlRclStableCycle64 = 2u, ///< 64 个周期数 167 SysctrlRclStableCycle256 = 3u, ///< 256 个周期数 168 }en_sysctrl_rcl_cycle_t; 169 170 /** 171 ******************************************************************************* 172 ** \brief XTL时钟稳定周期数类型定义 173 ******************************************************************************/ 174 typedef enum en_sysctrl_xtl_cycle 175 { 176 SysctrlXtlStableCycle256 = 0u, ///< 256 个周期数 177 SysctrlXtlStableCycle1024 = 1u, ///< 1024 个周期数 178 SysctrlXtlStableCycle4096 = 2u, ///< 4096 个周期数 179 SysctrlXtlStableCycle16384 = 3u, ///< 16384 个周期数 180 }en_sysctrl_xtl_cycle_t; 181 182 /** 183 ******************************************************************************* 184 ** \brief XTL晶体振幅枚举类型定义 185 ******************************************************************************/ 186 typedef enum en_sysctrl_xtl_amp 187 { 188 SysctrlXtlAmp0 = 0u, ///< 最小振幅 189 SysctrlXtlAmp1 = 1u, ///< 小振幅 190 SysctrlXtlAmp2 = 2u, ///< 一般振幅 191 SysctrlXtlAmp3 = 3u, ///< 最大振幅 192 }en_sysctrl_xtl_amp_t; 193 194 /** 195 ******************************************************************************* 196 ** \brief PLL时钟稳定周期数类型定义 197 ******************************************************************************/ 198 typedef enum en_sysctrl_pll_cycle 199 { 200 SysctrlPllStableCycle128 = 0u, ///< 128个周期数 201 SysctrlPllStableCycle256 = 1u, ///< 256个周期数 202 SysctrlPllStableCycle512 = 2u, ///< 512个周期数 203 SysctrlPllStableCycle1024 = 3u, ///< 1024个周期数 204 SysctrlPllStableCycle2048 = 4u, ///< 2048个周期数 205 SysctrlPllStableCycle4096 = 5u, ///< 4096个周期数 206 SysctrlPllStableCycle8192 = 6u, ///< 8192个周期数 207 SysctrlPllStableCycle16384 = 7u, ///< 16384个周期数 208 }en_sysctrl_pll_cycle_t; 209 210 /** 211 ******************************************************************************* 212 ** \brief PLL输入频率范围类型定义 213 ******************************************************************************/ 214 typedef enum en_sysctrl_pll_infreq 215 { 216 SysctrlPllInFreq4_6MHz = 0u, ///< 4~16MHz 217 SysctrlPllInFreq6_12MHz = 1u, ///< 6~12MHz 218 SysctrlPllInFreq12_20MHz = 2u, ///< 12~20MHz 219 SysctrlPllInFreq20_24MHz = 3u, ///< 20~24MHz 220 }en_sysctrl_pll_infreq_t; 221 222 /** 223 ******************************************************************************* 224 ** \brief PLL输出频率范围类型定义 225 ******************************************************************************/ 226 typedef enum en_sysctrl_pll_outfreq 227 { 228 SysctrlPllOutFreq8_12MHz = 0u, ///< 8~12MHz 229 SysctrlPllOutFreq12_18MHz = 1u, ///< 12~18MHz 230 SysctrlPllOutFreq18_24MHz = 2u, ///< 18~24MHz 231 SysctrlPllOutFreq24_36MHz = 3u, ///< 24~36MHz 232 SysctrlPllOutFreq36_48MHz = 4u, ///< 36~48MHz 233 }en_sysctrl_pll_outfreq_t; 234 235 /** 236 ******************************************************************************* 237 ** \brief PLL输入时钟源类型定义 238 ******************************************************************************/ 239 typedef enum en_sysctrl_pll_clksource 240 { 241 SysctrlPllXthXtal = 0u, ///< XTH晶振输入的时钟 242 SysctrlPllXthPd00In = 2u, ///< XTH从端口PD00输入的时钟 243 SysctrlPllRch = 3u, ///< RCH时钟 244 }en_sysctrl_pll_clksource_t; 245 246 /** 247 ******************************************************************************* 248 ** \brief PLL输入时钟源类型定义 249 ******************************************************************************/ 250 typedef enum en_sysctrl_pll_mul 251 { 252 SysctrlPllMul1 = 1u, ///< 1倍频 253 SysctrlPllMul2 = 2u, ///< 2倍频 254 SysctrlPllMul3 = 3u, ///< 3倍频 255 SysctrlPllMul4 = 4u, ///< 4倍频 256 SysctrlPllMul5 = 5u, ///< 5倍频 257 SysctrlPllMul6 = 6u, ///< 6倍频 258 SysctrlPllMul7 = 7u, ///< 7倍频 259 SysctrlPllMul8 = 8u, ///< 8倍频 260 SysctrlPllMul9 = 9u, ///< 9倍频 261 SysctrlPllMul10 = 10u, ///< 10倍频 262 SysctrlPllMul11 = 11u, ///< 11倍频 263 SysctrlPllMul12 = 12u, ///< 12倍频 264 }en_sysctrl_pll_mul_t; 265 266 /** 267 ******************************************************************************* 268 ** \brief HCLK时钟分频系数类型定义 269 ******************************************************************************/ 270 typedef enum en_sysctrl_hclk_div 271 { 272 SysctrlHclkDiv1 = 0u, ///< SystemClk 273 SysctrlHclkDiv2 = 1u, ///< SystemClk/2 274 SysctrlHclkDiv4 = 2u, ///< SystemClk/4 275 SysctrlHclkDiv8 = 3u, ///< SystemClk/8 276 SysctrlHclkDiv16 = 4u, ///< SystemClk/16 277 SysctrlHclkDiv32 = 5u, ///< SystemClk/32 278 SysctrlHclkDiv64 = 6u, ///< SystemClk/64 279 SysctrlHclkDiv128 = 7u, ///< SystemClk/128 280 }en_sysctrl_hclk_div_t; 281 282 /** 283 ******************************************************************************* 284 ** \brief PCLK分频系数 285 ******************************************************************************/ 286 typedef enum en_sysctrl_pclk_div 287 { 288 SysctrlPclkDiv1 = 0u, ///< HCLK 289 SysctrlPclkDiv2 = 1u, ///< HCLK/2 290 SysctrlPclkDiv4 = 2u, ///< HCLK/4 291 SysctrlPclkDiv8 = 3u, ///< HCLK/8 292 }en_sysctrl_pclk_div_t; 293 294 /** 295 ******************************************************************************* 296 ** \brief RTC高速时钟补偿时钟频率数据类型定义 297 ******************************************************************************/ 298 typedef enum en_sysctrl_rtc_adjust 299 { 300 SysctrlRTC4MHz = 0u, ///< 4MHz 301 SysctrlRTC6MHz = 1u, ///< 6MHz 302 SysctrlRTC8MHz = 2u, ///< 8MHz 303 SysctrlRTC12MHz = 3u, ///< 12MHz 304 SysctrlRTC16MHz = 4u, ///< 16MHz 305 SysctrlRTC20MHz = 5u, ///< 20MHz 306 SysctrlRTC24MHz = 6u, ///< 24MHz 307 SysctrlRTC32MHz = 7u, ///< 32MHz 308 }en_sysctrl_rtc_adjust_t; 309 310 /** 311 ******************************************************************************* 312 ** \brief 系统控制模块其他功能数据类型定义 313 ******************************************************************************/ 314 typedef enum en_sysctrl_func 315 { 316 SysctrlWkupByRCHEn =0u, ///< 唤醒时使用RCH时钟 317 SysctrlEXTHEn =1u, ///< 使能外部高速时钟从输入引脚PD00输入 318 SysctrlEXTLEn =2u, ///< 使能外部低速速时钟从输入引脚PC14输入 319 SysctrlXTLAlwaysOnEn =3u, ///< 使能后XTL_EN只可置位 320 SysctrlClkFuncRTCLpmEn =4u, ///< 使能RTC低功耗模式 321 SysctrlCMLockUpEn =5u, ///< 使能后CPU执行无效指令会复位MCU 322 SysctrlSWDUseIOEn =6u, ///< SWD端口设为IO功能 323 }en_sysctrl_func_t; 324 325 /** 326 ******************************************************************************* 327 ** \brief 外设时钟门控开关类型枚举 328 ******************************************************************************/ 329 typedef enum en_sysctrl_peripheral_gate 330 { 331 SysctrlPeripheralUart0 = 0u, ///< 串口0 332 SysctrlPeripheralUart1 = 1u, ///< 串口1 333 SysctrlPeripheralLpUart0 = 2u, ///< 低功耗串口0 334 SysctrlPeripheralLpUart1 = 3u, ///< 低功耗串口1 335 SysctrlPeripheralI2c0 = 4u, ///< I2C0 336 SysctrlPeripheralI2c1 = 5u, ///< I2C1 337 SysctrlPeripheralSpi0 = 6u, ///< SPI0 338 SysctrlPeripheralSpi1 = 7u, ///< SPI1 339 SysctrlPeripheralBTim = 8u, ///< 基础定时器 340 SysctrlPeripheralLpTim = 9u, ///< 低功耗定时器 341 SysctrlPeripheralAdvTim = 10u, ///< 高级定时器 342 SysctrlPeripheralTim3 = 11u, ///< 定时器3 343 SysctrlPeripheralOpa = 13u, ///< OPA 344 SysctrlPeripheralPca = 14u, ///< 可编程计数阵列 345 SysctrlPeripheralWdt = 15u, ///< 看门狗 346 SysctrlPeripheralAdcBgr = 16u, ///< ADC&BGR 347 SysctrlPeripheralVcLvd = 17u, ///< 电压比较和低电压检测 348 SysctrlPeripheralRng = 18u, ///< RNG 349 SysctrlPeripheralPcnt = 19u, ///< PCNT 350 SysctrlPeripheralRtc = 20u, ///< RTC 351 SysctrlPeripheralTrim = 21u, ///< 时钟校准 352 SysctrlPeripheralLcd = 22u, ///< LCD 353 SysctrlPeripheralTick = 24u, ///< 系统定时器 354 SysctrlPeripheralSwd = 25u, ///< SWD 355 SysctrlPeripheralCrc = 26u, ///< CRC 356 SysctrlPeripheralAes = 27u, ///< AES 357 SysctrlPeripheralGpio = 28u, ///< GPIO 358 SysctrlPeripheralDma = 29u, ///< DMA 359 SysctrlPeripheralDiv = 30u, ///< 除法器 360 SysctrlPeripheralFlash = 31u, ///< Flash 361 }en_sysctrl_peripheral_gate_t; 362 363 /** 364 ******************************************************************************* 365 ** \brief 时钟初始化配置结构体定义 366 ******************************************************************************/ 367 typedef struct 368 { 369 en_sysctrl_clk_source_t enClkSrc; ///< 时钟源选择 370 en_sysctrl_hclk_div_t enHClkDiv; ///< HCLK分频系数 371 en_sysctrl_pclk_div_t enPClkDiv; ///< PCLK分频系数 372 }stc_sysctrl_clk_config_t; 373 374 /** 375 ******************************************************************************* 376 ** \brief 时钟初始化配置结构体定义 377 ******************************************************************************/ 378 typedef struct 379 { 380 en_sysctrl_pll_infreq_t enInFreq; ///< PLL输入时钟频率范围选择 381 en_sysctrl_pll_outfreq_t enOutFreq; ///< PLL输出时钟频率范围选择 382 en_sysctrl_pll_clksource_t enPllClkSrc; ///< PLL输入时钟源选择 383 en_sysctrl_pll_mul_t enPllMul; ///< PLL倍频系数选择 384 }stc_sysctrl_pll_config_t; 385 386 /****************************************************************************** 387 * Global variable declarations ('extern', definition in C source) 388 ******************************************************************************/ 389 390 /****************************************************************************** 391 * Global function prototypes (definition in C source) 392 ******************************************************************************/ 393 ///< 系统时钟初始化API:用于上电后，系统工作之前对主频及外设时钟进行初始化； 394 ///< 注意1：使用该初始化函数前需要根据系统，必须优先设置目标内部时钟源的TRIM值或外部时钟源的频率范围， 395 ///< 注意2：XTH、XTL的频率范围设定，需要根据外部晶振决定， 396 ///< 注意3：本驱动默认宏定义：SYSTEM_XTH=32MHz,SYSTEM_XTL=32768Hz,如使用其它外部晶振，必须修改这两个宏定义的值。 397 en_result_t Sysctrl_ClkInit(stc_sysctrl_clk_config_t *pstcCfg); 398 399 ///< 系统时钟去初始化API:恢复为上电默认状态->PCLK=HCLK=SystemClk=RCH4MHz 400 en_result_t Sysctrl_ClkDeInit(void); 401 402 ///< 系统时钟模块的基本功能设置 403 ///< 注意：使能需要使用的时钟源之前，必须优先设置目标内部时钟源的TRIM值或外部时钟源的频率范围 404 en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag); 405 406 ///<外部晶振驱动配置：系统初始化Sysctrl_ClkInit()之后，可根据需要配置外部晶振的驱动能力，时钟初始化Sysctrl_ClkInit()默认为最大值; 407 en_result_t Sysctrl_XTHDriverConfig(en_sysctrl_xtal_driver_t enDriver); 408 en_result_t Sysctrl_XTLDriverConfig(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver); 409 410 ///<时钟稳定周期设置:系统初始化Sysctrl_ClkInit()之后，可根据需要配置时钟开启后的稳定之间，默认为最大值; 411 en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle); 412 en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle); 413 en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle); 414 en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle); 415 416 ///<系统时钟源切换并更新系统时钟：如果需要在系统时钟初始化Sysctrl_ClkInit()之后切换主频时钟源，则使用该函数； 417 ///< 时钟切换前后，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2， 418 ///< 注意!!!：当HCLK大于24MHz时，FLASH等待周期插入必须至少为1,否则程序运行可能产生未知错误 419 en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource); 420 421 ///< 时钟源频率设定：根据系统情况，单独设置不同时钟源的频率值; 422 ///< 时钟频率设置前，必须根据目标频率值设置Flash读等待周期，可配置插入周期为0、1、2， 423 ///< 其中XTL的时钟由外部晶振决定，无需设置。 424 en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq); 425 en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq); 426 en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq); 427 en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_config_t *pstcPLLCfg); 428 429 ///< 时钟分频设置:根据系统情况，单独设置HCLK、PCLK的分配值; 430 en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv); 431 en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv); 432 433 ///< 时钟频率获取：根据系统需要，获取当前HCLK及PCLK的频率值 434 uint32_t Sysctrl_GetHClkFreq(void); 435 uint32_t Sysctrl_GetPClkFreq(void); 436 437 ///< 外设门控开关/状态获取：用于控制外设模块的使能，使用该模块的功能之前，必须使能该模块的门控时钟； 438 en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag); 439 boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral); 440 441 ///< 系统功能配置：用于设置其他系统相关特殊功能； 442 en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag); 443 444 ///< RTC高速时钟补偿:用于设置RTC高速时钟下的频率补偿 445 en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj); 446 447 //@} // Sysctrl Group 448 449 #ifdef __cplusplus 450 #endif 451 452 #endif /* __SYSCTRL_H__ */ 453 /******************************************************************************* 454 * EOF (not truncated) 455 ******************************************************************************/ 456 457 458