1 /*
2 * Copyright (C) 2021, Huada Semiconductor Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2021-08-19 pjq first version
9 */
10
11 #include <rtthread.h>
12 #include "rthw.h"
13
14 #ifdef RT_USING_PIN
15 #include "gpio.h"
16 #include "drv_gpio.h"
17 #include "interrupts_hc32l136.h"
18
19 #define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F))
20 #define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) * 0x40u))
21 #define GPIO_PIN(pin) ((uint16_t)(GPIO_PIN_INDEX(pin)))
22
23 #define PIN_NUM(port, pin) (((((port) / 0x40u) << 4) | ((pin) & 0x0F)))
24 #define PIN_MAX_NUM ((GpioPortD / 0x40u * 16) + (GpioPin15 + 1))
25
26 struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
27 {
28 {-1, 0, RT_NULL, RT_NULL},
29 {-1, 0, RT_NULL, RT_NULL},
30 {-1, 0, RT_NULL, RT_NULL},
31 {-1, 0, RT_NULL, RT_NULL},
32 {-1, 0, RT_NULL, RT_NULL},
33 {-1, 0, RT_NULL, RT_NULL},
34 {-1, 0, RT_NULL, RT_NULL},
35 {-1, 0, RT_NULL, RT_NULL},
36 {-1, 0, RT_NULL, RT_NULL},
37 {-1, 0, RT_NULL, RT_NULL},
38 {-1, 0, RT_NULL, RT_NULL},
39 {-1, 0, RT_NULL, RT_NULL},
40 {-1, 0, RT_NULL, RT_NULL},
41 {-1, 0, RT_NULL, RT_NULL},
42 {-1, 0, RT_NULL, RT_NULL},
43 {-1, 0, RT_NULL, RT_NULL},
44
45 {-1, 0, RT_NULL, RT_NULL},
46 {-1, 0, RT_NULL, RT_NULL},
47 {-1, 0, RT_NULL, RT_NULL},
48 {-1, 0, RT_NULL, RT_NULL},
49 {-1, 0, RT_NULL, RT_NULL},
50 {-1, 0, RT_NULL, RT_NULL},
51 {-1, 0, RT_NULL, RT_NULL},
52 {-1, 0, RT_NULL, RT_NULL},
53 {-1, 0, RT_NULL, RT_NULL},
54 {-1, 0, RT_NULL, RT_NULL},
55 {-1, 0, RT_NULL, RT_NULL},
56 {-1, 0, RT_NULL, RT_NULL},
57 {-1, 0, RT_NULL, RT_NULL},
58 {-1, 0, RT_NULL, RT_NULL},
59 {-1, 0, RT_NULL, RT_NULL},
60 {-1, 0, RT_NULL, RT_NULL},
61
62 {-1, 0, RT_NULL, RT_NULL},
63 {-1, 0, RT_NULL, RT_NULL},
64 {-1, 0, RT_NULL, RT_NULL},
65 {-1, 0, RT_NULL, RT_NULL},
66 {-1, 0, RT_NULL, RT_NULL},
67 {-1, 0, RT_NULL, RT_NULL},
68 {-1, 0, RT_NULL, RT_NULL},
69 {-1, 0, RT_NULL, RT_NULL},
70 {-1, 0, RT_NULL, RT_NULL},
71 {-1, 0, RT_NULL, RT_NULL},
72 {-1, 0, RT_NULL, RT_NULL},
73 {-1, 0, RT_NULL, RT_NULL},
74 {-1, 0, RT_NULL, RT_NULL},
75 {-1, 0, RT_NULL, RT_NULL},
76 {-1, 0, RT_NULL, RT_NULL},
77 {-1, 0, RT_NULL, RT_NULL},
78
79 {-1, 0, RT_NULL, RT_NULL},
80 {-1, 0, RT_NULL, RT_NULL},
81 {-1, 0, RT_NULL, RT_NULL},
82 {-1, 0, RT_NULL, RT_NULL},
83 {-1, 0, RT_NULL, RT_NULL},
84 {-1, 0, RT_NULL, RT_NULL},
85 {-1, 0, RT_NULL, RT_NULL},
86 {-1, 0, RT_NULL, RT_NULL},
87 {-1, 0, RT_NULL, RT_NULL},
88 {-1, 0, RT_NULL, RT_NULL},
89 {-1, 0, RT_NULL, RT_NULL},
90 {-1, 0, RT_NULL, RT_NULL},
91 {-1, 0, RT_NULL, RT_NULL},
92 {-1, 0, RT_NULL, RT_NULL},
93 {-1, 0, RT_NULL, RT_NULL},
94 {-1, 0, RT_NULL, RT_NULL},
95
96 };
97
pin_irq_handler(en_gpio_port_t port,en_gpio_pin_t pin)98 static void pin_irq_handler(en_gpio_port_t port, en_gpio_pin_t pin)
99 {
100 rt_int32_t irqindex = -1;
101
102 irqindex = PIN_NUM(port, pin);
103 if (pin_irq_hdr_tab[irqindex].hdr)
104 {
105 pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
106 }
107 }
108
Gpio_IRQHandler(uint8_t u8Param)109 void Gpio_IRQHandler(uint8_t u8Param)
110 {
111 en_gpio_pin_t i;
112 en_gpio_port_t enPort;
113
114 enPort = (en_gpio_port_t)(GpioPortA + (GpioPortB - GpioPortA) * u8Param);
115 rt_interrupt_enter();
116 for (i=GpioPin0; i<=GpioPin15; i++)
117 {
118 if(TRUE == Gpio_GetIrqStatus(enPort, i))
119 {
120 Gpio_ClearIrq(enPort, i);
121 pin_irq_handler(enPort, i);
122 }
123
124 }
125 rt_interrupt_leave();
126 }
127
_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)128 static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
129 {
130 uint8_t gpio_port;
131 uint16_t gpio_pin;
132
133 if (pin < PIN_MAX_NUM)
134 {
135 gpio_port = GPIO_PORT(pin);
136 gpio_pin = GPIO_PIN(pin);
137 if (PIN_LOW == value)
138 {
139 Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, FALSE);
140 }
141 else
142 {
143 Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, TRUE);
144 }
145 }
146 }
147
_pin_read(rt_device_t dev,rt_base_t pin)148 static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin)
149 {
150 uint8_t gpio_port;
151 uint16_t gpio_pin;
152 rt_ssize_t value = PIN_LOW;
153
154 if (pin < PIN_MAX_NUM)
155 {
156 gpio_port = GPIO_PORT(pin);
157 gpio_pin = GPIO_PIN(pin);
158 if (FALSE == Gpio_GetInputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin))
159 {
160 value = PIN_LOW;
161 }
162 else
163 {
164 value = PIN_HIGH;
165 }
166 }
167 else
168 {
169 value = -RT_EINVAL;
170 }
171
172 return value;
173 }
174
_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)175 static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
176 {
177 uint8_t gpio_port;
178 uint16_t gpio_pin;
179 stc_gpio_config_t pstcGpioCfg;
180
181 memset(&pstcGpioCfg, 0, sizeof(pstcGpioCfg));
182 if (pin >= PIN_MAX_NUM)
183 {
184 return;
185 }
186
187 switch (mode)
188 {
189 case PIN_MODE_OUTPUT:
190 pstcGpioCfg.enDir = GpioDirOut;
191 pstcGpioCfg.enDrv = GpioDrvL;
192 pstcGpioCfg.enCtrlMode = GpioAHB;
193 break;
194 case PIN_MODE_INPUT:
195 pstcGpioCfg.enDir = GpioDirIn;
196 pstcGpioCfg.enDrv = GpioDrvL;
197 pstcGpioCfg.enPuPd = GpioPu;
198 pstcGpioCfg.enOD = GpioOdDisable;
199 pstcGpioCfg.enCtrlMode = GpioAHB;
200 break;
201 case PIN_MODE_INPUT_PULLUP:
202 pstcGpioCfg.enDir = GpioDirIn;
203 pstcGpioCfg.enDrv = GpioDrvL;
204 pstcGpioCfg.enPuPd = GpioPu;
205 pstcGpioCfg.enOD = GpioOdDisable;
206 pstcGpioCfg.enCtrlMode = GpioAHB;
207 break;
208 case PIN_MODE_INPUT_PULLDOWN:
209 pstcGpioCfg.enDir = GpioDirIn;
210 pstcGpioCfg.enDrv = GpioDrvL;
211 pstcGpioCfg.enPuPd = GpioPd;
212 pstcGpioCfg.enOD = GpioOdDisable;
213 pstcGpioCfg.enCtrlMode = GpioAHB;
214 break;
215 case PIN_MODE_OUTPUT_OD:
216 pstcGpioCfg.enDir = GpioDirOut;
217 pstcGpioCfg.enDrv = GpioDrvL;
218 pstcGpioCfg.enOD = GpioOdEnable;
219 pstcGpioCfg.enCtrlMode = GpioAHB;
220 break;
221 default:
222 break;
223 }
224 gpio_port = GPIO_PORT(pin);
225 gpio_pin = GPIO_PIN(pin);
226 Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg);
227 }
228
_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)229 static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin,
230 rt_uint8_t mode, void (*hdr)(void *args), void *args)
231 {
232 rt_base_t level;
233 rt_int32_t irqindex = -1;
234
235 if (pin >= PIN_MAX_NUM)
236 {
237 return -RT_ENOSYS;
238 }
239
240 irqindex = pin;
241 level = rt_hw_interrupt_disable();
242 if (pin_irq_hdr_tab[irqindex].pin == pin &&
243 pin_irq_hdr_tab[irqindex].hdr == hdr &&
244 pin_irq_hdr_tab[irqindex].mode == mode &&
245 pin_irq_hdr_tab[irqindex].args == args)
246 {
247 rt_hw_interrupt_enable(level);
248 return RT_EOK;
249 }
250 if (pin_irq_hdr_tab[irqindex].pin != -1)
251 {
252 rt_hw_interrupt_enable(level);
253 return -RT_EBUSY;
254 }
255 pin_irq_hdr_tab[irqindex].pin = pin;
256 pin_irq_hdr_tab[irqindex].hdr = hdr;
257 pin_irq_hdr_tab[irqindex].mode = mode;
258 pin_irq_hdr_tab[irqindex].args = args;
259 rt_hw_interrupt_enable(level);
260
261 return RT_EOK;
262 }
263
_pin_detach_irq(struct rt_device * device,rt_base_t pin)264 static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
265 {
266 rt_base_t level;
267 rt_int32_t irqindex = -1;
268
269 if (pin >= PIN_MAX_NUM)
270 {
271 return -RT_ENOSYS;
272 }
273
274 irqindex = pin;
275 level = rt_hw_interrupt_disable();
276 if (pin_irq_hdr_tab[irqindex].pin == -1)
277 {
278 rt_hw_interrupt_enable(level);
279 return RT_EOK;
280 }
281 pin_irq_hdr_tab[irqindex].pin = -1;
282 pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
283 pin_irq_hdr_tab[irqindex].mode = 0;
284 pin_irq_hdr_tab[irqindex].args = RT_NULL;
285 rt_hw_interrupt_enable(level);
286
287 return RT_EOK;
288 }
289
_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)290 static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
291 {
292 rt_base_t level;
293 en_gpio_port_t gpio_port;
294 en_gpio_pin_t gpio_pin;
295 rt_int32_t irqindex;
296 stc_gpio_config_t pstcGpioCfg;
297
298 if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled)))
299 {
300 return -RT_ENOSYS;
301 }
302
303 irqindex = pin;
304 gpio_port = (en_gpio_port_t)GPIO_PORT(pin);
305 gpio_pin = (en_gpio_pin_t)GPIO_PIN(pin);
306 if (enabled == PIN_IRQ_ENABLE)
307 {
308 level = rt_hw_interrupt_disable();
309 if (pin_irq_hdr_tab[irqindex].pin == -1)
310 {
311 rt_hw_interrupt_enable(level);
312 return -RT_ENOSYS;
313 }
314
315 /* Exint config */
316 pstcGpioCfg.enDir = GpioDirIn;
317 pstcGpioCfg.enDrv = GpioDrvL;
318 pstcGpioCfg.enPuPd = GpioPu;
319 pstcGpioCfg.enOD = GpioOdDisable;
320 pstcGpioCfg.enCtrlMode = GpioAHB;
321 Gpio_Init(gpio_port, gpio_pin, &pstcGpioCfg);
322 Gpio_ClearIrq(gpio_port, gpio_pin);
323
324 switch (pin_irq_hdr_tab[irqindex].mode)
325 {
326 case PIN_IRQ_MODE_RISING:
327 Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqRising);
328 break;
329 case PIN_IRQ_MODE_FALLING:
330 Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqFalling);
331 break;
332 case PIN_IRQ_MODE_HIGH_LEVEL:
333 Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqHigh);
334 break;
335 case PIN_IRQ_MODE_LOW_LEVEL:
336 Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqLow);
337 break;
338 }
339 EnableNvic((IRQn_Type)(pin / 16), IrqLevel3, TRUE);
340
341 rt_hw_interrupt_enable(level);
342 }
343 else
344 {
345 level = rt_hw_interrupt_disable();
346 switch (pin_irq_hdr_tab[irqindex].mode)
347 {
348 case PIN_IRQ_MODE_RISING:
349 Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqRising);
350 break;
351 case PIN_IRQ_MODE_FALLING:
352 Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling);
353 break;
354 case PIN_IRQ_MODE_RISING_FALLING:
355
356 break;
357 case PIN_IRQ_MODE_LOW_LEVEL:
358 Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqLow);
359 break;
360 }
361 rt_hw_interrupt_enable(level);
362 }
363
364 return RT_EOK;
365 }
366
367 static const struct rt_pin_ops _pin_ops =
368 {
369 _pin_mode,
370 _pin_write,
371 _pin_read,
372 _pin_attach_irq,
373 _pin_detach_irq,
374 _pin_irq_enable,
375 };
376
rt_hw_pin_init(void)377 int rt_hw_pin_init(void)
378 {
379 Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE);
380
381 return rt_device_pin_register("pin", &_pin_ops, RT_NULL);
382 }
383 INIT_BOARD_EXPORT(rt_hw_pin_init);
384
385 #endif /* RT_USING_PIN */
386