1 /**
2 ******************************************************************************
3 * @file hk32f0xx_rcc.c
4 * @version V1.0.1
5 * @date 2019-08-15
6 ===============================================================================
7 ##### RCC specific features #####
8 ===============================================================================
9 [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
10 all peripherals are off except internal SRAM, Flash and SWD.
11 (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
12 all peripherals mapped on these busses are running at HSI speed.
13 (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
14 (#) All GPIOs are in input floating state, except the SWD pins which
15 are assigned to be used for debug purpose.
16 [..] Once the device started from reset, the user application has to:
17 (#) Configure the clock source to be used to drive the System clock
18 (if the application needs higher frequency/performance)
19 (#) Configure the System clock frequency and Flash settings
20 (#) Configure the AHB and APB busses prescalers
21 (#) Enable the clock for the peripheral(s) to be used
22 (#) Configure the clock source(s) for peripherals which clocks are not
23 derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)
24
25 @endverbatim
26
27 ******************************************************************************
28 */
29
30 /* Includes ------------------------------------------------------------------*/
31 #include "hk32f0xx_rcc.h"
32
33 /** @addtogroup HK32F0xx_StdPeriph_Driver
34 * @{
35 */
36
37 /** @defgroup RCC
38 * @brief RCC driver modules
39 * @{
40 */
41
42 /* Private typedef -----------------------------------------------------------*/
43 /* Private define ------------------------------------------------------------*/
44
45 /* ---------------------- RCC registers mask -------------------------------- */
46 /* RCC Flag Mask */
47 #define FLAG_MASK ((uint8_t)0x1F)
48
49 /* CR register byte 2 (Bits[23:16]) base address */
50 #define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
51
52 /* CFGR register byte 3 (Bits[31:23]) base address */
53 #define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
54
55 /* CIR register byte 1 (Bits[15:8]) base address */
56 #define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009)
57
58 /* CIR register byte 2 (Bits[23:16]) base address */
59 #define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A)
60
61 /* Private macro -------------------------------------------------------------*/
62 /* Private variables ---------------------------------------------------------*/
63 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
64
65 /* Private function prototypes -----------------------------------------------*/
66 /* Private functions ---------------------------------------------------------*/
67
68 /** @defgroup RCC_Private_Functions
69 * @{
70 */
71
72 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
73 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
74 *
75 @verbatim
76 ===============================================================================
77 ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
78 ===============================================================================
79 [..] This section provides functions allowing to configure the internal/external clocks,
80 PLL, CSS and MCO.
81 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
82 or through the PLL as System clock source.
83 The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
84 (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock
85 the ADC peripheral.
86 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
87 clock source.
88 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
89 through the PLL as System clock source. Can be used also as RTC clock source.
90 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
91 LSE can be used also to clock the USART and CEC peripherals.
92 (#) PLL (clocked by HSI or HSE), for System clock.
93 (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
94 (HSE used directly or through PLL as System clock source), the System clock
95 is automatically switched to HSI and an interrupt is generated if enabled.
96 The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt)
97 exception vector.
98 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI,
99 HSE, LSE or PLL (divided by 2) clock on PA8 pin.
100
101 @endverbatim
102 * @{
103 */
104
105 /**
106 * @brief Resets the RCC clock configuration to the default reset state.
107 * @note The default reset state of the clock configuration is given below:
108 * @note HSI ON and used as system clock source
109 * @note HSI14, HSE and PLL OFF
110 * @note AHB, APB prescaler set to 1.
111 * @note CSS and MCO OFF
112 * @note All interrupts disabled
113 * @note However, this function doesn't modify the configuration of the
114 * @note Peripheral clocks
115 * @note LSI, LSE and RTC clocks
116 * @param None
117 * @retval None
118 */
RCC_DeInit(void)119 void RCC_DeInit(void)
120 {
121 /* Set HSION bit */
122 RCC->CR |= (uint32_t)0x00000001;
123
124 #if defined (HK32F051)
125 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
126 RCC->CFGR &= (uint32_t)0xF8FFB80C;
127 #else
128 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
129 RCC->CFGR &= (uint32_t)0x08FFB80C;
130 #endif /* HK32F051 */
131
132 /* Reset HSEON, CSSON and PLLON bits */
133 RCC->CR &= (uint32_t)0xFEF6FFFF;
134
135 /* Reset HSEBYP bit */
136 RCC->CR &= (uint32_t)0xFFFBFFFF;
137
138 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
139 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
140
141 /* Reset PREDIV1[3:0] bits */
142 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
143
144 /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
145 RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
146
147 /* Reset HSI14 bit */
148 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
149
150 /* Disable all interrupts */
151 RCC->CIR = 0x00000000;
152 }
153
154 /**
155 * @brief Configures the External High Speed oscillator (HSE).
156 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
157 * software should wait on HSERDY flag to be set indicating that HSE clock
158 * is stable and can be used to clock the PLL and/or system clock.
159 * @note HSE state can not be changed if it is used directly or through the
160 * PLL as system clock. In this case, you have to select another source
161 * of the system clock then change the HSE state (ex. disable it).
162 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
163 * @note This function resets the CSSON bit, so if the Clock security system(CSS)
164 * was previously enabled you have to enable it again after calling this
165 * function.
166 * @param RCC_HSE: specifies the new state of the HSE.
167 * This parameter can be one of the following values:
168 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
169 * 6 HSE oscillator clock cycles.
170 * @arg RCC_HSE_ON: turn ON the HSE oscillator
171 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
172 * @retval None
173 */
RCC_HSEConfig(uint8_t RCC_HSE)174 void RCC_HSEConfig(uint8_t RCC_HSE)
175 {
176 /* Check the parameters */
177 assert_param(IS_RCC_HSE(RCC_HSE));
178
179 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
180 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
181
182 /* Set the new HSE configuration -------------------------------------------*/
183 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
184
185 }
186
187 /**
188 * @brief Waits for HSE start-up.
189 * @note This function waits on HSERDY flag to be set and return SUCCESS if
190 * this flag is set, otherwise returns ERROR if the timeout is reached
191 * and this flag is not set. The timeout value is defined by the constant
192 * HSE_STARTUP_TIMEOUT in hk32f0xx.h file. You can tailor it depending
193 * on the HSE crystal used in your application.
194 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
195 * @param None
196 * @retval An ErrorStatus enumeration value:
197 * - SUCCESS: HSE oscillator is stable and ready to use
198 * - ERROR: HSE oscillator not yet ready
199 */
RCC_WaitForHSEStartUp(void)200 ErrorStatus RCC_WaitForHSEStartUp(void)
201 {
202 __IO uint32_t StartUpCounter = 0;
203 ErrorStatus status = ERROR;
204 FlagStatus HSEStatus = RESET;
205
206 /* Wait till HSE is ready and if timeout is reached exit */
207 do
208 {
209 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
210 StartUpCounter++;
211 }
212 while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
213
214 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
215 {
216 status = SUCCESS;
217 }
218 else
219 {
220 status = ERROR;
221 }
222 return (status);
223 }
224
225 /**
226 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
227 * @note The calibration is used to compensate for the variations in voltage
228 * and temperature that influence the frequency of the internal HSI RC.
229 * Refer to the Application Note AN4067 for more details on how to
230 * calibrate the HSI.
231 * @param HSICalibrationValue: specifies the HSI calibration trimming value.
232 * This parameter must be a number between 0 and 0x1F.
233 * @retval None
234 */
RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)235 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
236 {
237 uint32_t tmpreg = 0;
238
239 /* Check the parameters */
240 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
241
242 tmpreg = RCC->CR;
243
244 /* Clear HSITRIM[4:0] bits */
245 tmpreg &= ~RCC_CR_HSITRIM;
246
247 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
248 tmpreg |= (uint32_t)HSICalibrationValue << 3;
249
250 /* Store the new value */
251 RCC->CR = tmpreg;
252 }
253
254 /**
255 * @brief Enables or disables the Internal High Speed oscillator (HSI).
256 * @note After enabling the HSI, the application software should wait on
257 * HSIRDY flag to be set indicating that HSI clock is stable and can
258 * be used to clock the PLL and/or system clock.
259 * @note HSI can not be stopped if it is used directly or through the PLL
260 * as system clock. In this case, you have to select another source
261 * of the system clock then stop the HSI.
262 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
263 * @param NewState: new state of the HSI.
264 * This parameter can be: ENABLE or DISABLE.
265 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
266 * clock cycles.
267 * @retval None
268 */
RCC_HSICmd(FunctionalState NewState)269 void RCC_HSICmd(FunctionalState NewState)
270 {
271 /* Check the parameters */
272 assert_param(IS_FUNCTIONAL_STATE(NewState));
273
274 if (NewState != DISABLE)
275 {
276 RCC->CR |= RCC_CR_HSION;
277 }
278 else
279 {
280 RCC->CR &= ~RCC_CR_HSION;
281 }
282 }
283
284 /**
285 * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14)
286 * calibration value.
287 * @note The calibration is used to compensate for the variations in voltage
288 * and temperature that influence the frequency of the internal HSI RC.
289 * Refer to the Application Note AN4067 for more details on how to
290 * calibrate the HSI14.
291 * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
292 * This parameter must be a number between 0 and 0x1F.
293 * @retval None
294 */
RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)295 void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
296 {
297 uint32_t tmpreg = 0;
298
299 /* Check the parameters */
300 assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
301
302 tmpreg = RCC->CR2;
303
304 /* Clear HSI14TRIM[4:0] bits */
305 tmpreg &= ~RCC_CR2_HSI14TRIM;
306
307 /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
308 tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
309
310 /* Store the new value */
311 RCC->CR2 = tmpreg;
312 }
313
314 /**
315 * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14).
316 * @note After enabling the HSI14, the application software should wait on
317 * HSIRDY flag to be set indicating that HSI clock is stable and can
318 * be used to clock the ADC.
319 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
320 * @param NewState: new state of the HSI14.
321 * This parameter can be: ENABLE or DISABLE.
322 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
323 * clock cycles.
324 * @retval None
325 */
RCC_HSI14Cmd(FunctionalState NewState)326 void RCC_HSI14Cmd(FunctionalState NewState)
327 {
328 /* Check the parameters */
329 assert_param(IS_FUNCTIONAL_STATE(NewState));
330
331 if (NewState != DISABLE)
332 {
333 RCC->CR2 |= RCC_CR2_HSI14ON;
334 }
335 else
336 {
337 RCC->CR2 &= ~RCC_CR2_HSI14ON;
338 }
339 }
340
341 /**
342 * @brief Enables or disables the Internal High Speed oscillator request from ADC.
343 * @param NewState: new state of the HSI14 ADC request.
344 * This parameter can be: ENABLE or DISABLE.
345 * @retval None
346 */
RCC_HSI14ADCRequestCmd(FunctionalState NewState)347 void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
348 {
349 /* Check the parameters */
350 assert_param(IS_FUNCTIONAL_STATE(NewState));
351
352 if (NewState != DISABLE)
353 {
354 RCC->CR2 &= ~RCC_CR2_HSI14DIS;
355 }
356 else
357 {
358 RCC->CR2 |= RCC_CR2_HSI14DIS;
359 }
360 }
361
362 /**
363 * @brief Configures the External Low Speed oscillator (LSE).
364 * @note As the LSE is in the Backup domain and write access is denied to this
365 * domain after reset, you have to enable write access using
366 * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
367 * (to be done once after reset).
368 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
369 * software should wait on LSERDY flag to be set indicating that LSE clock
370 * is stable and can be used to clock the RTC.
371 * @param RCC_LSE: specifies the new state of the LSE.
372 * This parameter can be one of the following values:
373 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
374 * 6 LSE oscillator clock cycles.
375 * @arg RCC_LSE_ON: turn ON the LSE oscillator
376 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
377 * @retval None
378 */
RCC_LSEConfig(uint32_t RCC_LSE)379 void RCC_LSEConfig(uint32_t RCC_LSE)
380 {
381 /* Check the parameters */
382 assert_param(IS_RCC_LSE(RCC_LSE));
383
384 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
385 /* Reset LSEON bit */
386 RCC->BDCR &= ~(RCC_BDCR_LSEON);
387
388 /* Reset LSEBYP bit */
389 RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
390
391 #if 0 // If you need to configure the drive strength for special reasons,please "#if 1"
392 *(unsigned long int *)0x400028F0 = 0x80000000 // Reserved , default 0
393 | 0x0 << 15 // Reserved , default 1
394 | 0x0 << 11 // Reserved , default 0
395 | 0x6 << 8 // Reserved , default 4
396 | 0x0 << 7 // Reserved , default 1
397 | 0x0 << 6 // NoiseFilterDis , default 1
398 | 0x6 << 0 // Strength , default 4
399 ;
400 #endif
401
402 /* Configure LSE */
403 RCC->BDCR |= RCC_LSE;
404 }
405
406 /**
407 * @brief Configures the External Low Speed oscillator (LSE) drive capability.
408 * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
409 * This parameter can be one of the following values:
410 * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
411 * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
412 * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
413 * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
414 * @retval None
415 */
RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)416 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
417 {
418 /* Check the parameters */
419 assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
420
421 /* Clear LSEDRV[1:0] bits */
422 RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
423
424 /* Set the LSE Drive */
425 RCC->BDCR |= RCC_LSEDrive;
426 }
427
428 /**
429 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
430 * @note After enabling the LSI, the application software should wait on
431 * LSIRDY flag to be set indicating that LSI clock is stable and can
432 * be used to clock the IWDG and/or the RTC.
433 * @note LSI can not be disabled if the IWDG is running.
434 * @param NewState: new state of the LSI.
435 * This parameter can be: ENABLE or DISABLE.
436 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
437 * clock cycles.
438 * @retval None
439 */
RCC_LSICmd(FunctionalState NewState)440 void RCC_LSICmd(FunctionalState NewState)
441 {
442 /* Check the parameters */
443 assert_param(IS_FUNCTIONAL_STATE(NewState));
444
445 if (NewState != DISABLE)
446 {
447 RCC->CSR |= RCC_CSR_LSION;
448 }
449 else
450 {
451 RCC->CSR &= ~RCC_CSR_LSION;
452 }
453 }
454
455 /**
456 * @brief Configures the PLL clock source and multiplication factor.
457 * @note This function must be used only when the PLL is disabled.
458 *
459 * @param RCC_PLLSource: specifies the PLL entry clock source.
460 * This parameter can be one of the following values:
461 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
462 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
463 * @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry
464 * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
465 * PLL source).
466 *
467 * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
468 * This parameter can be RCC_PLLMul_x where x:[2,16]
469 *
470 * @retval None
471 */
RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t RCC_PLLMul)472 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
473 {
474 /* Check the parameters */
475 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
476 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
477
478 /* Clear PLL Source [16] and Multiplier [21:18] bits */
479 RCC->CFGR &= ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC);
480
481 /* Set the PLL Source and Multiplier */
482 RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
483 }
484
485 /**
486 * @brief Enables or disables the PLL.
487 * @note After enabling the PLL, the application software should wait on
488 * PLLRDY flag to be set indicating that PLL clock is stable and can
489 * be used as system clock source.
490 * @note The PLL can not be disabled if it is used as system clock source
491 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
492 * @param NewState: new state of the PLL.
493 * This parameter can be: ENABLE or DISABLE.
494 * @retval None
495 */
RCC_PLLCmd(FunctionalState NewState)496 void RCC_PLLCmd(FunctionalState NewState)
497 {
498 /* Check the parameters */
499 assert_param(IS_FUNCTIONAL_STATE(NewState));
500
501 if (NewState != DISABLE)
502 {
503 RCC->CR |= RCC_CR_PLLON;
504 }
505 else
506 {
507 RCC->CR &= ~RCC_CR_PLLON;
508 }
509 }
510
511
512 /**
513 * @brief Configures the PREDIV1 division factor.
514 * @note This function must be used only when the PLL is disabled.
515 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
516 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
517 * @retval None
518 */
RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)519 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
520 {
521 uint32_t tmpreg = 0;
522
523 /* Check the parameters */
524 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
525
526 tmpreg = RCC->CFGR2;
527 /* Clear PREDIV1[3:0] bits */
528 tmpreg &= ~(RCC_CFGR2_PREDIV);
529 /* Set the PREDIV1 division factor */
530 tmpreg |= RCC_PREDIV1_Div;
531 /* Store the new value */
532 RCC->CFGR2 = tmpreg;
533 }
534
535 /**
536 * @brief Enables or disables the Clock Security System.
537 * @note If a failure is detected on the HSE oscillator clock, this oscillator
538 * is automatically disabled and an interrupt is generated to inform the
539 * software about the failure (Clock Security System Interrupt, CSSI),
540 * allowing the MCU to perform rescue operations. The CSSI is linked to
541 * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
542 * @param NewState: new state of the Clock Security System.
543 * This parameter can be: ENABLE or DISABLE.
544 * @retval None
545 */
RCC_ClockSecuritySystemCmd(FunctionalState NewState)546 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
547 {
548 /* Check the parameters */
549 assert_param(IS_FUNCTIONAL_STATE(NewState));
550
551 if (NewState != DISABLE)
552 {
553 RCC->CR |= RCC_CR_CSSON;
554 }
555 else
556 {
557 RCC->CR &= ~RCC_CR_CSSON;
558 }
559 }
560
561
562 #ifdef HK32F030x8
563 /**
564 * @brief Selects the clock source to output on MCO pin (PA8).
565 * @note PA8 should be configured in alternate function mode.
566 * @param RCC_MCOSource: specifies the clock source to output.
567 * This parameter can be one of the following values:
568 * @arg RCC_MCOSource_NoClock: No clock selected.
569 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
570 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
571 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
572 * @arg RCC_MCOSource_SYSCLK: System clock selected.
573 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
574 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
575 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
576 * @retval None
577 */
RCC_MCOConfig(uint8_t RCC_MCOSource)578 void RCC_MCOConfig(uint8_t RCC_MCOSource)
579 {
580 /* Check the parameters */
581 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
582
583 /* Select MCO clock source and prescaler */
584 *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource;
585 }
586 #else
587
588 /**
589 * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
590 * prescsaler.
591 * @note PA8 should be configured in alternate function mode.
592 * @param RCC_MCOSource: specifies the clock source to output.
593 * This parameter can be one of the following values:
594 * @arg RCC_MCOSource_NoClock: No clock selected.
595 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
596 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
597 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
598 * @arg RCC_MCOSource_SYSCLK: System clock selected.
599 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
600 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
601 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
602 * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
603 * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
604 * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
605 * This parameter can be one of the following values:
606 * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
607 * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
608 * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
609 * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
610 * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
611 * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
612 * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
613 * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
614 * @retval None
615 */
RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler)616 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
617 {
618 uint32_t tmpreg = 0;
619
620 /* Check the parameters */
621 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
622 assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
623
624 /* Get CFGR value */
625 tmpreg = RCC->CFGR;
626 /* Clear MCOPRE[2:0] bits */
627 tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
628 /* Set the RCC_MCOSource and RCC_MCOPrescaler */
629 tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource << 24));
630 /* Store the new value */
631 RCC->CFGR = tmpreg;
632 }
633
634 #endif
635 /**
636 * @}
637 */
638
639 /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
640 * @brief System, AHB and APB busses clocks configuration functions
641 *
642 @verbatim
643 ===============================================================================
644 ##### System, AHB and APB busses clocks configuration functions #####
645 ===============================================================================
646
647 [..] This section provide functions allowing to configure the System, AHB and
648 APB busses clocks.
649 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
650 HSE and PLL.
651 The AHB clock (HCLK) is derived from System clock through configurable prescaler
652 and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
653 and APB (PCLK) clocks are derived from AHB clock through
654 configurable prescalers and used to clock the peripherals mapped on these busses.
655 You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
656
657 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
658 (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a
659 programmable prescaler: 2 or 4).
660 (+@) The CEC clock which is derived from LSE or HSI divided by 244.
661 (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
662 (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
663 (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
664 divided by a programmable prescaler).
665 The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
666 clock frequency.
667 (+@) IWDG clock which is always the LSI clock.
668
669 (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.
670 Depending on the maximum frequency, the FLASH wait states (WS) should be
671 adapted accordingly:
672 +--------------------------------------------- +
673 | Wait states | HCLK clock frequency (MHz) |
674 |---------------|------------------------------|
675 |0WS(1CPU cycle)| 0 < HCLK <= 24 |
676 |---------------|------------------------------|
677 |1WS(2CPU cycle)| 24 < HCLK <= 48 |
678 +----------------------------------------------+
679
680 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
681 prefetch is disabled.
682
683 [..] It is recommended to use the following software sequences to tune the number
684 of wait states needed to access the Flash memory with the CPU frequency (HCLK).
685 (+) Increasing the CPU frequency
686 (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
687 function
688 (++) Check that Flash Prefetch buffer activation is taken into account by
689 reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
690 (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
691 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
692 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
693 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
694 (++) Check that the new CPU clock source is taken into account by reading
695 the clock source status, using "RCC_GetSYSCLKSource()" function
696 (+) Decreasing the CPU frequency
697 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
698 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
699 (++) Check that the new CPU clock source is taken into account by reading
700 the clock source status, using "RCC_GetSYSCLKSource()" function
701 (++) Program the new number of WS, using "FLASH_SetLatency()" function
702 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
703 (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
704 function
705 (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
706 using the FLASH_GetPrefetchBufferStatus() function.
707
708 @endverbatim
709 * @{
710 */
711
712 /**
713 * @brief Configures the system clock (SYSCLK).
714 * @note The HSI is used (enabled by hardware) as system clock source after
715 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
716 * of failure of the HSE used directly or indirectly as system clock
717 * (if the Clock Security System CSS is enabled).
718 * @note A switch from one clock source to another occurs only if the target
719 * clock source is ready (clock stable after startup delay or PLL locked).
720 * If a clock source which is not yet ready is selected, the switch will
721 * occur when the clock source will be ready.
722 * You can use RCC_GetSYSCLKSource() function to know which clock is
723 * currently used as system clock source.
724 * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
725 * This parameter can be one of the following values:
726 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
727 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
728 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
729 * @retval None
730 */
RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)731 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
732 {
733 uint32_t tmpreg = 0;
734
735 /* Check the parameters */
736 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
737
738 tmpreg = RCC->CFGR;
739
740 /* Clear SW[1:0] bits */
741 tmpreg &= ~RCC_CFGR_SW;
742
743 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
744 tmpreg |= RCC_SYSCLKSource;
745
746 /* Store the new value */
747 RCC->CFGR = tmpreg;
748 }
749
750 /**
751 * @brief Returns the clock source used as system clock.
752 * @param None
753 * @retval The clock source used as system clock. The returned value can be one
754 * of the following values:
755 * - 0x00: HSI used as system clock
756 * - 0x04: HSE used as system clock
757 * - 0x08: PLL used as system clock
758 */
RCC_GetSYSCLKSource(void)759 uint8_t RCC_GetSYSCLKSource(void)
760 {
761 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
762 }
763
764 /**
765 * @brief Configures the AHB clock (HCLK).
766 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
767 * the system clock (SYSCLK).
768 * This parameter can be one of the following values:
769 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
770 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
771 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
772 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
773 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
774 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
775 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
776 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
777 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
778 * @retval None
779 */
RCC_HCLKConfig(uint32_t RCC_SYSCLK)780 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
781 {
782 uint32_t tmpreg = 0;
783
784 /* Check the parameters */
785 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
786
787 tmpreg = RCC->CFGR;
788
789 /* Clear HPRE[3:0] bits */
790 tmpreg &= ~RCC_CFGR_HPRE;
791
792 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
793 tmpreg |= RCC_SYSCLK;
794
795 /* Store the new value */
796 RCC->CFGR = tmpreg;
797 }
798
799 /**
800 * @brief Configures the APB clock (PCLK).
801 * @param RCC_HCLK: defines the APB clock divider. This clock is derived from
802 * the AHB clock (HCLK).
803 * This parameter can be one of the following values:
804 * @arg RCC_HCLK_Div1: APB clock = HCLK
805 * @arg RCC_HCLK_Div2: APB clock = HCLK/2
806 * @arg RCC_HCLK_Div4: APB clock = HCLK/4
807 * @arg RCC_HCLK_Div8: APB clock = HCLK/8
808 * @arg RCC_HCLK_Div16: APB clock = HCLK/16
809 * @retval None
810 */
RCC_PCLKConfig(uint32_t RCC_HCLK)811 void RCC_PCLKConfig(uint32_t RCC_HCLK)
812 {
813 uint32_t tmpreg = 0;
814
815 /* Check the parameters */
816 assert_param(IS_RCC_PCLK(RCC_HCLK));
817
818 tmpreg = RCC->CFGR;
819
820 /* Clear PPRE[2:0] bits */
821 tmpreg &= ~RCC_CFGR_PPRE;
822
823 /* Set PPRE[2:0] bits according to RCC_HCLK value */
824 tmpreg |= RCC_HCLK;
825
826 /* Store the new value */
827 RCC->CFGR = tmpreg;
828 }
829
830 /**
831 * @brief Configures the ADC clock (ADCCLK).
832 * @note This function is obsolete.
833 * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver
834 * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived
835 * from the HSI14 or APB clock (PCLK).
836 * This parameter can be one of the following values:
837 * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
838 * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
839 * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4
840 * @retval None
841 */
RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)842 void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
843 {
844 /* Check the parameters */
845 assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
846
847 /* Clear ADCPRE bit */
848 RCC->CFGR &= ~RCC_CFGR_ADCPRE;
849 /* Set ADCPRE bits according to RCC_PCLK value */
850 RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
851
852 /* Clear ADCSW bit */
853 RCC->CFGR3 &= ~RCC_CFGR3_ADCSW;
854 /* Set ADCSW bits according to RCC_ADCCLK value */
855 RCC->CFGR3 |= RCC_ADCCLK >> 16;
856 }
857
858 /**
859 * @brief Configures the CEC clock (CECCLK).
860 * @param RCC_CECCLK: defines the CEC clock source. This clock is derived
861 * from the HSI or LSE clock.
862 * This parameter can be one of the following values:
863 * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
864 * @arg RCC_CECCLK_LSE: CEC clock = LSE
865 * @retval None
866 */
RCC_CECCLKConfig(uint32_t RCC_CECCLK)867 void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
868 {
869 /* Check the parameters */
870 assert_param(IS_RCC_CECCLK(RCC_CECCLK));
871
872 /* Set CECSW bits according to RCC_CECCLK value */
873 RCC->CFGR3 |= RCC_CECCLK;
874 }
875
876 /**
877 * @brief Configures the I2C1 clock (I2C1CLK).
878 * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived
879 * from the HSI or System clock.
880 * This parameter can be one of the following values:
881 * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
882 * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
883 * @retval None
884 */
RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)885 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
886 {
887 /* Check the parameters */
888 assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
889
890 /* Clear I2CSW bit */
891 RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
892 /* Set I2CSW bits according to RCC_I2CCLK value */
893 RCC->CFGR3 |= RCC_I2CCLK;
894 }
895
896 /**
897 * @brief Configures the USART1 clock (USART1CLK).
898 * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
899 * from the HSI or System clock.
900 * This parameter can be one of the following values:
901 * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
902 * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
903 * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
904 * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
905 * @retval None
906 */
RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)907 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
908 {
909 uint32_t tmp = 0;
910
911 /* Check the parameters */
912 assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
913
914 /* Get USART index */
915 tmp = (RCC_USARTCLK >> 28);
916
917 /* Clear USARTSW[1:0] bit */
918 if (tmp == (uint32_t)0x00000001)
919 {
920 /* Clear USART1SW[1:0] bit */
921 RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
922 }
923 /* Set USARTxSW bits according to RCC_USARTCLK value */
924 RCC->CFGR3 |= RCC_USARTCLK;
925 }
926
927
928 /**
929 * @brief Returns the frequencies of the System, AHB and APB busses clocks.
930 * @note The frequency returned by this function is not the real frequency
931 * in the chip. It is calculated based on the predefined constant and
932 * the source selected by RCC_SYSCLKConfig():
933 *
934 * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
935 *
936 * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
937 *
938 * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
939 * or HSI_VALUE(*) multiplied by the PLL factors.
940 *
941 * @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***)
942 *
943 * @note (*) HSI_VALUE is a constant defined in HK32f0xx.h file (default value
944 * 8 MHz) but the real value may vary depending on the variations
945 * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
946 *
947 * @note (**) HSE_VALUE is a constant defined in HK32f0xx.h file (default value
948 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
949 * frequency of the crystal used. Otherwise, this function may
950 * return wrong result.
951 *
952 * @note (***) HSI48_VALUE is a constant defined in HK32f0xx.h file (default value
953 * 48 MHz) but the real value may vary depending on the variations
954 * in voltage and temperature.
955 *
956 * @note The result of this function could be not correct when using fractional
957 * value for HSE crystal.
958 *
959 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
960 * the clocks frequencies.
961 *
962 * @note This function can be used by the user application to compute the
963 * baudrate for the communication peripherals or configure other parameters.
964 * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function
965 * must be called to update the structure's field. Otherwise, any
966 * configuration based on this function will be incorrect.
967 *
968 * @retval None
969 */
RCC_GetClocksFreq(RCC_ClocksTypeDef * RCC_Clocks)970 void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
971 {
972 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
973
974 /* Get SYSCLK source -------------------------------------------------------*/
975 tmp = RCC->CFGR & RCC_CFGR_SWS;
976
977 switch (tmp)
978 {
979 case 0x00: /* HSI used as system clock */
980 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
981 break;
982 case 0x04: /* HSE used as system clock */
983 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
984 break;
985 case 0x08: /* PLL used as system clock */
986 /* Get PLL clock source and multiplication factor ----------------------*/
987 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
988 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
989 pllmull = (pllmull >> 18) + 2;
990
991 if (pllsource == 0x00)
992 {
993 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
994 pllclk = (HSI_VALUE >> 1) * pllmull;
995 }
996 else
997 {
998 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
999 /* HSE oscillator clock selected as PREDIV1 clock entry */
1000 pllclk = (HSE_VALUE / prediv1factor) * pllmull;
1001 }
1002 RCC_Clocks->SYSCLK_Frequency = pllclk;
1003 break;
1004 case 0x0C: /* HSI48 used as system clock */
1005 RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
1006 break;
1007 default: /* HSI used as system clock */
1008 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
1009 break;
1010 }
1011 /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
1012 /* Get HCLK prescaler */
1013 tmp = RCC->CFGR & RCC_CFGR_HPRE;
1014 tmp = tmp >> 4;
1015 presc = APBAHBPrescTable[tmp];
1016 /* HCLK clock frequency */
1017 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
1018
1019 /* Get PCLK prescaler */
1020 tmp = RCC->CFGR & RCC_CFGR_PPRE;
1021 tmp = tmp >> 8;
1022 presc = APBAHBPrescTable[tmp];
1023 /* PCLK clock frequency */
1024 RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
1025
1026 /* ADCCLK clock frequency */
1027 if ((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
1028 {
1029 /* ADC Clock is HSI14 Osc. */
1030 RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
1031 }
1032 else
1033 {
1034 if ((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
1035 {
1036 /* ADC Clock is derived from PCLK/2 */
1037 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
1038 }
1039 else
1040 {
1041 /* ADC Clock is derived from PCLK/4 */
1042 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
1043 }
1044
1045 }
1046
1047
1048 /* I2C1CLK clock frequency */
1049 if ((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
1050 {
1051 /* I2C1 Clock is HSI Osc. */
1052 RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
1053 }
1054 else
1055 {
1056 /* I2C1 Clock is System Clock */
1057 RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
1058 }
1059
1060 /* USART1CLK clock frequency */
1061 if ((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
1062 {
1063 /* USART1 Clock is PCLK */
1064 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
1065 }
1066 else if ((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
1067 {
1068 /* USART1 Clock is System Clock */
1069 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
1070 }
1071 else if ((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
1072 {
1073 /* USART1 Clock is LSE Osc. */
1074 RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
1075 }
1076 else if ((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
1077 {
1078 /* USART1 Clock is HSI Osc. */
1079 RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
1080 }
1081
1082 }
1083
1084 /**
1085 * @}
1086 */
1087
1088 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
1089 * @brief Peripheral clocks configuration functions
1090 *
1091 @verbatim
1092 ===============================================================================
1093 #####Peripheral clocks configuration functions #####
1094 ===============================================================================
1095
1096 [..] This section provide functions allowing to configure the Peripheral clocks.
1097 (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE
1098 divided by 32).
1099 (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
1100 except internal SRAM, Flash and SWD. Before to start using a peripheral you
1101 have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
1102 RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
1103 (#) To reset the peripherals configuration (to the default state after device reset)
1104 you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
1105 RCC_APB1PeriphResetCmd() functions.
1106
1107 @endverbatim
1108 * @{
1109 */
1110
1111 /**
1112 * @brief Configures the RTC clock (RTCCLK).
1113 * @note As the RTC clock configuration bits are in the Backup domain and write
1114 * access is denied to this domain after reset, you have to enable write
1115 * access using PWR_BackupAccessCmd(ENABLE) function before to configure
1116 * the RTC clock source (to be done once after reset).
1117 * @note Once the RTC clock is configured it can't be changed unless the RTC
1118 * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
1119 *
1120 * @param RCC_RTCCLKSource: specifies the RTC clock source.
1121 * This parameter can be one of the following values:
1122 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
1123 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
1124 * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
1125 *
1126 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
1127 * work in STOP and STANDBY modes, and can be used as wakeup source.
1128 * However, when the HSE clock is used as RTC clock source, the RTC
1129 * cannot be used in STOP and STANDBY modes.
1130 *
1131 * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
1132 * RTC clock source).
1133 *
1134 * @retval None
1135 */
RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)1136 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
1137 {
1138 /* Check the parameters */
1139 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
1140
1141 /* Select the RTC clock source */
1142 RCC->BDCR |= RCC_RTCCLKSource;
1143 }
1144
1145 /**
1146 * @brief Enables or disables the RTC clock.
1147 * @note This function must be used only after the RTC clock source was selected
1148 * using the RCC_RTCCLKConfig function.
1149 * @param NewState: new state of the RTC clock.
1150 * This parameter can be: ENABLE or DISABLE.
1151 * @retval None
1152 */
RCC_RTCCLKCmd(FunctionalState NewState)1153 void RCC_RTCCLKCmd(FunctionalState NewState)
1154 {
1155 /* Check the parameters */
1156 assert_param(IS_FUNCTIONAL_STATE(NewState));
1157
1158 if (NewState != DISABLE)
1159 {
1160 RCC->BDCR |= RCC_BDCR_RTCEN;
1161 }
1162 else
1163 {
1164 RCC->BDCR &= ~RCC_BDCR_RTCEN;
1165 }
1166 }
1167
1168 /**
1169 * @brief Forces or releases the Backup domain reset.
1170 * @note This function resets the RTC peripheral (including the backup registers)
1171 * and the RTC clock source selection in RCC_BDCR register.
1172 * @param NewState: new state of the Backup domain reset.
1173 * This parameter can be: ENABLE or DISABLE.
1174 * @retval None
1175 */
RCC_BackupResetCmd(FunctionalState NewState)1176 void RCC_BackupResetCmd(FunctionalState NewState)
1177 {
1178 /* Check the parameters */
1179 assert_param(IS_FUNCTIONAL_STATE(NewState));
1180
1181 if (NewState != DISABLE)
1182 {
1183 RCC->BDCR |= RCC_BDCR_BDRST;
1184 }
1185 else
1186 {
1187 RCC->BDCR &= ~RCC_BDCR_BDRST;
1188 }
1189 }
1190
1191 /**
1192 * @brief Enables or disables the AHB peripheral clock.
1193 * @note After reset, the peripheral clock (used for registers read/write access)
1194 * is disabled and the application software has to enable this clock before
1195 * using it.
1196 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
1197 * This parameter can be any combination of the following values:
1198 * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
1199 * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
1200 * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
1201 * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
1202 * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
1203 * @arg RCC_AHBPeriph_TS: TS clock
1204 * @arg RCC_AHBPeriph_CRC: CRC clock
1205 * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
1206 * @arg RCC_AHBPeriph_SRAM: SRAM clock
1207 * @arg RCC_AHBPeriph_DMA1: DMA1 clock
1208 * @arg RCC_AHBPeriph_DMA2: DMA2 clock
1209 * @param NewState: new state of the specified peripheral clock.
1210 * This parameter can be: ENABLE or DISABLE.
1211 * @retval None
1212 */
RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph,FunctionalState NewState)1213 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
1214 {
1215 /* Check the parameters */
1216 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
1217 assert_param(IS_FUNCTIONAL_STATE(NewState));
1218
1219 if (NewState != DISABLE)
1220 {
1221 RCC->AHBENR |= RCC_AHBPeriph;
1222 }
1223 else
1224 {
1225 RCC->AHBENR &= ~RCC_AHBPeriph;
1226 }
1227 }
1228
1229 /**
1230 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
1231 * @note After reset, the peripheral clock (used for registers read/write access)
1232 * is disabled and the application software has to enable this clock before
1233 * using it.
1234 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
1235 * This parameter can be any combination of the following values:
1236 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
1237 * @arg RCC_APB2Periph_USART6: USART6 clock
1238 * @arg RCC_APB2Periph_USART7: USART7 clock
1239 * @arg RCC_APB2Periph_USART8: USART8 clock
1240 * @arg RCC_APB2Periph_ADC1: ADC1 clock
1241 * @arg RCC_APB2Periph_TIM1: TIM1 clock
1242 * @arg RCC_APB2Periph_SPI1: SPI1 clock
1243 * @arg RCC_APB2Periph_USART1: USART1 clock
1244 * @arg RCC_APB2Periph_TIM15: TIM15 clock
1245 * @arg RCC_APB2Periph_TIM16: TIM16 clock
1246 * @arg RCC_APB2Periph_TIM17: TIM17 clock
1247 * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
1248 * @param NewState: new state of the specified peripheral clock.
1249 * This parameter can be: ENABLE or DISABLE.
1250 * @retval None
1251 */
RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)1252 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1253 {
1254 /* Check the parameters */
1255 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1256 assert_param(IS_FUNCTIONAL_STATE(NewState));
1257
1258 if (NewState != DISABLE)
1259 {
1260 RCC->APB2ENR |= RCC_APB2Periph;
1261 }
1262 else
1263 {
1264 RCC->APB2ENR &= ~RCC_APB2Periph;
1265 }
1266 }
1267
1268 /**
1269 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
1270 * @note After reset, the peripheral clock (used for registers read/write access)
1271 * is disabled and the application software has to enable this clock before
1272 * using it.
1273 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
1274 * This parameter can be any combination of the following values:
1275 * @arg RCC_APB1Periph_TIM2: TIM2 clock
1276 * @arg RCC_APB1Periph_TIM3: TIM3 clock
1277 * @arg RCC_APB1Periph_TIM6: TIM6 clock
1278 * @arg RCC_APB1Periph_TIM14: TIM14 clock
1279 * @arg RCC_APB1Periph_WWDG: WWDG clock
1280 * @arg RCC_APB1Periph_SPI2: SPI2 clock
1281 * @arg RCC_APB1Periph_USART2: USART2 clock
1282 * @arg RCC_APB1Periph_I2C1: I2C1 clock
1283 * @arg RCC_APB1Periph_I2C2: I2C2 clock
1284 * @arg RCC_APB1Periph_PWR: PWR clock
1285 * @param NewState: new state of the specified peripheral clock.
1286 * This parameter can be: ENABLE or DISABLE.
1287 * @retval None
1288 */
RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)1289 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1290 {
1291 /* Check the parameters */
1292 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1293 assert_param(IS_FUNCTIONAL_STATE(NewState));
1294
1295 if (NewState != DISABLE)
1296 {
1297 RCC->APB1ENR |= RCC_APB1Periph;
1298 }
1299 else
1300 {
1301 RCC->APB1ENR &= ~RCC_APB1Periph;
1302 }
1303 }
1304
1305 /**
1306 * @brief Forces or releases AHB peripheral reset.
1307 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
1308 * This parameter can be any combination of the following values:
1309 * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
1310 * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
1311 * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
1312 * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
1313 * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
1314 * @arg RCC_AHBPeriph_TS: TS clock
1315 * @param NewState: new state of the specified peripheral reset.
1316 * This parameter can be: ENABLE or DISABLE.
1317 * @retval None
1318 */
RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph,FunctionalState NewState)1319 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
1320 {
1321 /* Check the parameters */
1322 assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
1323 assert_param(IS_FUNCTIONAL_STATE(NewState));
1324
1325 if (NewState != DISABLE)
1326 {
1327 RCC->AHBRSTR |= RCC_AHBPeriph;
1328 }
1329 else
1330 {
1331 RCC->AHBRSTR &= ~RCC_AHBPeriph;
1332 }
1333 }
1334
1335 /**
1336 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
1337 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
1338 * This parameter can be any combination of the following values:
1339 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
1340 * @arg RCC_APB2Periph_USART6: USART6 clock
1341 * @arg RCC_APB2Periph_USART7: USART7 clock
1342 * @arg RCC_APB2Periph_USART8: USART8 clock
1343 * @arg RCC_APB2Periph_ADC1: ADC1 clock
1344 * @arg RCC_APB2Periph_TIM1: TIM1 clock
1345 * @arg RCC_APB2Periph_SPI1: SPI1 clock
1346 * @arg RCC_APB2Periph_USART1: USART1 clock
1347 * @arg RCC_APB2Periph_TIM15: TIM15 clock
1348 * @arg RCC_APB2Periph_TIM16: TIM16 clock
1349 * @arg RCC_APB2Periph_TIM17: TIM17 clock
1350 * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
1351 * @param NewState: new state of the specified peripheral reset.
1352 * This parameter can be: ENABLE or DISABLE.
1353 * @retval None
1354 */
RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)1355 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1356 {
1357 /* Check the parameters */
1358 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1359 assert_param(IS_FUNCTIONAL_STATE(NewState));
1360
1361 if (NewState != DISABLE)
1362 {
1363 RCC->APB2RSTR |= RCC_APB2Periph;
1364 }
1365 else
1366 {
1367 RCC->APB2RSTR &= ~RCC_APB2Periph;
1368 }
1369 }
1370
1371 /**
1372 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
1373 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
1374 * This parameter can be any combination of the following values:
1375 * @arg RCC_APB1Periph_TIM2: TIM2 clock,
1376 * @arg RCC_APB1Periph_TIM3: TIM3 clock
1377 * @arg RCC_APB1Periph_TIM6: TIM6 clock
1378 * @arg RCC_APB1Periph_TIM14: TIM14 clock
1379 * @arg RCC_APB1Periph_WWDG: WWDG clock
1380 * @arg RCC_APB1Periph_SPI2: SPI2 clock
1381 * @arg RCC_APB1Periph_USART2: USART2 clock
1382 * @arg RCC_APB1Periph_I2C1: I2C1 clock
1383 * @arg RCC_APB1Periph_I2C2: I2C2 clock
1384 * @arg RCC_APB1Periph_PWR: PWR clock
1385 * @param NewState: new state of the specified peripheral clock.
1386 * This parameter can be: ENABLE or DISABLE.
1387 * @retval None
1388 */
RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)1389 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1390 {
1391 /* Check the parameters */
1392 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1393 assert_param(IS_FUNCTIONAL_STATE(NewState));
1394
1395 if (NewState != DISABLE)
1396 {
1397 RCC->APB1RSTR |= RCC_APB1Periph;
1398 }
1399 else
1400 {
1401 RCC->APB1RSTR &= ~RCC_APB1Periph;
1402 }
1403 }
1404
1405 /**
1406 * @}
1407 */
1408
1409 /** @defgroup RCC_Group4 Interrupts and flags management functions
1410 * @brief Interrupts and flags management functions
1411 *
1412 @verbatim
1413 ===============================================================================
1414 ##### Interrupts and flags management functions #####
1415 ===============================================================================
1416 @endverbatim
1417 * @{
1418 */
1419
1420 /**
1421 * @brief Enables or disables the specified RCC interrupts.
1422 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
1423 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
1424 * automatically generated. The NMI will be executed indefinitely, and
1425 * since NMI has higher priority than any other IRQ (and main program)
1426 * the application will be stacked in the NMI ISR unless the CSS interrupt
1427 * pending bit is cleared.
1428 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
1429 * This parameter can be any combination of the following values:
1430 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1431 * @arg RCC_IT_LSERDY: LSE ready interrupt
1432 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1433 * @arg RCC_IT_HSERDY: HSE ready interrupt
1434 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1435 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
1436 * @param NewState: new state of the specified RCC interrupts.
1437 * This parameter can be: ENABLE or DISABLE.
1438 * @retval None
1439 */
RCC_ITConfig(uint8_t RCC_IT,FunctionalState NewState)1440 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
1441 {
1442 /* Check the parameters */
1443 assert_param(IS_RCC_IT(RCC_IT));
1444 assert_param(IS_FUNCTIONAL_STATE(NewState));
1445
1446 if (NewState != DISABLE)
1447 {
1448 /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
1449 *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
1450 }
1451 else
1452 {
1453 /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
1454 *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
1455 }
1456 }
1457
1458 /**
1459 * @brief Checks whether the specified RCC flag is set or not.
1460 * @param RCC_FLAG: specifies the flag to check.
1461 * This parameter can be one of the following values:
1462 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
1463 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
1464 * @arg RCC_FLAG_PLLRDY: PLL clock ready
1465 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
1466 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
1467 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
1468 * @arg RCC_FLAG_PINRST: Pin reset
1469 * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset
1470 * @arg RCC_FLAG_PORRST: POR/PDR reset
1471 * @arg RCC_FLAG_SFTRST: Software reset
1472 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
1473 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
1474 * @arg RCC_FLAG_LPWRRST: Low Power reset
1475 * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
1476 * @retval The new state of RCC_FLAG (SET or RESET).
1477 */
RCC_GetFlagStatus(uint8_t RCC_FLAG)1478 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
1479 {
1480 uint32_t tmp = 0;
1481 uint32_t statusreg = 0;
1482 FlagStatus bitstatus = RESET;
1483
1484 /* Check the parameters */
1485 assert_param(IS_RCC_FLAG(RCC_FLAG));
1486
1487 /* Get the RCC register index */
1488 tmp = RCC_FLAG >> 5;
1489
1490 if (tmp == 0) /* The flag to check is in CR register */
1491 {
1492 statusreg = RCC->CR;
1493 }
1494 else if (tmp == 1) /* The flag to check is in BDCR register */
1495 {
1496 statusreg = RCC->BDCR;
1497 }
1498 else if (tmp == 2) /* The flag to check is in CSR register */
1499 {
1500 statusreg = RCC->CSR;
1501 }
1502 else /* The flag to check is in CR2 register */
1503 {
1504 statusreg = RCC->CR2;
1505 }
1506
1507 /* Get the flag position */
1508 tmp = RCC_FLAG & FLAG_MASK;
1509
1510 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
1511 {
1512 bitstatus = SET;
1513 }
1514 else
1515 {
1516 bitstatus = RESET;
1517 }
1518 /* Return the flag status */
1519 return bitstatus;
1520 }
1521
1522 /**
1523 * @brief Clears the RCC reset flags.
1524 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
1525 * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
1526 * RCC_FLAG_LPWRRST.
1527 * @param None
1528 * @retval None
1529 */
RCC_ClearFlag(void)1530 void RCC_ClearFlag(void)
1531 {
1532 /* Set RMVF bit to clear the reset flags */
1533 RCC->CSR |= RCC_CSR_RMVF;
1534 }
1535
1536 /**
1537 * @brief Checks whether the specified RCC interrupt has occurred or not.
1538 * @param RCC_IT: specifies the RCC interrupt source to check.
1539 * This parameter can be one of the following values:
1540 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1541 * @arg RCC_IT_LSERDY: LSE ready interrupt
1542 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1543 * @arg RCC_IT_HSERDY: HSE ready interrupt
1544 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1545 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
1546 * @arg RCC_IT_CSS: Clock Security System interrupt
1547 * @retval The new state of RCC_IT (SET or RESET).
1548 */
RCC_GetITStatus(uint8_t RCC_IT)1549 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
1550 {
1551 ITStatus bitstatus = RESET;
1552
1553 /* Check the parameters */
1554 assert_param(IS_RCC_GET_IT(RCC_IT));
1555
1556 /* Check the status of the specified RCC interrupt */
1557 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
1558 {
1559 bitstatus = SET;
1560 }
1561 else
1562 {
1563 bitstatus = RESET;
1564 }
1565 /* Return the RCC_IT status */
1566 return bitstatus;
1567 }
1568
1569 /**
1570 * @brief Clears the RCC's interrupt pending bits.
1571 * @param RCC_IT: specifies the interrupt pending bit to clear.
1572 * This parameter can be any combination of the following values:
1573 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1574 * @arg RCC_IT_LSERDY: LSE ready interrupt
1575 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1576 * @arg RCC_IT_HSERDY: HSE ready interrupt
1577 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1578 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
1579 * @arg RCC_IT_CSS: Clock Security System interrupt
1580 * @retval None
1581 */
RCC_ClearITPendingBit(uint8_t RCC_IT)1582 void RCC_ClearITPendingBit(uint8_t RCC_IT)
1583 {
1584 /* Check the parameters */
1585 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
1586
1587 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
1588 pending bits */
1589 *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
1590 }
1591
1592 /**
1593 * @}
1594 */
1595
1596 /**
1597 * @}
1598 */
1599
1600 /**
1601 * @}
1602 */
1603
1604 /**
1605 * @}
1606 */
1607
1608