1 /*
2  * Copyright (c) 2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 /*
9  * Note:
10  *  PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
11  *  besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
12  *  expected SoC function can be enabled on these IOs.
13  *
14  */
15 #include "board.h"
16 #include "pinmux.h"
17 
init_xtal_pins(void)18 void init_xtal_pins(void)
19 {
20     /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */
21     /*
22      * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
23      * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
24      */
25 }
26 
init_py_pins_as_pgpio(void)27 void init_py_pins_as_pgpio(void)
28 {
29     /* Set PY00-PY05 default function to PGPIO */
30     HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PGPIO_Y_00;
31     HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PGPIO_Y_01;
32     HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02;
33     HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03;
34     HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_PGPIO_Y_04;
35     HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_PGPIO_Y_05;
36 }
37 
init_uart_pins(UART_Type * ptr)38 void init_uart_pins(UART_Type *ptr)
39 {
40     if (ptr == HPM_UART0) {
41         HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
42         HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
43     } else if (ptr == HPM_UART2) {
44         HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD;
45         HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD;
46         HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE;
47     } else if (ptr == HPM_UART3) {
48         /* using for uart_lin function */
49         HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_UART3_RXD;
50         HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_UART3_TXD;
51     } else if (ptr == HPM_UART7) {
52         /* using for uart_lin function */
53         HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_UART7_TXD;
54         HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_UART7_RXD;
55     } else {
56         ;
57     }
58 }
59 
init_lin_transceiver_ctrl_pin(void)60 void init_lin_transceiver_ctrl_pin(void)
61 {
62     /* PA24 is used to control the 12V power supply of the LIN transceiver */
63     HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_GPIO_A_24;
64     /* PA13 is used to control the LIN transceiver not to enter sleep mode */
65     HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_GPIO_A_13;
66 }
67 
68 /* for uart_lin case, need to configure pin as gpio to sent break signal */
init_uart_pin_as_gpio(UART_Type * ptr)69 void init_uart_pin_as_gpio(UART_Type *ptr)
70 {
71     /* pull-up */
72     uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
73 
74     if (ptr == HPM_UART3) {
75         HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl;
76         HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl;
77         HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14;
78         HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_GPIO_A_15;
79     }
80 }
81 
init_i2c_pins(I2C_Type * ptr)82 void init_i2c_pins(I2C_Type *ptr)
83 {
84     if (ptr == HPM_I2C0) {
85         HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
86         HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
87         HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
88         HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
89     } else if (ptr == HPM_I2C1) {
90         HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
91         HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
92         HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
93         HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
94     } else {
95         ;
96     }
97 }
98 
init_gpio_pins(void)99 void init_gpio_pins(void)
100 {
101     /* configure pad setting: pull enable and pull up, schmitt trigger enable */
102     /* enable schmitt trigger to eliminate jitter of pin used as button */
103 
104     /* Button */
105     uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
106     HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09;
107     HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl;
108 }
109 
init_spi_pins(SPI_Type * ptr)110 void init_spi_pins(SPI_Type *ptr)
111 {
112     if (ptr == HPM_SPI1) {
113         HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_SPI1_CS_1;
114         HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0;
115         HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
116         HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
117         HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
118     }
119 }
120 
init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)121 void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
122 {
123     if (ptr == HPM_SPI1) {
124         HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPIO_A_25;
125         HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26;
126         HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
127         HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
128         HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
129     }
130 }
131 
132 
init_gptmr_pins(GPTMR_Type * ptr)133 void init_gptmr_pins(GPTMR_Type *ptr)
134 {
135     if (ptr == HPM_GPTMR0) {
136         HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0;
137         HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0;
138         HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1;
139     }
140 }
141 
init_hall_trgm_pins(void)142 void init_hall_trgm_pins(void)
143 {
144     init_qeiv2_uvw_pins(HPM_QEI1);
145 }
146 
init_qei_trgm_pins(void)147 void init_qei_trgm_pins(void)
148 {
149     init_qeiv2_ab_pins(HPM_QEI1);
150 }
151 
init_butn_pins(void)152 void init_butn_pins(void)
153 {
154     /* configure pad setting: pull enable and pull up, schmitt trigger enable */
155     /* enable schmitt trigger to eliminate jitter of pin used as button */
156 
157     /* Button */
158     uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
159     HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09;
160     HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl;
161 }
162 
init_acmp_pins(void)163 void init_acmp_pins(void)
164 {
165     /* configure to ACMP_COMP_1(ALT16) function */
166     HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ACMP_COMP_1;
167     /* configure to CMP1_INN4 function */
168     HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
169 }
170 
init_pwm_pins(PWM_Type * ptr)171 void init_pwm_pins(PWM_Type *ptr)
172 {
173     if (ptr == HPM_PWM0) {
174         HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_PWM0_P_2;
175         HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM0_P_3;
176         HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_PWM0_P_4;
177         HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_PWM0_P_5;
178         HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_PWM0_P_6;
179         HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_PWM0_P_7;
180     }
181 }
182 
init_adc_pins(void)183 void init_adc_pins(void)
184 {
185     HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;         /* ADC0.13 */
186 }
187 
init_adc_bldc_pins(void)188 void init_adc_bldc_pins(void)
189 {
190     HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;         /* ADC_IU:   ADC0.5 /ADC1.5  */
191     HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;         /* ADC_IV:   ADC0.6 /ADC1.6  */
192 }
193 
init_adc_qeiv2_pins(void)194 void init_adc_qeiv2_pins(void)
195 {
196     HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;         /* ADC_IW:   ADC0.4 /ADC1.4  */
197     HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;         /* ADC_IU:   ADC0.5 /ADC1.5  */
198 }
199 
init_usb_pins(void)200 void init_usb_pins(void)
201 {
202     /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */
203     /*
204      * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
205      * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
206      */
207 
208     /* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */
209     /*
210      * HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
211      * HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
212      */
213 
214     /* USB0_ID */
215     HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
216     /* USB0_OC */
217     HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
218     /* USB0_PWR */
219     HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
220 
221     /* PY port IO needs to configure PIOC as well */
222     HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
223     HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
224     HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
225 }
226 
init_can_pins(MCAN_Type * ptr)227 void init_can_pins(MCAN_Type *ptr)
228 {
229     if (ptr == HPM_MCAN3) {
230         HPM_IOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_MCAN3_RXD;
231         HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_MCAN3_TXD;
232         /* PY port IO needs to configure PIOC as well */
233         HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04;
234         HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05;
235     }
236 }
237 
init_led_pins_as_gpio(void)238 void init_led_pins_as_gpio(void)
239 {
240     HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPIO_A_23;
241 }
242 
init_led_pins_as_pwm(void)243 void init_led_pins_as_pwm(void)
244 {
245     HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_TRGM0_P_03;
246 }
247 
init_dac_pins(DAC_Type * ptr)248 void init_dac_pins(DAC_Type *ptr)
249 {
250     if (ptr == HPM_DAC0) {
251         HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* DAC0.OUT */
252     } else if (ptr == HPM_DAC1) {
253         HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* DAC1.OUT */
254     }
255 }
256 
init_plb_pins(void)257 void init_plb_pins(void)
258 {
259     HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02;
260 }
261 
init_qeo_pins(QEO_Type * ptr)262 void init_qeo_pins(QEO_Type *ptr)
263 {
264     if (ptr == HPM_QEO0) {
265         HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_QEO0_A;
266         HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_QEO0_B;
267         HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_QEO0_Z;
268     }
269 }
270 
init_sei_pins(SEI_Type * ptr,uint8_t sei_ctrl_idx)271 void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx)
272 {
273     if (ptr == HPM_SEI) {
274         if (sei_ctrl_idx == SEI_CTRL_1) {
275             HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_SEI1_DE;
276             HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_SEI1_CK;
277             HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_SEI1_TX;
278             HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_SEI1_RX;
279         }
280     }
281 }
282 
init_rdc_pin(void)283 void init_rdc_pin(void)
284 {
285     HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_RDC0_EXC_P;
286     HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
287     HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
288 
289 /*The GPIO is designed for debug */
290 #ifdef RDC_SAMPLE_TEST_GPIO_OUTPUT
291     HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_TRGM0_P_00;
292 #endif
293 }
294 
init_qeiv2_uvw_pins(QEIV2_Type * ptr)295 void init_qeiv2_uvw_pins(QEIV2_Type *ptr)
296 {
297     if (ptr == HPM_QEI1) {
298         HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A;
299         HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B;
300         HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z;
301     }
302 }
303 
init_qeiv2_ab_pins(QEIV2_Type * ptr)304 void init_qeiv2_ab_pins(QEIV2_Type *ptr)
305 {
306     if (ptr == HPM_QEI1) {
307         HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A;
308         HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B;
309     }
310 }
311 
init_qeiv2_abz_pins(QEIV2_Type * ptr)312 void init_qeiv2_abz_pins(QEIV2_Type *ptr)
313 {
314     if (ptr == HPM_QEI1) {
315         HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A;
316         HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B;
317         HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z;
318     }
319 }
320 
init_opamp_pins(void)321 void init_opamp_pins(void)
322 {
323     HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
324     HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
325 }
326