1 /*
2 * Copyright (c) 2023 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 */
6
7 #include "board.h"
8 #include "hpm_uart_drv.h"
9 #include "hpm_gptmr_drv.h"
10 #include "hpm_gpio_drv.h"
11 #include "hpm_usb_drv.h"
12 #include "hpm_clock_drv.h"
13 #include "hpm_pllctlv2_drv.h"
14 #include "hpm_i2c_drv.h"
15 #include "hpm_pcfg_drv.h"
16
17 static board_timer_cb timer_cb;
18
19 /**
20 * @brief FLASH configuration option definitions:
21 * option[0]:
22 * [31:16] 0xfcf9 - FLASH configuration option tag
23 * [15:4] 0 - Reserved
24 * [3:0] option words (exclude option[0])
25 * option[1]:
26 * [31:28] Flash probe type
27 * 0 - SFDP SDR / 1 - SFDP DDR
28 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
29 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
30 * 6 - OctaBus DDR (SPI -> OPI DDR)
31 * 8 - Xccela DDR (SPI -> OPI DDR)
32 * 10 - EcoXiP DDR (SPI -> OPI DDR)
33 * [27:24] Command Pads after Power-on Reset
34 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
35 * [23:20] Command Pads after Configuring FLASH
36 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
37 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
38 * 0 - Not needed
39 * 1 - QE bit is at bit 6 in Status Register 1
40 * 2 - QE bit is at bit1 in Status Register 2
41 * 3 - QE bit is at bit7 in Status Register 2
42 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
43 * [15:8] Dummy cycles
44 * 0 - Auto-probed / detected / default value
45 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
46 * [7:4] Misc.
47 * 0 - Not used
48 * 1 - SPI mode
49 * 2 - Internal loopback
50 * 3 - External DQS
51 * [3:0] Frequency option
52 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
53 *
54 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
55 * [31:20] Reserved
56 * [19:16] IO voltage
57 * 0 - 3V / 1 - 1.8V
58 * [15:12] Pin group
59 * 0 - 1st group / 1 - 2nd group
60 * [11:8] Connection selection
61 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
62 * [7:0] Drive Strength
63 * 0 - Default value
64 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
65 * JESD216)
66 * [31:16] reserved
67 * [15:12] Sector Erase Command Option, not required here
68 * [11:8] Sector Size Option, not required here
69 * [7:0] Flash Size Option
70 * 0 - 4MB / 1 - 8MB / 2 - 16MB
71 */
72 #if defined(FLASH_XIP) && FLASH_XIP
73 __attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0};
74 #endif
75
76 #if defined(FLASH_UF2) && FLASH_UF2
77 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
78 #endif
79
board_init_console(void)80 void board_init_console(void)
81 {
82 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
83 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
84 console_config_t cfg;
85
86 /* uart needs to configure pin function before enabling clock, otherwise the level change of
87 * uart rx pin when configuring pin function will cause a wrong data to be received.
88 * And a uart rx dma request will be generated by default uart fifo dma trigger level.
89 */
90 init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
91
92 /* Configure the UART clock to 24MHz */
93 clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
94 clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
95
96 cfg.type = BOARD_CONSOLE_TYPE;
97 cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE;
98 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
99 cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
100
101 if (status_success != console_init(&cfg)) {
102 /* failed to initialize debug console */
103 while (1) {
104 }
105 }
106 #else
107 while (1)
108 ;
109 #endif
110 #endif
111 }
112
board_print_banner(void)113 void board_print_banner(void)
114 {
115 const uint8_t banner[] = "\n"
116 "----------------------------------------------------------------------\n"
117 "$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n"
118 "$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n"
119 "$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n"
120 "$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n"
121 "$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n"
122 "$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n"
123 "$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n"
124 "\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n"
125 "----------------------------------------------------------------------\n";
126 #ifdef SDK_VERSION_STRING
127 printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
128 #endif
129 printf("%s", banner);
130 }
131
board_print_clock_freq(void)132 void board_print_clock_freq(void)
133 {
134 printf("==============================\n");
135 printf(" %s clock summary\n", BOARD_NAME);
136 printf("==============================\n");
137 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
138 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
139 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
140 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
141 printf("==============================\n");
142 }
143
board_init(void)144 void board_init(void)
145 {
146 init_xtal_pins();
147 init_py_pins_as_pgpio();
148 board_init_usb_dp_dm_pins();
149
150 board_init_clock();
151 board_init_console();
152 board_init_pmp();
153 #if BOARD_SHOW_CLOCK
154 board_print_clock_freq();
155 #endif
156 #if BOARD_SHOW_BANNER
157 board_print_banner();
158 #endif
159 }
160
board_init_usb_dp_dm_pins(void)161 void board_init_usb_dp_dm_pins(void)
162 {
163 /* Disconnect usb dp/dm pins pull down 45ohm resistance */
164
165 while (sysctl_resource_any_is_busy(HPM_SYSCTL)) {
166 ;
167 }
168 if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) {
169 if (clock_check_in_group(clock_usb0, 0)) {
170 usb_phy_disable_dp_dm_pulldown(HPM_USB0);
171 } else {
172 clock_add_to_group(clock_usb0, 0);
173 usb_phy_disable_dp_dm_pulldown(HPM_USB0);
174 clock_remove_from_group(clock_usb0, 0);
175 }
176 } else {
177 uint8_t tmp;
178 tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal);
179 sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03);
180 clock_add_to_group(clock_usb0, 0);
181 usb_phy_disable_dp_dm_pulldown(HPM_USB0);
182 clock_remove_from_group(clock_usb0, 0);
183 while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) {
184 ;
185 }
186 sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp);
187 }
188 }
189
board_init_clock(void)190 void board_init_clock(void)
191 {
192 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
193
194 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
195 /* Configure the External OSC ramp-up time: ~9ms */
196 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
197
198 /* Select clock setting preset1 */
199 sysctl_clock_set_preset(HPM_SYSCTL, 2);
200 }
201
202 /* group0[0] */
203 clock_add_to_group(clock_cpu0, 0);
204 clock_add_to_group(clock_ahb, 0);
205 clock_add_to_group(clock_lmm0, 0);
206 clock_add_to_group(clock_mchtmr0, 0);
207 clock_add_to_group(clock_rom, 0);
208 clock_add_to_group(clock_gptmr0, 0);
209 clock_add_to_group(clock_gptmr1, 0);
210 clock_add_to_group(clock_i2c2, 0);
211 clock_add_to_group(clock_spi1, 0);
212 clock_add_to_group(clock_uart0, 0);
213 clock_add_to_group(clock_uart3, 0);
214
215 clock_add_to_group(clock_watchdog0, 0);
216 clock_add_to_group(clock_watchdog1, 0);
217 clock_add_to_group(clock_mbx0, 0);
218 clock_add_to_group(clock_tsns, 0);
219 clock_add_to_group(clock_crc0, 0);
220 clock_add_to_group(clock_adc0, 0);
221 clock_add_to_group(clock_acmp, 0);
222 clock_add_to_group(clock_kman, 0);
223 clock_add_to_group(clock_gpio, 0);
224 clock_add_to_group(clock_hdma, 0);
225 clock_add_to_group(clock_xpi0, 0);
226 clock_add_to_group(clock_usb0, 0);
227
228 /* Connect Group0 to CPU0 */
229 clock_connect_group_to_cpu(0, 0);
230
231 /* Bump up DCDC voltage to 1175mv */
232 pcfg_dcdc_set_voltage(HPM_PCFG, 1175);
233
234 /* Configure CPU to 360MHz, AXI/AHB to 120MHz */
235 sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3);
236 /* Configure PLL0 Post Divider */
237 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 720MHz */
238 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 450MHz */
239 pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 300MHz */
240 /* Configure PLL0 Frequency to 720MHz */
241 pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 720000000);
242
243 clock_update_core_clock();
244
245 /* Configure mchtmr to 24MHz */
246 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
247 }
248
board_init_gptmr_clock(GPTMR_Type * ptr)249 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
250 {
251 uint32_t freq = 0;
252 clock_name_t gptmr_clock =0;
253 uint32_t HPM_GPTMR = (uint32_t)ptr;
254 bool gptmr_valid = true;
255
256 switch(HPM_GPTMR){
257 case HPM_GPTMR0_BASE:
258 gptmr_clock = clock_gptmr0;
259 break;
260 case HPM_GPTMR1_BASE:
261 gptmr_clock = clock_gptmr1;
262 break;
263 default:
264 gptmr_valid = false;
265 }
266 if(gptmr_valid)
267 {
268 clock_add_to_group(gptmr_clock, 0);
269 clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4);
270 freq = clock_get_frequency(gptmr_clock);
271 }
272 return freq;
273 }
274
board_delay_us(uint32_t us)275 void board_delay_us(uint32_t us)
276 {
277 clock_cpu_delay_us(us);
278 }
279
board_delay_ms(uint32_t ms)280 void board_delay_ms(uint32_t ms)
281 {
282 clock_cpu_delay_ms(ms);
283 }
284
board_timer_create(uint32_t ms,board_timer_cb cb)285 void board_timer_create(uint32_t ms, board_timer_cb cb)
286 {
287 uint32_t gptmr_freq;
288 gptmr_channel_config_t config;
289
290 timer_cb = cb;
291 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
292
293 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
294 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
295
296 config.reload = gptmr_freq / 1000 * ms;
297 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
298 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
299 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
300
301 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
302 }
303
board_init_gpio_pins(void)304 void board_init_gpio_pins(void)
305 {
306 init_gpio_pins();
307 gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN);
308 }
309
board_init_led_pins(void)310 void board_init_led_pins(void)
311 {
312 init_led_pins_as_gpio();
313 gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
314 }
315
board_init_usb_pins(void)316 void board_init_usb_pins(void)
317 {
318 init_usb_pins();
319 usb_hcd_set_power_ctrl_polarity(BOARD_USB, true);
320 /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
321 board_delay_ms(100);
322
323 /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */
324 usb_phy_using_internal_vbus(BOARD_USB);
325 }
326
board_led_write(uint8_t state)327 void board_led_write(uint8_t state)
328 {
329 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
330 }
331
board_led_toggle(void)332 void board_led_toggle(void)
333 {
334 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
335 }
336
board_init_uart(UART_Type * ptr)337 void board_init_uart(UART_Type *ptr)
338 {
339 /* configure uart's pin before opening uart's clock */
340 init_uart_pins(ptr);
341 board_init_uart_clock(ptr);
342 }
343
board_ungate_mchtmr_at_lp_mode(void)344 void board_ungate_mchtmr_at_lp_mode(void)
345 {
346 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
347 sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
348 }
349
board_init_spi_clock(SPI_Type * ptr)350 uint32_t board_init_spi_clock(SPI_Type *ptr)
351 {
352 if (ptr == HPM_SPI1) {
353 clock_add_to_group(clock_spi1, 0);
354 return clock_get_frequency(clock_spi1);
355 }
356 return 0;
357 }
358
board_init_spi_pins(SPI_Type * ptr)359 void board_init_spi_pins(SPI_Type *ptr)
360 {
361 init_spi_pins(ptr);
362 }
363
board_write_spi_cs(uint32_t pin,uint8_t state)364 void board_write_spi_cs(uint32_t pin, uint8_t state)
365 {
366 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
367 }
368
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)369 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
370 {
371 init_spi_pins_with_gpio_as_cs(ptr);
372 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
373 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
374 }
375
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)376 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
377 {
378 (void) usb_index;
379 (void) level;
380 }
381
board_init_adc16_clock(ADC16_Type * ptr,bool clk_src_ahb)382 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
383 {
384 uint32_t freq = 0;
385
386 if (ptr == HPM_ADC0) {
387 if (clk_src_ahb) {
388 /* Configure the ADC clock from AHB (@200MHz by default)*/
389 clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
390 } else {
391 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
392 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
393 clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U);
394 }
395
396 freq = clock_get_frequency(clock_adc0);
397 }
398
399 return freq;
400 }
401
board_init_adc16_pins(void)402 void board_init_adc16_pins(void)
403 {
404 init_adc_pins();
405 }
406
board_disable_output_rgb_led(uint8_t color)407 void board_disable_output_rgb_led(uint8_t color)
408 {
409 (void) color;
410 }
411
board_enable_output_rgb_led(uint8_t color)412 void board_enable_output_rgb_led(uint8_t color)
413 {
414 (void) color;
415 }
416
board_get_led_gpio_off_level(void)417 uint8_t board_get_led_gpio_off_level(void)
418 {
419 return BOARD_LED_OFF_LEVEL;
420 }
421
board_init_pmp(void)422 void board_init_pmp(void)
423 {
424 }
425
board_init_uart_clock(UART_Type * ptr)426 uint32_t board_init_uart_clock(UART_Type *ptr)
427 {
428 uint32_t freq = 0U;
429 if (ptr == HPM_UART0) {
430 clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
431 clock_add_to_group(clock_uart0, 0);
432 freq = clock_get_frequency(clock_uart0);
433 } else if (ptr == HPM_UART2) {
434 clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 6);
435 clock_add_to_group(clock_uart2, 0);
436 freq = clock_get_frequency(clock_uart2);
437 } else if (ptr == HPM_UART3) {
438 clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 6); /* 50MHz */
439 clock_add_to_group(clock_uart3, 0);
440 freq = clock_get_frequency(clock_uart3);
441 }
442
443 return freq;
444 }
445
board_i2c_bus_clear(I2C_Type * ptr)446 void board_i2c_bus_clear(I2C_Type *ptr)
447 {
448 if (i2c_get_line_scl_status(ptr) == false) {
449 printf("CLK is low, please power cycle the board\n");
450 while (1) {
451 }
452 }
453 if (i2c_get_line_sda_status(ptr) == false) {
454 printf("SDA is low, try to issue I2C bus clear\n");
455 } else {
456 printf("I2C bus is ready\n");
457 return;
458 }
459 i2s_gen_reset_signal(ptr, 9);
460 board_delay_ms(100);
461 printf("I2C bus is cleared\n");
462 }
463
board_init_i2c(I2C_Type * ptr)464 void board_init_i2c(I2C_Type *ptr)
465 {
466 i2c_config_t config;
467 hpm_stat_t stat;
468 uint32_t freq;
469 if (ptr == NULL) {
470 return;
471 }
472 init_i2c_pins(ptr);
473 board_i2c_bus_clear(ptr);
474
475 clock_add_to_group(clock_i2c2, 0);
476 /* Configure the I2C clock to 24MHz */
477 clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
478
479 config.i2c_mode = i2c_mode_normal;
480 config.is_10bit_addressing = false;
481 freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
482 stat = i2c_init_master(ptr, freq, &config);
483 if (stat != status_success) {
484 printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
485 while (1) {
486 }
487 }
488
489 }
490
491