1 /*
2 * Copyright (c) 2023-2024 HPMicro
3 * SPDX-License-Identifier: BSD-3-Clause
4 *
5 *
6 */
7
8 #include "board.h"
9 #include "hpm_uart_drv.h"
10 #include "hpm_gptmr_drv.h"
11 #include "hpm_i2c_drv.h"
12 #include "hpm_gpio_drv.h"
13 #include "pinmux.h"
14 #include "hpm_pmp_drv.h"
15 #include "assert.h"
16 #include "hpm_clock_drv.h"
17 #include "hpm_sysctl_drv.h"
18 #include "hpm_pwm_drv.h"
19 #include "hpm_trgm_drv.h"
20 #include "hpm_pllctlv2_drv.h"
21 #include "hpm_pcfg_drv.h"
22
23 static board_timer_cb timer_cb;
24 ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag;
25
26 /**
27 * @brief FLASH configuration option definitions:
28 * option[0]:
29 * [31:16] 0xfcf9 - FLASH configuration option tag
30 * [15:4] 0 - Reserved
31 * [3:0] option words (exclude option[0])
32 * option[1]:
33 * [31:28] Flash probe type
34 * 0 - SFDP SDR / 1 - SFDP DDR
35 * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
36 * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
37 * 6 - OctaBus DDR (SPI -> OPI DDR)
38 * 8 - Xccela DDR (SPI -> OPI DDR)
39 * 10 - EcoXiP DDR (SPI -> OPI DDR)
40 * [27:24] Command Pads after Power-on Reset
41 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
42 * [23:20] Command Pads after Configuring FLASH
43 * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
44 * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
45 * 0 - Not needed
46 * 1 - QE bit is at bit 6 in Status Register 1
47 * 2 - QE bit is at bit1 in Status Register 2
48 * 3 - QE bit is at bit7 in Status Register 2
49 * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
50 * [15:8] Dummy cycles
51 * 0 - Auto-probed / detected / default value
52 * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
53 * [7:4] Misc.
54 * 0 - Not used
55 * 1 - SPI mode
56 * 2 - Internal loopback
57 * 3 - External DQS
58 * [3:0] Frequency option
59 * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
60 *
61 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
62 * [31:20] Reserved
63 * [19:16] IO voltage
64 * 0 - 3V / 1 - 1.8V
65 * [15:12] Pin group
66 * 0 - 1st group / 1 - 2nd group
67 * [11:8] Connection selection
68 * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
69 * [7:0] Drive Strength
70 * 0 - Default value
71 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
72 * JESD216)
73 * [31:16] reserved
74 * [15:12] Sector Erase Command Option, not required here
75 * [11:8] Sector Size Option, not required here
76 * [7:0] Flash Size Option
77 * 0 - 4MB / 1 - 8MB / 2 - 16MB
78 */
79 #if defined(FLASH_XIP) && FLASH_XIP
80 __attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 };
81 #endif
82
83 #if defined(FLASH_UF2) && FLASH_UF2
84 ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
85 #endif
86
board_init_console(void)87 void board_init_console(void)
88 {
89 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
90 #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
91 console_config_t cfg;
92
93 /* uart needs to configure pin function before enabling clock, otherwise the level change of
94 uart rx pin when configuring pin function will cause a wrong data to be received.
95 And a uart rx dma request will be generated by default uart fifo dma trigger level. */
96 init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);
97
98 /* Configure the UART clock to 24MHz */
99 clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U);
100 clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);
101
102 cfg.type = BOARD_CONSOLE_TYPE;
103 cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE;
104 cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
105 cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;
106
107 if (status_success != console_init(&cfg)) {
108 /* failed to initialize debug console */
109 while (1) {
110 }
111 }
112 #else
113 while (1)
114 ;
115 #endif
116 #endif
117 }
118
board_print_clock_freq(void)119 void board_print_clock_freq(void)
120 {
121 printf("==============================\n");
122 printf(" %s clock summary\n", BOARD_NAME);
123 printf("==============================\n");
124 printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
125 printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
126 printf("axi:\t\t %luHz\n", clock_get_frequency(clock_axi));
127 printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
128 printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
129 printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
130 printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
131 printf("==============================\n");
132 }
133
board_init_uart(UART_Type * ptr)134 void board_init_uart(UART_Type *ptr)
135 {
136 /* configure uart's pin before opening uart's clock */
137 init_uart_pins(ptr);
138 board_init_uart_clock(ptr);
139 }
140
board_print_banner(void)141 void board_print_banner(void)
142 {
143 const uint8_t banner[] = { "\n\
144 ----------------------------------------------------------------------\n\
145 $$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\
146 $$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\
147 $$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\
148 $$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\
149 $$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\
150 $$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\
151 $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\
152 \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\
153 ----------------------------------------------------------------------\n"};
154 #ifdef SDK_VERSION_STRING
155 printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
156 #endif
157 printf("%s", banner);
158 }
159
board_get_led_pwm_off_level(void)160 uint8_t board_get_led_pwm_off_level(void)
161 {
162 return BOARD_LED_OFF_LEVEL;
163 }
164
board_get_led_gpio_off_level(void)165 uint8_t board_get_led_gpio_off_level(void)
166 {
167 return BOARD_LED_OFF_LEVEL;
168 }
169
board_ungate_mchtmr_at_lp_mode(void)170 void board_ungate_mchtmr_at_lp_mode(void)
171 {
172 /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
173 sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
174 }
175
board_init(void)176 void board_init(void)
177 {
178 board_init_clock();
179 board_init_console();
180 board_init_pmp();
181 #if BOARD_SHOW_CLOCK
182 board_print_clock_freq();
183 #endif
184 #if BOARD_SHOW_BANNER
185 board_print_banner();
186 #endif
187 }
188
board_init_core1(void)189 void board_init_core1(void)
190 {
191 board_init_console();
192 board_init_pmp();
193 }
194
board_delay_us(uint32_t us)195 void board_delay_us(uint32_t us)
196 {
197 clock_cpu_delay_us(us);
198 }
199
board_delay_ms(uint32_t ms)200 void board_delay_ms(uint32_t ms)
201 {
202 clock_cpu_delay_ms(ms);
203 }
204
board_timer_isr(void)205 void board_timer_isr(void)
206 {
207 if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
208 gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
209 timer_cb();
210 }
211 }
212 SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
213
board_timer_create(uint32_t ms,board_timer_cb cb)214 void board_timer_create(uint32_t ms, board_timer_cb cb)
215 {
216 uint32_t gptmr_freq;
217 gptmr_channel_config_t config;
218
219 timer_cb = cb;
220 gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
221
222 clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
223 gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
224
225 config.reload = gptmr_freq / 1000 * ms;
226 gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
227 gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
228 intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
229
230 gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
231 }
232
board_i2c_bus_clear(I2C_Type * ptr)233 void board_i2c_bus_clear(I2C_Type *ptr)
234 {
235 init_i2c_pins_as_gpio(ptr);
236 if (ptr == BOARD_APP_I2C_BASE) {
237 gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN);
238 gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN);
239 if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN)) {
240 printf("CLK is low, please power cycle the board\n");
241 while (1) {
242 }
243 }
244 if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN)) {
245 printf("SDA is low, try to issue I2C bus clear\n");
246 } else {
247 printf("I2C bus is ready\n");
248 return;
249 }
250
251 gpio_set_pin_output(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN);
252 while (1) {
253 for (uint32_t i = 0; i < 9; i++) {
254 gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 1);
255 board_delay_ms(10);
256 gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 0);
257 board_delay_ms(10);
258 }
259 board_delay_ms(100);
260 }
261 printf("I2C bus is cleared\n");
262 }
263 }
264
board_init_i2c(I2C_Type * ptr)265 void board_init_i2c(I2C_Type *ptr)
266 {
267 i2c_config_t config;
268 hpm_stat_t stat;
269 uint32_t freq;
270 if (ptr == NULL) {
271 return;
272 }
273
274 board_i2c_bus_clear(ptr);
275 init_i2c_pins(ptr);
276 clock_add_to_group(clock_i2c0, 0);
277 clock_add_to_group(clock_i2c1, 0);
278 clock_add_to_group(clock_i2c2, 0);
279 clock_add_to_group(clock_i2c3, 0);
280 /* Configure the I2C clock to 24MHz */
281 clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U);
282
283 config.i2c_mode = i2c_mode_normal;
284 config.is_10bit_addressing = false;
285 freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME);
286 stat = i2c_init_master(ptr, freq, &config);
287 if (stat != status_success) {
288 printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr);
289 while (1) {
290 }
291 }
292 }
293
board_init_spi_clock(SPI_Type * ptr)294 uint32_t board_init_spi_clock(SPI_Type *ptr)
295 {
296 if (ptr == HPM_SPI1) {
297 /* SPI1 clock configure */
298 clock_add_to_group(clock_spi1, 0);
299 clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); /* 80MHz */
300
301 return clock_get_frequency(clock_spi1);
302 } else if (ptr == HPM_SPI2) {
303 /* SPI3 clock configure */
304 clock_add_to_group(clock_spi2, 0);
305 clock_set_source_divider(clock_spi2, clk_src_pll0_clk0, 5U); /* 80MHz */
306
307 return clock_get_frequency(clock_spi2);
308 } else if (ptr == HPM_SPI3) {
309 /* SPI3 clock configure */
310 clock_add_to_group(clock_spi3, 0);
311 clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */
312
313 return clock_get_frequency(clock_spi3);
314 }
315 return 0;
316 }
317
board_init_lin_pins(LIN_Type * ptr)318 void board_init_lin_pins(LIN_Type *ptr)
319 {
320 init_lin_pins(ptr);
321 }
322
board_init_lin_clock(LIN_Type * ptr)323 uint32_t board_init_lin_clock(LIN_Type *ptr)
324 {
325 if (ptr == HPM_LIN0) {
326 clock_add_to_group(clock_lin0, 0);
327 clock_set_source_divider(clock_lin0, clk_src_pll0_clk0, 20U); /* 20MHz */
328
329 return clock_get_frequency(clock_lin0);
330 }
331 return 0;
332 }
333
board_init_gpio_pins(void)334 void board_init_gpio_pins(void)
335 {
336 init_gpio_pins();
337 }
338
board_init_spi_pins(SPI_Type * ptr)339 void board_init_spi_pins(SPI_Type *ptr)
340 {
341 init_spi_pins(ptr);
342 }
343
board_init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)344 void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
345 {
346 init_spi_pins_with_gpio_as_cs(ptr);
347 gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
348 GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
349 }
350
board_write_spi_cs(uint32_t pin,uint8_t state)351 void board_write_spi_cs(uint32_t pin, uint8_t state)
352 {
353 gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
354 }
355
board_init_led_pins(void)356 void board_init_led_pins(void)
357 {
358 init_led_pins_as_gpio();
359 gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level());
360 gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level());
361 gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level());
362 }
363
board_led_toggle(void)364 void board_led_toggle(void)
365 {
366 #ifdef BOARD_LED_TOGGLE_RGB
367 static uint8_t i;
368 switch (i) {
369 case 1:
370 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
371 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_ON_LEVEL);
372 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
373 break;
374
375 case 2:
376 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
377 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
378 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_ON_LEVEL);
379 break;
380
381 case 0:
382 default:
383 gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_ON_LEVEL);
384 gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
385 gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
386 break;
387 }
388 i++;
389 i = i % 3;
390 #else
391 gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
392 #endif
393 }
394
board_led_write(uint8_t state)395 void board_led_write(uint8_t state)
396 {
397 gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
398 }
399
board_init_usb_pins(void)400 void board_init_usb_pins(void)
401 {
402 /* set pull-up for USBx ID pin */
403 init_usb_pins();
404
405 /* configure USBx ID pin as input function */
406 gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
407 }
408
board_get_usb_id_status(void)409 uint8_t board_get_usb_id_status(void)
410 {
411 return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
412 }
413
board_usb_vbus_ctrl(uint8_t usb_index,uint8_t level)414 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
415 {
416 (void) usb_index;
417 (void) level;
418 }
419
board_init_pmp(void)420 void board_init_pmp(void)
421 {
422 uint32_t start_addr;
423 uint32_t end_addr;
424 uint32_t length;
425 pmp_entry_t pmp_entry[16];
426 uint8_t index = 0;
427
428 /* Init noncachable memory */
429 extern uint32_t __noncacheable_start__[];
430 extern uint32_t __noncacheable_end__[];
431 start_addr = (uint32_t)__noncacheable_start__;
432 end_addr = (uint32_t)__noncacheable_end__;
433 length = end_addr - start_addr;
434 if (length > 0) {
435 /* Ensure the address and the length are power of 2 aligned */
436 assert((length & (length - 1U)) == 0U);
437 assert((start_addr & (length - 1U)) == 0U);
438 pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
439 pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
440 pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
441 pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
442 index++;
443 }
444
445 /* Init share memory */
446 extern uint32_t __share_mem_start__[];
447 extern uint32_t __share_mem_end__[];
448 start_addr = (uint32_t)__share_mem_start__;
449 end_addr = (uint32_t)__share_mem_end__;
450 length = end_addr - start_addr;
451 if (length > 0) {
452 /* Ensure the address and the length are power of 2 aligned */
453 assert((length & (length - 1U)) == 0U);
454 assert((start_addr & (length - 1U)) == 0U);
455 pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
456 pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
457 pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
458 pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
459 index++;
460 }
461
462 pmp_config(&pmp_entry[0], index);
463 }
464
board_init_clock(void)465 void board_init_clock(void)
466 {
467 uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
468 if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
469 /* Configure the External OSC ramp-up time: ~9ms */
470 pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
471
472 /* Select clock setting preset1 */
473 sysctl_clock_set_preset(HPM_SYSCTL, 2);
474 }
475 /* Add most Clocks to group 0 */
476 /* not open uart clock in this API, uart should configure pin function before opening clock */
477 clock_add_to_group(clock_cpu0, 0);
478 clock_add_to_group(clock_ahbp, 0);
479 clock_add_to_group(clock_axic, 0);
480 clock_add_to_group(clock_axis, 0);
481
482 clock_add_to_group(clock_mchtmr0, 0);
483 clock_add_to_group(clock_xpi0, 0);
484 clock_add_to_group(clock_gptmr0, 0);
485 clock_add_to_group(clock_gptmr1, 0);
486 clock_add_to_group(clock_gptmr2, 0);
487 clock_add_to_group(clock_gptmr3, 0);
488 clock_add_to_group(clock_i2c0, 0);
489 clock_add_to_group(clock_i2c1, 0);
490 clock_add_to_group(clock_i2c2, 0);
491 clock_add_to_group(clock_i2c3, 0);
492 clock_add_to_group(clock_lin0, 0);
493 clock_add_to_group(clock_lin1, 0);
494 clock_add_to_group(clock_lin2, 0);
495 clock_add_to_group(clock_lin3, 0);
496 clock_add_to_group(clock_spi0, 0);
497 clock_add_to_group(clock_spi1, 0);
498 clock_add_to_group(clock_spi2, 0);
499 clock_add_to_group(clock_spi3, 0);
500 clock_add_to_group(clock_can0, 0);
501 clock_add_to_group(clock_can1, 0);
502 clock_add_to_group(clock_can2, 0);
503 clock_add_to_group(clock_can3, 0);
504 clock_add_to_group(clock_ptpc, 0);
505 clock_add_to_group(clock_ref0, 0);
506 clock_add_to_group(clock_ref1, 0);
507 clock_add_to_group(clock_watchdog0, 0);
508 clock_add_to_group(clock_sdp, 0);
509 clock_add_to_group(clock_xdma, 0);
510 clock_add_to_group(clock_ram0, 0);
511 clock_add_to_group(clock_usb0, 0);
512 clock_add_to_group(clock_kman, 0);
513 clock_add_to_group(clock_gpio, 0);
514 clock_add_to_group(clock_mbx0, 0);
515 clock_add_to_group(clock_hdma, 0);
516 clock_add_to_group(clock_rng, 0);
517 clock_add_to_group(clock_mot0, 0);
518 clock_add_to_group(clock_mot1, 0);
519 clock_add_to_group(clock_mot2, 0);
520 clock_add_to_group(clock_mot3, 0);
521 clock_add_to_group(clock_acmp, 0);
522 clock_add_to_group(clock_synt, 0);
523 clock_add_to_group(clock_lmm0, 0);
524 clock_add_to_group(clock_lmm1, 0);
525
526 clock_add_to_group(clock_adc0, 0);
527 clock_add_to_group(clock_adc1, 0);
528 clock_add_to_group(clock_adc2, 0);
529
530 clock_add_to_group(clock_dac0, 0);
531 clock_add_to_group(clock_dac1, 0);
532
533 clock_add_to_group(clock_tsns, 0);
534 clock_add_to_group(clock_crc0, 0);
535 clock_add_to_group(clock_sdm0, 0);
536
537 /* Connect Group0 to CPU0 */
538 clock_connect_group_to_cpu(0, 0);
539
540 /* Add the CPU1 clock to Group1 */
541 clock_add_to_group(clock_mchtmr1, 1);
542
543 /* Connect Group1 to CPU1 */
544 clock_connect_group_to_cpu(1, 1);
545
546 /* Bump up DCDC voltage to 1275mv */
547 pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
548
549 /* Connect CAN2/CAN3 to pll0clk0*/
550 clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1);
551 clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1);
552
553 /* Configure CPU to 600MHz, AXI/AHB to 200MHz */
554 sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3);
555 /* Configure PLL1_CLK0 Post Divider to 1 */
556 pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0);
557 pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000);
558 clock_update_core_clock();
559
560 /* Configure mchtmr to 24MHz */
561 clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
562 clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
563 }
564
board_init_gptmr_clock(GPTMR_Type * ptr)565 uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
566 {
567 uint32_t freq = 0;
568
569 if (ptr == HPM_GPTMR0) {
570 clock_add_to_group(clock_gptmr0, 0);
571 clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
572 freq = clock_get_frequency(clock_gptmr0);
573 }
574 else if (ptr == HPM_GPTMR1) {
575 clock_add_to_group(clock_gptmr1, 0);
576 clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
577 freq = clock_get_frequency(clock_gptmr1);
578 }
579 else if (ptr == HPM_GPTMR2) {
580 clock_add_to_group(clock_gptmr2, 0);
581 clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
582 freq = clock_get_frequency(clock_gptmr2);
583 }
584 else if (ptr == HPM_GPTMR3) {
585 clock_add_to_group(clock_gptmr3, 0);
586 clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
587 freq = clock_get_frequency(clock_gptmr3);
588 }
589 else {
590 /* Invalid instance */
591 }
592 return freq;
593 }
594
board_init_adc12_clock(ADC16_Type * ptr)595 uint32_t board_init_adc12_clock(ADC16_Type *ptr)
596 {
597 uint32_t freq = 0;
598 switch ((uint32_t)ptr) {
599 case HPM_ADC0_BASE:
600 /* Configure the ADC clock to 200MHz */
601 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
602 clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
603 freq = clock_get_frequency(clock_adc0);
604 break;
605 case HPM_ADC1_BASE:
606 /* Configure the ADC clock to 200MHz */
607 clock_set_adc_source(clock_adc1, clk_adc_src_ana0);
608 clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
609 freq = clock_get_frequency(clock_adc1);
610 break;
611 case HPM_ADC2_BASE:
612 /* Configure the ADC clock to 200MHz */
613 clock_set_adc_source(clock_adc2, clk_adc_src_ana0);
614 clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
615 freq = clock_get_frequency(clock_adc2);
616 break;
617 default:
618 /* Invalid ADC instance */
619 break;
620 }
621
622 return freq;
623 }
624
board_init_adc16_clock(ADC16_Type * ptr,bool clk_src_ahb)625 uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb)
626 {
627 uint32_t freq = 0;
628
629 if (ptr == HPM_ADC0) {
630 if (clk_src_ahb) {
631 /* Configure the ADC clock from AHB (@200MHz by default)*/
632 clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
633 } else {
634 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
635 clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
636 clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U);
637 }
638
639 freq = clock_get_frequency(clock_adc0);
640 } else if (ptr == HPM_ADC1) {
641 if (clk_src_ahb) {
642 /* Configure the ADC clock from AHB (@200MHz by default)*/
643 clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
644 } else {
645 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
646 clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
647 clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U);
648 }
649
650 freq = clock_get_frequency(clock_adc1);
651 } else if (ptr == HPM_ADC2) {
652 if (clk_src_ahb) {
653 /* Configure the ADC clock from AHB (@200MHz by default)*/
654 clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
655 } else {
656 /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */
657 clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
658 clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U);
659 }
660
661 freq = clock_get_frequency(clock_adc2);
662 }
663
664 return freq;
665 }
666
board_init_dac_clock(DAC_Type * ptr,bool clk_src_ahb)667 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
668 {
669 uint32_t freq = 0;
670
671 if (ptr == HPM_DAC0) {
672 if (clk_src_ahb == true) {
673 /* Configure the DAC clock to 200MHz */
674 clock_set_dac_source(clock_dac0, clk_dac_src_ahb0);
675 } else {
676 /* Configure the DAC clock to 166MHz */
677 clock_set_dac_source(clock_dac0, clk_dac_src_ana3);
678 clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
679 }
680
681 freq = clock_get_frequency(clock_dac0);
682 } else if (ptr == HPM_DAC1) {
683 if (clk_src_ahb == true) {
684 /* Configure the DAC clock to 200MHz */
685 clock_set_dac_source(clock_dac1, clk_dac_src_ahb0);
686 } else {
687 /* Configure the DAC clock to 166MHz */
688 clock_set_dac_source(clock_dac1, clk_dac_src_ana4);
689 clock_set_source_divider(clock_ana4, clk_src_pll0_clk1, 2);
690 }
691
692 freq = clock_get_frequency(clock_dac1);
693 }
694
695 return freq;
696 }
697
board_init_can(MCAN_Type * ptr)698 void board_init_can(MCAN_Type *ptr)
699 {
700 init_can_pins(ptr);
701 }
702
board_init_can_clock(MCAN_Type * ptr)703 uint32_t board_init_can_clock(MCAN_Type *ptr)
704 {
705 uint32_t freq = 0;
706 if (ptr == HPM_MCAN0) {
707 /* Set the CAN0 peripheral clock to 8MHz */
708 clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5);
709 freq = clock_get_frequency(clock_can0);
710 } else if (ptr == HPM_MCAN1) {
711 /* Set the CAN1 peripheral clock to 8MHz */
712 clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5);
713 freq = clock_get_frequency(clock_can1);
714 } else if (ptr == HPM_MCAN2) {
715 /* Set the CAN2 peripheral clock to 8MHz */
716 clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 5);
717 freq = clock_get_frequency(clock_can2);
718 } else if (ptr == HPM_MCAN3) {
719 /* Set the CAN2 peripheral clock to 8MHz */
720 clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 5);
721 freq = clock_get_frequency(clock_can3);
722 } else {
723 /* Invalid CAN instance */
724 }
725 return freq;
726 }
727
board_init_adc16_pins(void)728 void board_init_adc16_pins(void)
729 {
730 init_adc_pins();
731 }
732
board_init_rgb_pwm_pins(void)733 void board_init_rgb_pwm_pins(void)
734 {
735 init_led_pins_as_pwm();
736 }
737
board_disable_output_rgb_led(uint8_t color)738 void board_disable_output_rgb_led(uint8_t color)
739 {
740 switch (color) {
741 case BOARD_RGB_RED:
742 pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
743 break;
744 case BOARD_RGB_GREEN:
745 pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
746 break;
747 case BOARD_RGB_BLUE:
748 pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
749 break;
750 default:
751 while (1) {
752 ;
753 }
754 }
755 }
756
board_enable_output_rgb_led(uint8_t color)757 void board_enable_output_rgb_led(uint8_t color)
758 {
759 switch (color) {
760 case BOARD_RGB_RED:
761 pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
762 break;
763 case BOARD_RGB_GREEN:
764 pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
765 break;
766 case BOARD_RGB_BLUE:
767 pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
768 break;
769 default:
770 while (1) {
771 ;
772 }
773 }
774 }
board_init_dac_pins(DAC_Type * ptr)775 void board_init_dac_pins(DAC_Type *ptr)
776 {
777 init_dac_pins(ptr);
778 }
779
board_init_uart_clock(UART_Type * ptr)780 uint32_t board_init_uart_clock(UART_Type *ptr)
781 {
782 uint32_t freq = 0U;
783 if (ptr == HPM_UART0) {
784 clock_set_source_divider(clock_uart0, clk_src_pll1_clk0, 6);
785 clock_add_to_group(clock_uart0, 0);
786 freq = clock_get_frequency(clock_uart0);
787 } else if (ptr == HPM_UART1) {
788 clock_set_source_divider(clock_uart1, clk_src_pll1_clk0, 6);
789 clock_add_to_group(clock_uart1, 0);
790 freq = clock_get_frequency(clock_uart1);
791 } else if (ptr == HPM_UART2) {
792 clock_set_source_divider(clock_uart2, clk_src_pll1_clk0, 6);
793 clock_add_to_group(clock_uart2, 0);
794 freq = clock_get_frequency(clock_uart2);
795 } else if (ptr == HPM_UART6) {
796 clock_set_source_divider(clock_uart6, clk_src_pll1_clk0, 6);
797 clock_add_to_group(clock_uart6, 0);
798 freq = clock_get_frequency(clock_uart6);
799 } else {
800 /* Not supported */
801 }
802 return freq;
803 }
804
board_init_pwm_clock(PWM_Type * ptr)805 uint32_t board_init_pwm_clock(PWM_Type *ptr)
806 {
807 uint32_t freq = 0;
808 if (ptr == HPM_PWM0) {
809 clock_add_to_group(clock_mot0, 0);
810 freq = clock_get_frequency(clock_mot0);
811 } else if (ptr == HPM_PWM1) {
812 clock_add_to_group(clock_mot1, 0);
813 freq = clock_get_frequency(clock_mot1);
814 } else if (ptr == HPM_PWM2) {
815 clock_add_to_group(clock_mot2, 0);
816 freq = clock_get_frequency(clock_mot2);
817 } else if (ptr == HPM_PWM3) {
818 clock_add_to_group(clock_mot3, 0);
819 freq = clock_get_frequency(clock_mot3);
820 } else {
821
822 }
823 return freq;
824 }
825